2019-05-29 08:18:05 -06:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-08-19 02:54:33 -06:00
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/*
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* Copyright(c) 2015 EZchip Technologies.
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*/
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#ifndef _PLAT_EZNPS_MTM_H
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#define _PLAT_EZNPS_MTM_H
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#include <plat/ctop.h>
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static inline void *nps_mtm_reg_addr(u32 cpu, u32 reg)
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{
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struct global_id gid;
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u32 core, blkid;
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gid.value = cpu;
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core = gid.core;
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blkid = (((core & 0x0C) << 2) | (core & 0x03));
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return nps_host_reg(cpu, blkid, reg);
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}
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#ifdef CONFIG_EZNPS_MTM_EXT
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#define NPS_CPU_TO_THREAD_NUM(cpu) \
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({ struct global_id gid; gid.value = cpu; gid.thread; })
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/* MTM registers */
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#define MTM_CFG(cpu) nps_mtm_reg_addr(cpu, 0x81)
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#define MTM_THR_INIT(cpu) nps_mtm_reg_addr(cpu, 0x92)
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#define MTM_THR_INIT_STS(cpu) nps_mtm_reg_addr(cpu, 0x93)
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#define get_thread(map) map.thread
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#define eznps_max_cpus 4096
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#define eznps_cpus_per_cluster 256
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void mtm_enable_core(unsigned int cpu);
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int mtm_enable_thread(int cpu);
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#else /* !CONFIG_EZNPS_MTM_EXT */
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#define get_thread(map) 0
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#define eznps_max_cpus 256
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#define eznps_cpus_per_cluster 16
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#define mtm_enable_core(cpu)
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#define mtm_enable_thread(cpu) 1
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#define NPS_CPU_TO_THREAD_NUM(cpu) 0
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#endif /* CONFIG_EZNPS_MTM_EXT */
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#endif /* _PLAT_EZNPS_MTM_H */
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