368 lines
11 KiB
C
368 lines
11 KiB
C
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* BSD LICENSE
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*
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* Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Support routines for v3+ hardware
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*/
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#include <linux/pci.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include "registers.h"
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#include "hw.h"
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#include "dma.h"
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#include "dma_v2.h"
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static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
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struct ioat_ring_ent *desc)
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{
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struct ioat_chan_common *chan = &ioat->base;
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struct pci_dev *pdev = chan->device->pdev;
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size_t len = desc->len;
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size_t offset = len - desc->hw->size;
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struct dma_async_tx_descriptor *tx = &desc->txd;
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enum dma_ctrl_flags flags = tx->flags;
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switch (desc->hw->ctl_f.op) {
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case IOAT_OP_COPY:
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ioat_dma_unmap(chan, flags, len, desc->hw);
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break;
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case IOAT_OP_FILL: {
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struct ioat_fill_descriptor *hw = desc->fill;
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if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
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ioat_unmap(pdev, hw->dst_addr - offset, len,
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PCI_DMA_FROMDEVICE, flags, 1);
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break;
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}
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default:
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dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
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__func__, desc->hw->ctl_f.op);
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}
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}
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static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
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{
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_ring_ent *desc;
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bool seen_current = false;
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u16 active;
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int i;
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dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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active = ioat2_ring_active(ioat);
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for (i = 0; i < active && !seen_current; i++) {
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struct dma_async_tx_descriptor *tx;
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prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
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desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
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dump_desc_dbg(ioat, desc);
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tx = &desc->txd;
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if (tx->cookie) {
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chan->completed_cookie = tx->cookie;
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ioat3_dma_unmap(ioat, desc);
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tx->cookie = 0;
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if (tx->callback) {
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tx->callback(tx->callback_param);
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tx->callback = NULL;
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}
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}
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if (tx->phys == phys_complete)
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seen_current = true;
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}
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ioat->tail += i;
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BUG_ON(!seen_current); /* no active descs have written a completion? */
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chan->last_completion = phys_complete;
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if (ioat->head == ioat->tail) {
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dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
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__func__);
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clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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}
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static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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unsigned long phys_complete;
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prefetch(chan->completion);
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if (!spin_trylock_bh(&chan->cleanup_lock))
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return;
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if (!ioat_cleanup_preamble(chan, &phys_complete)) {
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spin_unlock_bh(&chan->cleanup_lock);
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return;
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}
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if (!spin_trylock_bh(&ioat->ring_lock)) {
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spin_unlock_bh(&chan->cleanup_lock);
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return;
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}
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__cleanup(ioat, phys_complete);
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spin_unlock_bh(&ioat->ring_lock);
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spin_unlock_bh(&chan->cleanup_lock);
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}
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static void ioat3_cleanup_tasklet(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = (void *) data;
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ioat3_cleanup(ioat);
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writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
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}
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static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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unsigned long phys_complete;
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u32 status;
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status = ioat_chansts(chan);
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if (is_ioat_active(status) || is_ioat_idle(status))
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ioat_suspend(chan);
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while (is_ioat_active(status) || is_ioat_idle(status)) {
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status = ioat_chansts(chan);
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cpu_relax();
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}
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if (ioat_cleanup_preamble(chan, &phys_complete))
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__cleanup(ioat, phys_complete);
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__ioat2_restart_chan(ioat);
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}
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static void ioat3_timer_event(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = (void *) data;
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struct ioat_chan_common *chan = &ioat->base;
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spin_lock_bh(&chan->cleanup_lock);
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if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
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unsigned long phys_complete;
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u64 status;
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spin_lock_bh(&ioat->ring_lock);
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status = ioat_chansts(chan);
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/* when halted due to errors check for channel
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* programming errors before advancing the completion state
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*/
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if (is_ioat_halted(status)) {
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u32 chanerr;
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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BUG_ON(is_ioat_bug(chanerr));
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}
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/* if we haven't made progress and we have already
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* acknowledged a pending completion once, then be more
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* forceful with a restart
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*/
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if (ioat_cleanup_preamble(chan, &phys_complete))
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__cleanup(ioat, phys_complete);
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else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
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ioat3_restart_channel(ioat);
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else {
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set_bit(IOAT_COMPLETION_ACK, &chan->state);
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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}
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spin_unlock_bh(&ioat->ring_lock);
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} else {
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u16 active;
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/* if the ring is idle, empty, and oversized try to step
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* down the size
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*/
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spin_lock_bh(&ioat->ring_lock);
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active = ioat2_ring_active(ioat);
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if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
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reshape_ring(ioat, ioat->alloc_order-1);
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spin_unlock_bh(&ioat->ring_lock);
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/* keep shrinking until we get back to our minimum
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* default size
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*/
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if (ioat->alloc_order > ioat_get_alloc_order())
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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spin_unlock_bh(&chan->cleanup_lock);
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}
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static enum dma_status
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ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie,
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dma_cookie_t *done, dma_cookie_t *used)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
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return DMA_SUCCESS;
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ioat3_cleanup(ioat);
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return ioat_is_complete(c, cookie, done, used);
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}
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static struct dma_async_tx_descriptor *
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ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value,
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size_t len, unsigned long flags)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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struct ioat_ring_ent *desc;
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size_t total_len = len;
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struct ioat_fill_descriptor *fill;
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int num_descs;
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u64 src_data = (0x0101010101010101ULL) * (value & 0xff);
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u16 idx;
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int i;
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num_descs = ioat2_xferlen_to_descs(ioat, len);
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if (likely(num_descs) &&
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ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
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/* pass */;
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else
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return NULL;
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for (i = 0; i < num_descs; i++) {
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size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
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desc = ioat2_get_ring_ent(ioat, idx + i);
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fill = desc->fill;
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fill->size = xfer_size;
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fill->src_data = src_data;
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fill->dst_addr = dest;
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fill->ctl = 0;
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fill->ctl_f.op = IOAT_OP_FILL;
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len -= xfer_size;
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dest += xfer_size;
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dump_desc_dbg(ioat, desc);
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}
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desc->txd.flags = flags;
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desc->len = total_len;
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fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
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fill->ctl_f.compl_write = 1;
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dump_desc_dbg(ioat, desc);
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/* we leave the channel locked to ensure in order submission */
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return &desc->txd;
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}
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int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
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{
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struct pci_dev *pdev = device->pdev;
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struct dma_device *dma;
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struct dma_chan *c;
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struct ioat_chan_common *chan;
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int err;
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u16 dev_id;
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u32 cap;
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device->enumerate_channels = ioat2_enumerate_channels;
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device->cleanup_tasklet = ioat3_cleanup_tasklet;
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device->timer_fn = ioat3_timer_event;
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dma = &device->common;
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dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
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dma->device_issue_pending = ioat2_issue_pending;
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dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
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dma->device_free_chan_resources = ioat2_free_chan_resources;
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dma->device_is_tx_complete = ioat3_is_complete;
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cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
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if (cap & IOAT_CAP_FILL_BLOCK) {
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dma_cap_set(DMA_MEMSET, dma->cap_mask);
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dma->device_prep_dma_memset = ioat3_prep_memset_lock;
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}
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/* -= IOAT ver.3 workarounds =- */
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/* Write CHANERRMSK_INT with 3E07h to mask out the errors
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* that can cause stability issues for IOAT ver.3
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*/
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pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
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/* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
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* (workaround for spurious config parity error after restart)
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*/
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pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
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if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
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pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
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err = ioat_probe(device);
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if (err)
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return err;
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ioat_set_tcp_copy_break(262144);
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list_for_each_entry(c, &dma->channels, device_node) {
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chan = to_chan_common(c);
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writel(IOAT_DMA_DCA_ANY_CPU,
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chan->reg_base + IOAT_DCACTRL_OFFSET);
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}
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err = ioat_register(device);
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if (err)
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return err;
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if (dca)
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device->dca = ioat3_dca_init(pdev, device->reg_base);
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return 0;
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}
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