License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 08:07:57 -06:00
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// SPDX-License-Identifier: GPL-2.0
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2017-01-21 05:00:15 -07:00
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/*
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* Device Tree file for Cortina systems Gemini SoC
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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2017-05-24 02:43:21 -06:00
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#include <dt-bindings/clock/cortina,gemini-clock.h>
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#include <dt-bindings/reset/cortina,gemini-reset.h>
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2017-01-21 05:00:15 -07:00
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#include <dt-bindings/gpio/gpio.h>
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/ {
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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interrupt-parent = <&intcon>;
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flash@30000000 {
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compatible = "cortina,gemini-flash", "cfi-flash";
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syscon = <&syscon>;
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2017-07-05 08:59:33 -06:00
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pinctrl-names = "default";
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pinctrl-0 = <&pflash_default_pins>;
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2017-01-21 05:00:15 -07:00
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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syscon: syscon@40000000 {
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2017-04-13 08:09:53 -06:00
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compatible = "cortina,gemini-syscon",
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"syscon", "simple-mfd";
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2017-01-21 05:00:15 -07:00
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reg = <0x40000000 0x1000>;
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2017-04-20 13:43:38 -06:00
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#clock-cells = <1>;
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2017-04-13 08:09:53 -06:00
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#reset-cells = <1>;
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2017-01-21 05:00:15 -07:00
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&syscon>;
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/* GLOBAL_RESET register */
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offset = <0x0c>;
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/* RESET_GLOBAL | RESET_CPU1 */
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mask = <0xC0000000>;
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};
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2017-07-05 08:59:33 -06:00
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pinctrl {
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compatible = "cortina,gemini-pinctrl";
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regmap = <&syscon>;
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/* Hog the DRAM pins */
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pinctrl-names = "default";
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pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
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<&vcontrol_default_pins>;
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dram_default_pins: pinctrl-dram {
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mux {
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function = "dram";
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groups = "dramgrp";
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};
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};
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rtc_default_pins: pinctrl-rtc {
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mux {
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function = "rtc";
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groups = "rtcgrp";
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};
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};
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power_default_pins: pinctrl-power {
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mux {
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function = "power";
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groups = "powergrp";
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};
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};
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cir_default_pins: pinctrl-cir {
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mux {
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function = "cir";
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groups = "cirgrp";
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};
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};
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system_default_pins: pinctrl-system {
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mux {
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function = "system";
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groups = "systemgrp";
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};
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};
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vcontrol_default_pins: pinctrl-vcontrol {
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mux {
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function = "vcontrol";
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groups = "vcontrolgrp";
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};
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};
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ice_default_pins: pinctrl-ice {
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mux {
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function = "ice";
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groups = "icegrp";
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};
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};
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uart_default_pins: pinctrl-uart {
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mux {
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function = "uart";
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groups = "uartrxtxgrp";
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};
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};
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pflash_default_pins: pinctrl-pflash {
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mux {
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function = "pflash";
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groups = "pflashgrp";
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};
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};
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usb_default_pins: pinctrl-usb {
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mux {
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function = "usb";
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groups = "usbgrp";
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};
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};
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gmii_default_pins: pinctrl-gmii {
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2017-11-05 16:05:28 -07:00
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/*
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* Only activate GMAC0 by default since
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* GMAC1 will overlap with 8 GPIO lines
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* gpio2a, gpio2b. Overlay groups with
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* "gmii_gmac0_grp", "gmii_gmac1_grp" for
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* both ethernet interfaces.
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*/
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2017-07-05 08:59:33 -06:00
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mux {
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function = "gmii";
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2017-11-05 16:05:28 -07:00
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groups = "gmii_gmac0_grp";
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2017-07-05 08:59:33 -06:00
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};
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};
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pci_default_pins: pinctrl-pci {
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mux {
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function = "pci";
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groups = "pcigrp";
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};
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};
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sata_default_pins: pinctrl-sata {
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mux {
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function = "sata";
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groups = "satagrp";
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};
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};
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/* Activate both groups of pins for this state */
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sata_and_ide_pins: pinctrl-sata-ide {
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mux0 {
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function = "sata";
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groups = "satagrp";
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};
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mux1 {
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function = "ide";
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groups = "idegrp";
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};
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};
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2017-10-11 11:45:19 -06:00
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tvc_default_pins: pinctrl-tvc {
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mux {
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function = "tvc";
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groups = "tvcgrp";
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};
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};
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2017-07-05 08:59:33 -06:00
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};
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2017-01-21 05:00:15 -07:00
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};
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2017-01-22 15:34:38 -07:00
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watchdog@41000000 {
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2017-10-16 08:26:07 -06:00
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compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
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2017-01-22 15:34:38 -07:00
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reg = <0x41000000 0x1000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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2017-05-24 02:43:21 -06:00
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resets = <&syscon GEMINI_RESET_WDOG>;
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clocks = <&syscon GEMINI_CLK_APB>;
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2017-10-16 08:26:07 -06:00
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clock-names = "PCLK";
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2017-01-22 15:34:38 -07:00
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};
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2017-01-21 05:00:15 -07:00
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uart0: serial@42000000 {
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compatible = "ns16550a";
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reg = <0x42000000 0x100>;
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2017-05-24 02:43:21 -06:00
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resets = <&syscon GEMINI_RESET_UART>;
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clocks = <&syscon GEMINI_CLK_UART>;
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2017-01-21 05:00:15 -07:00
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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2017-07-05 08:59:33 -06:00
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pinctrl-names = "default";
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pinctrl-0 = <&uart_default_pins>;
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2017-01-21 05:00:15 -07:00
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reg-shift = <2>;
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};
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timer@43000000 {
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2017-04-20 13:43:38 -06:00
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compatible = "faraday,fttmr010";
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2017-01-21 05:00:15 -07:00
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reg = <0x43000000 0x1000>;
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interrupt-parent = <&intcon>;
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interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
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<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
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<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
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2017-05-24 02:43:21 -06:00
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resets = <&syscon GEMINI_RESET_TIMER>;
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2017-04-20 13:43:38 -06:00
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/* APB clock or RTC clock */
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2017-05-24 02:43:21 -06:00
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clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
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2017-04-20 13:43:38 -06:00
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clock-names = "PCLK", "EXTCLK";
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2017-01-21 05:00:15 -07:00
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syscon = <&syscon>;
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};
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rtc@45000000 {
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compatible = "cortina,gemini-rtc";
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reg = <0x45000000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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2017-05-24 02:43:21 -06:00
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resets = <&syscon GEMINI_RESET_RTC>;
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clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
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2017-04-20 13:43:38 -06:00
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clock-names = "PCLK", "EXTCLK";
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2017-07-05 08:59:33 -06:00
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pinctrl-names = "default";
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pinctrl-0 = <&rtc_default_pins>;
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2017-01-21 05:00:15 -07:00
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};
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2017-03-20 16:39:26 -06:00
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sata: sata@46000000 {
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compatible = "cortina,gemini-sata-bridge";
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reg = <0x46000000 0x100>;
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2017-05-24 02:43:21 -06:00
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resets = <&syscon GEMINI_RESET_SATA0>,
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<&syscon GEMINI_RESET_SATA1>;
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2017-03-20 16:39:26 -06:00
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reset-names = "sata0", "sata1";
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2017-05-24 02:43:21 -06:00
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clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
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<&syscon GEMINI_CLK_GATE_SATA1>;
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2017-03-20 16:39:26 -06:00
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clock-names = "SATA0_PCLK", "SATA1_PCLK";
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2017-07-05 08:59:33 -06:00
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/*
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* This defines the special "ide" state that needs
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* to be explicitly enabled to enable the IDE pins,
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* as these pins are normally used for other things.
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*/
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pinctrl-names = "default", "ide";
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pinctrl-0 = <&sata_default_pins>;
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pinctrl-1 = <&sata_and_ide_pins>;
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2017-03-20 16:39:26 -06:00
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syscon = <&syscon>;
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status = "disabled";
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};
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2017-01-21 05:00:15 -07:00
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intcon: interrupt-controller@48000000 {
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compatible = "faraday,ftintc010";
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reg = <0x48000000 0x1000>;
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2017-05-24 02:43:21 -06:00
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resets = <&syscon GEMINI_RESET_INTCON0>;
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2017-01-21 05:00:15 -07:00
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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2017-01-30 12:21:49 -07:00
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power-controller@4b000000 {
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compatible = "cortina,gemini-power-controller";
|
|
|
|
|
reg = <0x4b000000 0x100>;
|
|
|
|
|
interrupts = <26 IRQ_TYPE_EDGE_RISING>;
|
2017-07-05 08:59:33 -06:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&power_default_pins>;
|
2017-01-30 12:21:49 -07:00
|
|
|
};
|
|
|
|
|
|
2017-01-21 05:00:15 -07:00
|
|
|
gpio0: gpio@4d000000 {
|
2017-03-12 17:20:45 -06:00
|
|
|
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
|
2017-01-21 05:00:15 -07:00
|
|
|
reg = <0x4d000000 0x100>;
|
|
|
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
2017-05-24 02:43:21 -06:00
|
|
|
resets = <&syscon GEMINI_RESET_GPIO0>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_APB>;
|
2017-01-21 05:00:15 -07:00
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio1: gpio@4e000000 {
|
2017-03-12 17:20:45 -06:00
|
|
|
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
|
2017-01-21 05:00:15 -07:00
|
|
|
reg = <0x4e000000 0x100>;
|
|
|
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
2017-05-24 02:43:21 -06:00
|
|
|
resets = <&syscon GEMINI_RESET_GPIO1>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_APB>;
|
2017-01-21 05:00:15 -07:00
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio2: gpio@4f000000 {
|
2017-03-12 17:20:45 -06:00
|
|
|
compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
|
2017-01-21 05:00:15 -07:00
|
|
|
reg = <0x4f000000 0x100>;
|
|
|
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
2017-05-24 02:43:21 -06:00
|
|
|
resets = <&syscon GEMINI_RESET_GPIO2>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_APB>;
|
2017-01-21 05:00:15 -07:00
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
2017-01-28 13:15:15 -07:00
|
|
|
|
|
|
|
|
pci@50000000 {
|
|
|
|
|
compatible = "cortina,gemini-pci", "faraday,ftpci100";
|
|
|
|
|
/*
|
|
|
|
|
* The first 256 bytes in the IO range is actually used
|
|
|
|
|
* to configure the host bridge.
|
|
|
|
|
*/
|
|
|
|
|
reg = <0x50000000 0x100>;
|
2017-05-24 02:43:21 -06:00
|
|
|
resets = <&syscon GEMINI_RESET_PCI>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
|
2017-04-20 13:43:38 -06:00
|
|
|
clock-names = "PCLK", "PCICLK";
|
2017-07-05 08:59:33 -06:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pci_default_pins>;
|
2017-01-28 13:15:15 -07:00
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
|
/* PCI ranges mappings */
|
|
|
|
|
ranges =
|
|
|
|
|
/* 1MiB I/O space 0x50000000-0x500fffff */
|
|
|
|
|
<0x01000000 0 0 0x50000000 0 0x00100000>,
|
|
|
|
|
/* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
|
|
|
|
|
<0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
|
|
|
|
|
|
|
|
|
|
/* DMA ranges */
|
|
|
|
|
dma-ranges =
|
|
|
|
|
/* 128MiB at 0x00000000-0x07ffffff */
|
|
|
|
|
<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
|
|
|
|
|
/* 64MiB at 0x00000000-0x03ffffff */
|
|
|
|
|
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
|
|
|
|
|
/* 64MiB at 0x00000000-0x03ffffff */
|
|
|
|
|
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This PCI host bridge variant has a cascaded interrupt
|
|
|
|
|
* controller embedded in the host bridge.
|
|
|
|
|
*/
|
|
|
|
|
pci_intc: interrupt-controller {
|
|
|
|
|
interrupt-parent = <&intcon>;
|
|
|
|
|
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#address-cells = <0>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2017-04-01 11:55:48 -06:00
|
|
|
|
2017-11-05 16:05:28 -07:00
|
|
|
ethernet@60000000 {
|
|
|
|
|
compatible = "cortina,gemini-ethernet";
|
|
|
|
|
reg = <0x60000000 0x4000>, /* Global registers, queue */
|
|
|
|
|
<0x60004000 0x2000>, /* V-bit */
|
|
|
|
|
<0x60006000 0x2000>; /* A-bit */
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&gmii_default_pins>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
gmac0: ethernet-port@0 {
|
|
|
|
|
compatible = "cortina,gemini-ethernet-port";
|
|
|
|
|
reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
|
|
|
|
|
<0x6000a000 0x2000>; /* Port 0 GMAC */
|
|
|
|
|
interrupt-parent = <&intcon>;
|
|
|
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
resets = <&syscon GEMINI_RESET_GMAC0>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
|
|
|
|
|
clock-names = "PCLK";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gmac1: ethernet-port@1 {
|
|
|
|
|
compatible = "cortina,gemini-ethernet-port";
|
|
|
|
|
reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
|
|
|
|
|
<0x6000e000 0x2000>; /* Port 1 GMAC */
|
|
|
|
|
interrupt-parent = <&intcon>;
|
|
|
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
resets = <&syscon GEMINI_RESET_GMAC1>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
|
|
|
|
|
clock-names = "PCLK";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-20 16:39:26 -06:00
|
|
|
ata@63000000 {
|
|
|
|
|
compatible = "cortina,gemini-pata", "faraday,ftide010";
|
|
|
|
|
reg = <0x63000000 0x1000>;
|
|
|
|
|
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
2017-05-24 02:43:21 -06:00
|
|
|
resets = <&syscon GEMINI_RESET_IDE>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_IDE>;
|
2017-03-20 16:39:26 -06:00
|
|
|
clock-names = "PCLK";
|
|
|
|
|
sata = <&sata>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ata@63400000 {
|
|
|
|
|
compatible = "cortina,gemini-pata", "faraday,ftide010";
|
|
|
|
|
reg = <0x63400000 0x1000>;
|
|
|
|
|
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
|
2017-05-24 02:43:21 -06:00
|
|
|
resets = <&syscon GEMINI_RESET_IDE>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_IDE>;
|
2017-03-20 16:39:26 -06:00
|
|
|
clock-names = "PCLK";
|
|
|
|
|
sata = <&sata>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2017-04-01 11:55:48 -06:00
|
|
|
dma-controller@67000000 {
|
|
|
|
|
compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
|
|
|
|
|
/* Faraday Technology FTDMAC020 variant */
|
|
|
|
|
arm,primecell-periphid = <0x0003b080>;
|
|
|
|
|
reg = <0x67000000 0x1000>;
|
|
|
|
|
interrupts = <9 IRQ_TYPE_EDGE_RISING>;
|
2017-05-24 02:43:21 -06:00
|
|
|
resets = <&syscon GEMINI_RESET_DMAC>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_AHB>;
|
2017-04-01 11:55:48 -06:00
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
/* Bus interface AHB1 (AHB0) is totally tilted */
|
|
|
|
|
lli-bus-interface-ahb2;
|
|
|
|
|
mem-bus-interface-ahb2;
|
|
|
|
|
memcpy-burst-size = <256>;
|
|
|
|
|
memcpy-bus-width = <32>;
|
|
|
|
|
#dma-cells = <2>;
|
|
|
|
|
};
|
2017-10-11 11:45:19 -06:00
|
|
|
|
|
|
|
|
display-controller@6a000000 {
|
|
|
|
|
compatible = "cortina,gemini-tvc", "faraday,tve200";
|
|
|
|
|
reg = <0x6a000000 0x1000>;
|
|
|
|
|
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
resets = <&syscon GEMINI_RESET_TVC>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_TVC>,
|
|
|
|
|
<&syscon GEMINI_CLK_TVC>;
|
|
|
|
|
clock-names = "PCLK", "TVE";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&tvc_default_pins>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2017-04-21 12:50:22 -06:00
|
|
|
|
|
|
|
|
usb@68000000 {
|
|
|
|
|
compatible = "cortina,gemini-usb", "faraday,fotg210";
|
|
|
|
|
reg = <0x68000000 0x1000>;
|
|
|
|
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
resets = <&syscon GEMINI_RESET_USB0>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_USB0>;
|
|
|
|
|
clock-names = "PCLK";
|
|
|
|
|
/*
|
|
|
|
|
* This will claim pins for USB0 and USB1 at the same
|
|
|
|
|
* time as they are using some common pins. If you for
|
|
|
|
|
* some reason have a system using USB1 at 96000000 but
|
|
|
|
|
* NOT using USB0 at 68000000 you wll have to add the
|
|
|
|
|
* usb_default_pins to the USB controller at 96000000
|
|
|
|
|
* in your .dts for the board.
|
|
|
|
|
*/
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&usb_default_pins>;
|
|
|
|
|
syscon = <&syscon>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@69000000 {
|
|
|
|
|
compatible = "cortina,gemini-usb", "faraday,fotg210";
|
|
|
|
|
reg = <0x69000000 0x1000>;
|
|
|
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
resets = <&syscon GEMINI_RESET_USB1>;
|
|
|
|
|
clocks = <&syscon GEMINI_CLK_GATE_USB1>;
|
|
|
|
|
clock-names = "PCLK";
|
|
|
|
|
syscon = <&syscon>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2017-01-21 05:00:15 -07:00
|
|
|
};
|
|
|
|
|
};
|