2008-05-19 11:47:05 -06:00
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/*
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* QUICC Engine GPIOs
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*
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* Copyright (c) MontaVista Software, Inc. 2008.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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2008-06-11 17:42:14 -06:00
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#include <linux/init.h>
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2008-05-19 11:47:05 -06:00
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#include <linux/spinlock.h>
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2008-12-03 12:27:38 -07:00
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#include <linux/err.h>
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2008-05-19 11:47:05 -06:00
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2011-05-27 08:46:24 -06:00
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#include <linux/export.h>
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2008-05-19 11:47:05 -06:00
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#include <asm/qe.h>
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struct qe_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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2008-12-03 12:27:38 -07:00
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unsigned long pin_flags[QE_PIO_PINS];
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#define QE_PIN_REQUESTED 0
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2008-05-19 11:47:05 -06:00
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/* shadowed data register to clear/set bits safely */
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u32 cpdata;
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2008-12-03 12:27:38 -07:00
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/* saved_regs used to restore dedicated functions */
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struct qe_pio_regs saved_regs;
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2008-05-19 11:47:05 -06:00
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};
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static inline struct qe_gpio_chip *
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to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
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{
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return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
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}
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static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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qe_gc->cpdata = in_be32(®s->cpdata);
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2008-12-03 12:27:38 -07:00
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qe_gc->saved_regs.cpdata = qe_gc->cpdata;
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qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
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qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
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qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
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qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
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qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
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2008-05-19 11:47:05 -06:00
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}
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static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
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return in_be32(®s->cpdata) & pin_mask;
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}
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static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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struct qe_pio_regs __iomem *regs = mm_gc->regs;
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unsigned long flags;
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u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
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spin_lock_irqsave(&qe_gc->lock, flags);
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if (val)
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qe_gc->cpdata |= pin_mask;
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else
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qe_gc->cpdata &= ~pin_mask;
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out_be32(®s->cpdata, qe_gc->cpdata);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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return 0;
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}
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static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
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unsigned long flags;
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2009-08-18 15:20:44 -06:00
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qe_gpio_set(gc, gpio, val);
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2008-05-19 11:47:05 -06:00
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spin_lock_irqsave(&qe_gc->lock, flags);
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__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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return 0;
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}
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2008-12-03 12:27:38 -07:00
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struct qe_pin {
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/*
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* The qe_gpio_chip name is unfortunate, we should change that to
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* something like qe_pio_controller. Someday.
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*/
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struct qe_gpio_chip *controller;
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int num;
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};
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/**
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* qe_pin_request - Request a QE pin
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* @np: device node to get a pin from
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* @index: index of a pin in the device tree
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* Context: non-atomic
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*
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* This function return qe_pin so that you could use it with the rest of
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* the QE Pin Multiplexing API.
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*/
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struct qe_pin *qe_pin_request(struct device_node *np, int index)
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{
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struct qe_pin *qe_pin;
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2010-06-08 07:48:16 -06:00
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struct gpio_chip *gc;
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2008-12-03 12:27:38 -07:00
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struct of_mm_gpio_chip *mm_gc;
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struct qe_gpio_chip *qe_gc;
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int err;
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unsigned long flags;
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qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
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if (!qe_pin) {
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pr_debug("%s: can't allocate memory\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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|
2011-12-12 09:25:57 -07:00
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err = of_get_gpio(np, index);
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if (err < 0)
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goto err0;
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gc = gpio_to_chip(err);
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if (WARN_ON(!gc))
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2008-12-03 12:27:38 -07:00
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goto err0;
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2011-12-12 09:25:57 -07:00
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if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
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2008-12-03 12:27:38 -07:00
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pr_debug("%s: tried to get a non-qe pin\n", __func__);
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err = -EINVAL;
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2011-12-12 09:25:57 -07:00
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goto err0;
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2008-12-03 12:27:38 -07:00
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}
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2010-06-08 07:48:16 -06:00
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mm_gc = to_of_mm_gpio_chip(gc);
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2008-12-03 12:27:38 -07:00
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qe_gc = to_qe_gpio_chip(mm_gc);
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spin_lock_irqsave(&qe_gc->lock, flags);
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2011-12-12 09:25:57 -07:00
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err -= gc->base;
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2008-12-03 12:27:38 -07:00
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if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
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qe_pin->controller = qe_gc;
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qe_pin->num = err;
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err = 0;
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} else {
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err = -EBUSY;
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}
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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if (!err)
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return qe_pin;
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err0:
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kfree(qe_pin);
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pr_debug("%s failed with status %d\n", __func__, err);
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return ERR_PTR(err);
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}
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EXPORT_SYMBOL(qe_pin_request);
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/**
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* qe_pin_free - Free a pin
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function frees the qe_pin structure and makes a pin available
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* for further qe_pin_request() calls.
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*/
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void qe_pin_free(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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unsigned long flags;
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const int pin = qe_pin->num;
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spin_lock_irqsave(&qe_gc->lock, flags);
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test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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kfree(qe_pin);
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}
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EXPORT_SYMBOL(qe_pin_free);
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/**
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* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
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* This function resets a pin to a dedicated peripheral function that
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* has been set up by the firmware.
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*/
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void qe_pin_set_dedicated(struct qe_pin *qe_pin)
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{
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struct qe_gpio_chip *qe_gc = qe_pin->controller;
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struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
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struct qe_pio_regs *sregs = &qe_gc->saved_regs;
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int pin = qe_pin->num;
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u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
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u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
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bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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if (second_reg) {
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clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
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clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
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} else {
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clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
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clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
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}
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if (sregs->cpdata & mask1)
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qe_gc->cpdata |= mask1;
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else
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qe_gc->cpdata &= ~mask1;
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out_be32(®s->cpdata, qe_gc->cpdata);
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clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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}
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EXPORT_SYMBOL(qe_pin_set_dedicated);
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/**
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* qe_pin_set_gpio - Set a pin to the GPIO mode
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* @qe_pin: pointer to the qe_pin structure
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* Context: any
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*
|
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* This function sets a pin to the GPIO mode.
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*/
|
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|
void qe_pin_set_gpio(struct qe_pin *qe_pin)
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|
|
|
{
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|
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|
struct qe_gpio_chip *qe_gc = qe_pin->controller;
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struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
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unsigned long flags;
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spin_lock_irqsave(&qe_gc->lock, flags);
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/* Let's make it input by default, GPIO API is able to change that. */
|
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|
|
__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
|
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|
|
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|
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spin_unlock_irqrestore(&qe_gc->lock, flags);
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|
|
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}
|
|
|
|
EXPORT_SYMBOL(qe_pin_set_gpio);
|
|
|
|
|
2008-06-11 17:42:14 -06:00
|
|
|
static int __init qe_add_gpiochips(void)
|
2008-05-19 11:47:05 -06:00
|
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
|
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|
|
for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
|
|
|
|
int ret;
|
|
|
|
struct qe_gpio_chip *qe_gc;
|
|
|
|
struct of_mm_gpio_chip *mm_gc;
|
|
|
|
struct gpio_chip *gc;
|
|
|
|
|
|
|
|
qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
|
|
|
|
if (!qe_gc) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_init(&qe_gc->lock);
|
|
|
|
|
|
|
|
mm_gc = &qe_gc->mm_gc;
|
2010-06-08 07:48:16 -06:00
|
|
|
gc = &mm_gc->gc;
|
2008-05-19 11:47:05 -06:00
|
|
|
|
|
|
|
mm_gc->save_regs = qe_gpio_save_regs;
|
|
|
|
gc->ngpio = QE_PIO_PINS;
|
|
|
|
gc->direction_input = qe_gpio_dir_in;
|
|
|
|
gc->direction_output = qe_gpio_dir_out;
|
|
|
|
gc->get = qe_gpio_get;
|
|
|
|
gc->set = qe_gpio_set;
|
|
|
|
|
|
|
|
ret = of_mm_gpiochip_add(np, mm_gc);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
continue;
|
|
|
|
err:
|
|
|
|
pr_err("%s: registration failed with status %d\n",
|
|
|
|
np->full_name, ret);
|
|
|
|
kfree(qe_gc);
|
|
|
|
/* try others anyway */
|
|
|
|
}
|
2008-06-11 17:42:14 -06:00
|
|
|
return 0;
|
2008-05-19 11:47:05 -06:00
|
|
|
}
|
2008-06-11 17:42:14 -06:00
|
|
|
arch_initcall(qe_add_gpiochips);
|