2010-01-06 16:07:20 -07:00
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/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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This only implements the mac core functions for this chip.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/crc32.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2013-03-25 22:43:08 -06:00
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#include <linux/ethtool.h>
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2018-01-18 16:12:21 -07:00
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#include <net/dsa.h>
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2011-06-16 05:01:34 -06:00
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#include <asm/io.h>
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2016-06-24 07:16:24 -06:00
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#include "stmmac_pcs.h"
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2010-01-06 16:07:20 -07:00
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#include "dwmac1000.h"
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2018-01-18 16:12:21 -07:00
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static void dwmac1000_core_init(struct mac_device_info *hw,
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struct net_device *dev)
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2010-01-06 16:07:20 -07:00
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{
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2014-07-31 14:49:13 -06:00
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void __iomem *ioaddr = hw->pcsr;
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2010-01-06 16:07:20 -07:00
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u32 value = readl(ioaddr + GMAC_CONTROL);
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2018-01-18 16:12:21 -07:00
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int mtu = dev->mtu;
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2016-06-24 07:16:25 -06:00
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/* Configure GMAC core */
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2010-01-06 16:07:20 -07:00
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value |= GMAC_CORE_INIT;
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2016-06-24 07:16:25 -06:00
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2018-01-18 16:12:21 -07:00
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/* Clear ACS bit because Ethernet switch tagging formats such as
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* Broadcom tags can look like invalid LLC/SNAP packets and cause the
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* hardware to truncate packets on reception.
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*/
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if (netdev_uses_dsa(dev))
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value &= ~GMAC_CONTROL_ACS;
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2014-01-20 04:39:01 -07:00
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if (mtu > 1500)
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value |= GMAC_CONTROL_2K;
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if (mtu > 2000)
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value |= GMAC_CONTROL_JE;
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2016-06-24 07:16:26 -06:00
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if (hw->ps) {
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value |= GMAC_CONTROL_TE;
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2017-05-24 01:16:47 -06:00
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value &= ~hw->link.speed_mask;
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switch (hw->ps) {
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case SPEED_1000:
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value |= hw->link.speed1000;
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break;
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case SPEED_100:
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value |= hw->link.speed100;
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break;
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case SPEED_10:
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value |= hw->link.speed10;
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break;
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2016-06-24 07:16:26 -06:00
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}
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}
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2010-01-06 16:07:20 -07:00
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writel(value, ioaddr + GMAC_CONTROL);
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/* Mask GMAC interrupts */
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2016-06-24 07:16:25 -06:00
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value = GMAC_INT_DEFAULT_MASK;
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if (hw->pcs)
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value &= ~GMAC_INT_DISABLE_PCS;
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writel(value, ioaddr + GMAC_INT_MASK);
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2010-01-06 16:07:20 -07:00
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#ifdef STMMAC_VLAN_TAG_USED
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/* Tag detection without filtering */
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writel(0x0, ioaddr + GMAC_VLAN_TAG);
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#endif
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}
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2014-07-31 14:49:13 -06:00
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static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
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2010-09-16 21:23:40 -06:00
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{
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2014-07-31 14:49:13 -06:00
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void __iomem *ioaddr = hw->pcsr;
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2010-09-16 21:23:40 -06:00
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u32 value = readl(ioaddr + GMAC_CONTROL);
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2014-09-01 01:17:52 -06:00
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if (hw->rx_csum)
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value |= GMAC_CONTROL_IPC;
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else
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value &= ~GMAC_CONTROL_IPC;
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2010-09-16 21:23:40 -06:00
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writel(value, ioaddr + GMAC_CONTROL);
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value = readl(ioaddr + GMAC_CONTROL);
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return !!(value & GMAC_CONTROL_IPC);
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}
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2017-02-23 06:12:25 -07:00
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static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
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2010-01-06 16:07:20 -07:00
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{
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2014-07-31 14:49:13 -06:00
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void __iomem *ioaddr = hw->pcsr;
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2010-01-06 16:07:20 -07:00
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int i;
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2017-02-23 06:12:25 -07:00
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for (i = 0; i < 55; i++)
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reg_space[i] = readl(ioaddr + i * 4);
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2010-01-06 16:07:20 -07:00
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}
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2014-07-31 14:49:13 -06:00
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static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
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unsigned char *addr,
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2013-04-07 20:10:01 -06:00
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unsigned int reg_n)
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2010-01-06 16:07:20 -07:00
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{
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2014-07-31 14:49:13 -06:00
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void __iomem *ioaddr = hw->pcsr;
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2010-01-06 16:07:20 -07:00
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stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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2013-04-07 20:10:01 -06:00
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GMAC_ADDR_LOW(reg_n));
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2010-01-06 16:07:20 -07:00
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}
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2014-07-31 14:49:13 -06:00
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static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
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unsigned char *addr,
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2013-04-07 20:10:01 -06:00
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unsigned int reg_n)
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2010-01-06 16:07:20 -07:00
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{
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2014-07-31 14:49:13 -06:00
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void __iomem *ioaddr = hw->pcsr;
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2010-01-06 16:07:20 -07:00
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stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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2013-04-07 20:10:01 -06:00
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GMAC_ADDR_LOW(reg_n));
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2010-01-06 16:07:20 -07:00
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}
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2014-07-31 14:49:17 -06:00
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static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
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int mcbitslog2)
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{
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int numhashregs, regs;
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switch (mcbitslog2) {
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case 6:
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writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
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writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
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return;
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break;
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case 7:
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numhashregs = 4;
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break;
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case 8:
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numhashregs = 8;
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break;
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default:
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2016-08-26 12:35:25 -06:00
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pr_debug("STMMAC: err in setting multicast filter\n");
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2014-07-31 14:49:17 -06:00
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return;
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break;
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}
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for (regs = 0; regs < numhashregs; regs++)
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writel(mcfilterbits[regs],
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ioaddr + GMAC_EXTHASH_BASE + regs * 4);
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}
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static void dwmac1000_set_filter(struct mac_device_info *hw,
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struct net_device *dev)
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2010-01-06 16:07:20 -07:00
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{
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2013-04-07 20:10:01 -06:00
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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2010-01-06 16:07:20 -07:00
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unsigned int value = 0;
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2014-07-31 14:49:17 -06:00
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unsigned int perfect_addr_number = hw->unicast_filter_entries;
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2014-10-09 09:10:36 -06:00
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u32 mc_filter[8];
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2014-07-31 14:49:17 -06:00
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int mcbitslog2 = hw->mcast_bits_log2;
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2010-01-06 16:07:20 -07:00
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2013-07-02 06:12:36 -06:00
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pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
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netdev_mc_count(dev), netdev_uc_count(dev));
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2010-01-06 16:07:20 -07:00
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2014-07-31 14:49:14 -06:00
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memset(mc_filter, 0, sizeof(mc_filter));
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if (dev->flags & IFF_PROMISC) {
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2010-01-06 16:07:20 -07:00
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value = GMAC_FRAME_FILTER_PR;
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2014-07-31 14:49:14 -06:00
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} else if (dev->flags & IFF_ALLMULTI) {
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2010-01-06 16:07:20 -07:00
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value = GMAC_FRAME_FILTER_PM; /* pass all multi */
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2010-02-07 21:30:35 -07:00
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} else if (!netdev_mc_empty(dev)) {
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2010-04-01 15:22:57 -06:00
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struct netdev_hw_addr *ha;
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2010-01-06 16:07:20 -07:00
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/* Hash filter for multicast */
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value = GMAC_FRAME_FILTER_HMC;
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2010-04-01 15:22:57 -06:00
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netdev_for_each_mc_addr(ha, dev) {
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2014-07-31 14:49:17 -06:00
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/* The upper n bits of the calculated CRC are used to
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* index the contents of the hash table. The number of
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* bits used depends on the hardware configuration
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* selected at core configuration time.
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2013-04-07 20:10:01 -06:00
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*/
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2014-07-31 14:49:17 -06:00
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int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
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ETH_ALEN)) >>
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(32 - mcbitslog2);
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2010-01-06 16:07:20 -07:00
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/* The most significant bit determines the register to
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* use (H/L) while the other 5 bits determine the bit
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2013-04-07 20:10:01 -06:00
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* within the register.
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*/
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2010-01-06 16:07:20 -07:00
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mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
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}
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}
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2014-07-31 14:49:17 -06:00
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dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
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2012-05-13 16:18:41 -06:00
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2013-04-07 20:10:01 -06:00
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/* Handle multiple unicast addresses (perfect filtering) */
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2012-05-13 16:18:41 -06:00
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if (netdev_uc_count(dev) > perfect_addr_number)
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2014-07-31 14:49:17 -06:00
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/* Switch to promiscuous mode if more than unicast
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* addresses are requested than supported by hardware.
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2013-04-07 20:10:01 -06:00
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*/
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2010-01-06 16:07:20 -07:00
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value |= GMAC_FRAME_FILTER_PR;
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else {
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int reg = 1;
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struct netdev_hw_addr *ha;
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2010-01-25 14:36:10 -07:00
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netdev_for_each_uc_addr(ha, dev) {
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2014-10-09 09:10:36 -06:00
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stmmac_set_mac_addr(ioaddr, ha->addr,
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2014-07-31 14:49:13 -06:00
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GMAC_ADDR_HIGH(reg),
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GMAC_ADDR_LOW(reg));
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2010-01-25 14:36:10 -07:00
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reg++;
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2010-01-06 16:07:20 -07:00
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}
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}
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#ifdef FRAME_FILTER_DEBUG
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/* Enable Receive all mode (to debug filtering_fail errors) */
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value |= GMAC_FRAME_FILTER_RA;
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#endif
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writel(value, ioaddr + GMAC_FRAME_FILTER);
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}
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2014-07-31 14:49:13 -06:00
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static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
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2017-03-10 11:24:56 -07:00
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unsigned int fc, unsigned int pause_time,
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u32 tx_cnt)
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2010-01-06 16:07:20 -07:00
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{
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2014-07-31 14:49:13 -06:00
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void __iomem *ioaddr = hw->pcsr;
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2015-04-15 10:17:41 -06:00
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/* Set flow such that DZPQ in Mac Register 6 is 0,
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* and unicast pause detect is enabled.
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*/
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unsigned int flow = GMAC_FLOW_CTRL_UP;
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2010-01-06 16:07:20 -07:00
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2013-07-02 06:12:36 -06:00
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pr_debug("GMAC Flow-Control:\n");
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2010-01-06 16:07:20 -07:00
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if (fc & FLOW_RX) {
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2013-07-02 06:12:36 -06:00
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pr_debug("\tReceive Flow-Control ON\n");
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2010-01-06 16:07:20 -07:00
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flow |= GMAC_FLOW_CTRL_RFE;
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}
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if (fc & FLOW_TX) {
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2013-07-02 06:12:36 -06:00
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pr_debug("\tTransmit Flow-Control ON\n");
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2010-01-06 16:07:20 -07:00
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flow |= GMAC_FLOW_CTRL_TFE;
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}
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if (duplex) {
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2013-07-02 06:12:36 -06:00
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pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
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2010-01-06 16:07:20 -07:00
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flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
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}
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|
|
|
writel(flow, ioaddr + GMAC_FLOW_CTRL);
|
|
|
|
}
|
|
|
|
|
2014-07-31 14:49:13 -06:00
|
|
|
static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
|
2010-01-06 16:07:20 -07:00
|
|
|
{
|
2014-07-31 14:49:13 -06:00
|
|
|
void __iomem *ioaddr = hw->pcsr;
|
2010-01-06 16:07:20 -07:00
|
|
|
unsigned int pmt = 0;
|
|
|
|
|
2011-04-13 12:51:43 -06:00
|
|
|
if (mode & WAKE_MAGIC) {
|
2013-07-02 06:12:36 -06:00
|
|
|
pr_debug("GMAC: WOL Magic frame\n");
|
2010-01-06 16:07:20 -07:00
|
|
|
pmt |= power_down | magic_pkt_en;
|
2011-04-13 12:51:43 -06:00
|
|
|
}
|
|
|
|
if (mode & WAKE_UCAST) {
|
2013-07-02 06:12:36 -06:00
|
|
|
pr_debug("GMAC: WOL on global unicast\n");
|
2016-09-16 02:50:13 -06:00
|
|
|
pmt |= power_down | global_unicast | wake_up_frame_en;
|
2010-01-06 16:07:20 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
writel(pmt, ioaddr + GMAC_PMT);
|
|
|
|
}
|
|
|
|
|
2016-06-24 07:16:24 -06:00
|
|
|
/* RGMII or SMII interface */
|
|
|
|
static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
|
|
|
|
{
|
|
|
|
u32 status;
|
|
|
|
|
|
|
|
status = readl(ioaddr + GMAC_RGSMIIIS);
|
|
|
|
x->irq_rgmii_n++;
|
|
|
|
|
|
|
|
/* Check the link status */
|
|
|
|
if (status & GMAC_RGSMIIIS_LNKSTS) {
|
|
|
|
int speed_value;
|
|
|
|
|
|
|
|
x->pcs_link = 1;
|
|
|
|
|
|
|
|
speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
|
|
|
|
GMAC_RGSMIIIS_SPEED_SHIFT);
|
|
|
|
if (speed_value == GMAC_RGSMIIIS_SPEED_125)
|
|
|
|
x->pcs_speed = SPEED_1000;
|
|
|
|
else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
|
|
|
|
x->pcs_speed = SPEED_100;
|
|
|
|
else
|
|
|
|
x->pcs_speed = SPEED_10;
|
|
|
|
|
|
|
|
x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
|
|
|
|
|
|
|
|
pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
|
|
|
|
x->pcs_duplex ? "Full" : "Half");
|
|
|
|
} else {
|
|
|
|
x->pcs_link = 0;
|
|
|
|
pr_info("Link is Down\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-31 14:49:13 -06:00
|
|
|
static int dwmac1000_irq_status(struct mac_device_info *hw,
|
2013-03-25 22:43:07 -06:00
|
|
|
struct stmmac_extra_stats *x)
|
2010-01-06 16:07:20 -07:00
|
|
|
{
|
2014-07-31 14:49:13 -06:00
|
|
|
void __iomem *ioaddr = hw->pcsr;
|
2010-01-06 16:07:20 -07:00
|
|
|
u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
|
2017-01-27 05:24:43 -07:00
|
|
|
u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
|
2013-03-25 22:43:07 -06:00
|
|
|
int ret = 0;
|
2010-01-06 16:07:20 -07:00
|
|
|
|
2017-01-27 05:24:43 -07:00
|
|
|
/* Discard masked bits */
|
|
|
|
intr_status &= ~intr_mask;
|
|
|
|
|
2010-01-06 16:07:20 -07:00
|
|
|
/* Not used events (e.g. MMC interrupts) are not handled. */
|
2016-06-24 07:16:25 -06:00
|
|
|
if ((intr_status & GMAC_INT_STATUS_MMCTIS))
|
2013-03-25 22:43:07 -06:00
|
|
|
x->mmc_tx_irq_n++;
|
2016-06-24 07:16:25 -06:00
|
|
|
if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
|
2013-03-25 22:43:07 -06:00
|
|
|
x->mmc_rx_irq_n++;
|
2016-06-24 07:16:25 -06:00
|
|
|
if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
|
2013-03-25 22:43:07 -06:00
|
|
|
x->mmc_rx_csum_offload_irq_n++;
|
2016-06-24 07:16:25 -06:00
|
|
|
if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
|
2013-04-07 20:10:01 -06:00
|
|
|
/* clear the PMT bits 5 and 6 by reading the PMT status reg */
|
2010-01-06 16:07:20 -07:00
|
|
|
readl(ioaddr + GMAC_PMT);
|
2013-03-25 22:43:07 -06:00
|
|
|
x->irq_receive_pmt_irq_n++;
|
2010-01-06 16:07:20 -07:00
|
|
|
}
|
2016-06-24 07:16:24 -06:00
|
|
|
|
2016-06-24 07:16:25 -06:00
|
|
|
/* MAC tx/rx EEE LPI entry/exit interrupts */
|
|
|
|
if (intr_status & GMAC_INT_STATUS_LPIIS) {
|
2012-06-27 15:14:37 -06:00
|
|
|
/* Clean LPI interrupt by reading the Reg 12 */
|
2013-03-25 22:43:07 -06:00
|
|
|
ret = readl(ioaddr + LPI_CTRL_STATUS);
|
2012-06-27 15:14:37 -06:00
|
|
|
|
2013-07-02 06:12:36 -06:00
|
|
|
if (ret & LPI_CTRL_STATUS_TLPIEN)
|
2013-03-25 22:43:07 -06:00
|
|
|
x->irq_tx_path_in_lpi_mode_n++;
|
2013-07-02 06:12:36 -06:00
|
|
|
if (ret & LPI_CTRL_STATUS_TLPIEX)
|
2013-03-25 22:43:07 -06:00
|
|
|
x->irq_tx_path_exit_lpi_mode_n++;
|
2013-07-02 06:12:36 -06:00
|
|
|
if (ret & LPI_CTRL_STATUS_RLPIEN)
|
2013-03-25 22:43:07 -06:00
|
|
|
x->irq_rx_path_in_lpi_mode_n++;
|
2013-07-02 06:12:36 -06:00
|
|
|
if (ret & LPI_CTRL_STATUS_RLPIEX)
|
2013-03-25 22:43:07 -06:00
|
|
|
x->irq_rx_path_exit_lpi_mode_n++;
|
2012-06-27 15:14:37 -06:00
|
|
|
}
|
|
|
|
|
2016-06-24 07:16:24 -06:00
|
|
|
dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
|
|
|
|
|
|
|
|
if (intr_status & PCS_RGSMIIIS_IRQ)
|
|
|
|
dwmac1000_rgsmii(ioaddr, x);
|
2013-03-25 22:43:07 -06:00
|
|
|
|
|
|
|
return ret;
|
2012-06-27 15:14:37 -06:00
|
|
|
}
|
|
|
|
|
2017-01-09 05:35:08 -07:00
|
|
|
static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
|
|
|
|
bool en_tx_lpi_clockgating)
|
2012-06-27 15:14:37 -06:00
|
|
|
{
|
2014-07-31 14:49:13 -06:00
|
|
|
void __iomem *ioaddr = hw->pcsr;
|
2012-06-27 15:14:37 -06:00
|
|
|
u32 value;
|
|
|
|
|
2017-01-09 05:35:08 -07:00
|
|
|
/*TODO - en_tx_lpi_clockgating treatment */
|
|
|
|
|
2012-06-27 15:14:37 -06:00
|
|
|
/* Enable the link status receive on RGMII, SGMII ore SMII
|
|
|
|
* receive path and instruct the transmit to enter in LPI
|
2013-04-07 20:10:01 -06:00
|
|
|
* state.
|
|
|
|
*/
|
2012-06-27 15:14:37 -06:00
|
|
|
value = readl(ioaddr + LPI_CTRL_STATUS);
|
|
|
|
value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
|
|
|
|
writel(value, ioaddr + LPI_CTRL_STATUS);
|
|
|
|
}
|
|
|
|
|
2014-07-31 14:49:13 -06:00
|
|
|
static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
|
2012-06-27 15:14:37 -06:00
|
|
|
{
|
2014-07-31 14:49:13 -06:00
|
|
|
void __iomem *ioaddr = hw->pcsr;
|
2012-06-27 15:14:37 -06:00
|
|
|
u32 value;
|
|
|
|
|
|
|
|
value = readl(ioaddr + LPI_CTRL_STATUS);
|
|
|
|
value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
|
|
|
|
writel(value, ioaddr + LPI_CTRL_STATUS);
|
|
|
|
}
|
|
|
|
|
2014-07-31 14:49:13 -06:00
|
|
|
static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
|
2012-06-27 15:14:37 -06:00
|
|
|
{
|
2014-07-31 14:49:13 -06:00
|
|
|
void __iomem *ioaddr = hw->pcsr;
|
2012-06-27 15:14:37 -06:00
|
|
|
u32 value;
|
|
|
|
|
|
|
|
value = readl(ioaddr + LPI_CTRL_STATUS);
|
|
|
|
|
|
|
|
if (link)
|
|
|
|
value |= LPI_CTRL_STATUS_PLS;
|
|
|
|
else
|
|
|
|
value &= ~LPI_CTRL_STATUS_PLS;
|
|
|
|
|
|
|
|
writel(value, ioaddr + LPI_CTRL_STATUS);
|
|
|
|
}
|
|
|
|
|
2014-07-31 14:49:13 -06:00
|
|
|
static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
|
2012-06-27 15:14:37 -06:00
|
|
|
{
|
2014-07-31 14:49:13 -06:00
|
|
|
void __iomem *ioaddr = hw->pcsr;
|
2012-06-27 15:14:37 -06:00
|
|
|
int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
|
|
|
|
|
|
|
|
/* Program the timers in the LPI timer control register:
|
|
|
|
* LS: minimum time (ms) for which the link
|
|
|
|
* status from PHY should be ok before transmitting
|
|
|
|
* the LPI pattern.
|
|
|
|
* TW: minimum time (us) for which the core waits
|
|
|
|
* after it has stopped transmitting the LPI pattern.
|
|
|
|
*/
|
|
|
|
writel(value, ioaddr + LPI_TIMER_CTRL);
|
2010-01-06 16:07:20 -07:00
|
|
|
}
|
|
|
|
|
2016-06-24 07:16:24 -06:00
|
|
|
static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
|
|
|
|
bool loopback)
|
2013-03-25 22:43:08 -06:00
|
|
|
{
|
2016-06-24 07:16:24 -06:00
|
|
|
dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
|
2013-03-25 22:43:08 -06:00
|
|
|
}
|
|
|
|
|
2016-06-24 07:16:24 -06:00
|
|
|
static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
|
2013-03-25 22:43:08 -06:00
|
|
|
{
|
2016-06-24 07:16:24 -06:00
|
|
|
dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
|
|
|
|
}
|
2013-03-25 22:43:08 -06:00
|
|
|
|
2016-06-24 07:16:24 -06:00
|
|
|
static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
|
|
|
|
{
|
|
|
|
dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
|
2013-03-25 22:43:08 -06:00
|
|
|
}
|
|
|
|
|
2017-03-10 11:24:58 -07:00
|
|
|
static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
|
|
|
|
u32 rx_queues, u32 tx_queues)
|
2015-11-30 03:33:10 -07:00
|
|
|
{
|
|
|
|
u32 value = readl(ioaddr + GMAC_DEBUG);
|
|
|
|
|
|
|
|
if (value & GMAC_DEBUG_TXSTSFSTS)
|
|
|
|
x->mtl_tx_status_fifo_full++;
|
|
|
|
if (value & GMAC_DEBUG_TXFSTS)
|
|
|
|
x->mtl_tx_fifo_not_empty++;
|
|
|
|
if (value & GMAC_DEBUG_TWCSTS)
|
|
|
|
x->mmtl_fifo_ctrl++;
|
|
|
|
if (value & GMAC_DEBUG_TRCSTS_MASK) {
|
|
|
|
u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
|
|
|
|
>> GMAC_DEBUG_TRCSTS_SHIFT;
|
|
|
|
if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
|
|
|
|
x->mtl_tx_fifo_read_ctrl_write++;
|
|
|
|
else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
|
|
|
|
x->mtl_tx_fifo_read_ctrl_wait++;
|
|
|
|
else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
|
|
|
|
x->mtl_tx_fifo_read_ctrl_read++;
|
|
|
|
else
|
|
|
|
x->mtl_tx_fifo_read_ctrl_idle++;
|
|
|
|
}
|
|
|
|
if (value & GMAC_DEBUG_TXPAUSED)
|
|
|
|
x->mac_tx_in_pause++;
|
|
|
|
if (value & GMAC_DEBUG_TFCSTS_MASK) {
|
|
|
|
u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
|
|
|
|
>> GMAC_DEBUG_TFCSTS_SHIFT;
|
|
|
|
|
|
|
|
if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
|
|
|
|
x->mac_tx_frame_ctrl_xfer++;
|
|
|
|
else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
|
|
|
|
x->mac_tx_frame_ctrl_pause++;
|
|
|
|
else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
|
|
|
|
x->mac_tx_frame_ctrl_wait++;
|
|
|
|
else
|
|
|
|
x->mac_tx_frame_ctrl_idle++;
|
|
|
|
}
|
|
|
|
if (value & GMAC_DEBUG_TPESTS)
|
|
|
|
x->mac_gmii_tx_proto_engine++;
|
|
|
|
if (value & GMAC_DEBUG_RXFSTS_MASK) {
|
|
|
|
u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
|
|
|
|
>> GMAC_DEBUG_RRCSTS_SHIFT;
|
|
|
|
|
|
|
|
if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
|
|
|
|
x->mtl_rx_fifo_fill_level_full++;
|
|
|
|
else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
|
|
|
|
x->mtl_rx_fifo_fill_above_thresh++;
|
|
|
|
else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
|
|
|
|
x->mtl_rx_fifo_fill_below_thresh++;
|
|
|
|
else
|
|
|
|
x->mtl_rx_fifo_fill_level_empty++;
|
|
|
|
}
|
|
|
|
if (value & GMAC_DEBUG_RRCSTS_MASK) {
|
|
|
|
u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
|
|
|
|
GMAC_DEBUG_RRCSTS_SHIFT;
|
|
|
|
|
|
|
|
if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
|
|
|
|
x->mtl_rx_fifo_read_ctrl_flush++;
|
|
|
|
else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
|
|
|
|
x->mtl_rx_fifo_read_ctrl_read_data++;
|
|
|
|
else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
|
|
|
|
x->mtl_rx_fifo_read_ctrl_status++;
|
|
|
|
else
|
|
|
|
x->mtl_rx_fifo_read_ctrl_idle++;
|
|
|
|
}
|
|
|
|
if (value & GMAC_DEBUG_RWCSTS)
|
|
|
|
x->mtl_rx_fifo_ctrl_active++;
|
|
|
|
if (value & GMAC_DEBUG_RFCFCSTS_MASK)
|
|
|
|
x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
|
|
|
|
>> GMAC_DEBUG_RFCFCSTS_SHIFT;
|
|
|
|
if (value & GMAC_DEBUG_RPESTS)
|
|
|
|
x->mac_gmii_rx_proto_engine++;
|
|
|
|
}
|
|
|
|
|
2010-10-13 08:51:25 -06:00
|
|
|
static const struct stmmac_ops dwmac1000_ops = {
|
2010-01-06 16:07:20 -07:00
|
|
|
.core_init = dwmac1000_core_init,
|
2017-03-23 07:40:22 -06:00
|
|
|
.set_mac = stmmac_set_mac,
|
2012-04-03 22:33:21 -06:00
|
|
|
.rx_ipc = dwmac1000_rx_ipc_enable,
|
2010-01-06 16:07:20 -07:00
|
|
|
.dump_regs = dwmac1000_dump_regs,
|
|
|
|
.host_irq_status = dwmac1000_irq_status,
|
|
|
|
.set_filter = dwmac1000_set_filter,
|
|
|
|
.flow_ctrl = dwmac1000_flow_ctrl,
|
|
|
|
.pmt = dwmac1000_pmt,
|
|
|
|
.set_umac_addr = dwmac1000_set_umac_addr,
|
|
|
|
.get_umac_addr = dwmac1000_get_umac_addr,
|
2013-04-07 20:10:01 -06:00
|
|
|
.set_eee_mode = dwmac1000_set_eee_mode,
|
|
|
|
.reset_eee_mode = dwmac1000_reset_eee_mode,
|
|
|
|
.set_eee_timer = dwmac1000_set_eee_timer,
|
|
|
|
.set_eee_pls = dwmac1000_set_eee_pls,
|
2015-11-30 03:33:10 -07:00
|
|
|
.debug = dwmac1000_debug,
|
2016-06-24 07:16:24 -06:00
|
|
|
.pcs_ctrl_ane = dwmac1000_ctrl_ane,
|
|
|
|
.pcs_rane = dwmac1000_rane,
|
|
|
|
.pcs_get_adv_lp = dwmac1000_get_adv_lp,
|
2010-01-06 16:07:20 -07:00
|
|
|
};
|
|
|
|
|
2014-07-31 14:49:17 -06:00
|
|
|
struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
|
2016-04-01 03:37:27 -06:00
|
|
|
int perfect_uc_entries,
|
|
|
|
int *synopsys_id)
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2010-01-06 16:07:20 -07:00
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{
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struct mac_device_info *mac;
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2011-09-01 15:51:40 -06:00
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u32 hwid = readl(ioaddr + GMAC_VERSION);
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2010-01-06 16:07:20 -07:00
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mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
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2010-07-21 19:16:48 -06:00
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if (!mac)
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return NULL;
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2010-01-06 16:07:20 -07:00
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2014-07-31 14:49:13 -06:00
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mac->pcsr = ioaddr;
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2014-07-31 14:49:17 -06:00
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mac->multicast_filter_bins = mcbins;
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mac->unicast_filter_entries = perfect_uc_entries;
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mac->mcast_bits_log2 = 0;
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if (mac->multicast_filter_bins)
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mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
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2010-01-06 16:07:20 -07:00
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mac->mac = &dwmac1000_ops;
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mac->dma = &dwmac1000_dma_ops;
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mac->link.duplex = GMAC_CONTROL_DM;
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2017-05-24 01:16:47 -06:00
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mac->link.speed10 = GMAC_CONTROL_PS;
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mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
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mac->link.speed1000 = 0;
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mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
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2010-01-06 16:07:20 -07:00
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mac->mii.addr = GMAC_MII_ADDR;
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mac->mii.data = GMAC_MII_DATA;
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2016-12-01 08:19:41 -07:00
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mac->mii.addr_shift = 11;
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mac->mii.addr_mask = 0x0000F800;
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mac->mii.reg_shift = 6;
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mac->mii.reg_mask = 0x000007C0;
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mac->mii.clk_csr_shift = 2;
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2016-12-23 03:15:59 -07:00
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mac->mii.clk_csr_mask = GENMASK(5, 2);
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2016-04-01 03:37:27 -06:00
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/* Get and dump the chip ID */
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*synopsys_id = stmmac_get_synopsys_id(hwid);
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2010-01-06 16:07:20 -07:00
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return mac;
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}
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