2019-06-02 23:44:50 -06:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-03-05 04:49:26 -07:00
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/*
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2016-04-27 10:47:00 -06:00
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* Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
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2012-03-05 04:49:26 -07:00
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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2015-02-20 06:53:13 -07:00
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#ifndef __ASM_ASSEMBLER_H
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#define __ASM_ASSEMBLER_H
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2018-12-07 11:08:16 -07:00
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#include <asm-generic/export.h>
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2016-04-27 10:47:00 -06:00
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#include <asm/asm-offsets.h>
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2016-06-28 11:07:29 -06:00
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#include <asm/cpufeature.h>
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2019-02-26 11:43:41 -07:00
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#include <asm/cputype.h>
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2017-10-25 03:04:32 -06:00
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#include <asm/debug-monitors.h>
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2016-04-27 10:47:10 -06:00
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#include <asm/page.h>
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2016-04-27 10:47:00 -06:00
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#include <asm/pgtable-hwdef.h>
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2012-03-05 04:49:26 -07:00
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#include <asm/ptrace.h>
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arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 12:04:06 -06:00
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#include <asm/thread_info.h>
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2012-03-05 04:49:26 -07:00
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2017-11-02 06:12:34 -06:00
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.macro save_and_disable_daif, flags
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mrs \flags, daif
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msr daifset, #0xf
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.endm
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.macro disable_daif
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msr daifset, #0xf
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.endm
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.macro enable_daif
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msr daifclr, #0xf
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.endm
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.macro restore_daif, flags:req
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msr daif, \flags
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.endm
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2017-11-02 06:12:39 -06:00
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/* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */
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.macro inherit_daif, pstate:req, tmp:req
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and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
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msr daif, \tmp
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.endm
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2017-11-02 06:12:41 -06:00
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/* IRQ is the lowest priority flag, unconditionally unmask the rest. */
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.macro enable_da_f
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msr daifclr, #(8 | 4 | 1)
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.endm
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2012-03-05 04:49:26 -07:00
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/*
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2019-01-31 07:58:40 -07:00
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* Save/restore interrupts.
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2012-03-05 04:49:26 -07:00
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*/
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2016-07-01 09:53:00 -06:00
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.macro save_and_disable_irq, flags
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mrs \flags, daif
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msr daifset, #2
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.endm
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.macro restore_irq, flags
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msr daif, \flags
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.endm
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2012-03-05 04:49:26 -07:00
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.macro enable_dbg
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msr daifclr, #8
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.endm
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arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 12:04:06 -06:00
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.macro disable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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2012-03-05 04:49:26 -07:00
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mrs \tmp, mdscr_el1
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2017-10-25 03:04:32 -06:00
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bic \tmp, \tmp, #DBG_MDSCR_SS
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2012-03-05 04:49:26 -07:00
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msr mdscr_el1, \tmp
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arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 12:04:06 -06:00
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isb // Synchronise with enable_dbg
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9990:
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2012-03-05 04:49:26 -07:00
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.endm
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2017-11-02 06:12:38 -06:00
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/* call with daif masked */
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arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 12:04:06 -06:00
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.macro enable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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2012-03-05 04:49:26 -07:00
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mrs \tmp, mdscr_el1
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2017-10-25 03:04:32 -06:00
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orr \tmp, \tmp, #DBG_MDSCR_SS
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2012-03-05 04:49:26 -07:00
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msr mdscr_el1, \tmp
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arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 12:04:06 -06:00
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9990:
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2012-03-05 04:49:26 -07:00
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.endm
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/*
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* SMP data memory barrier
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*/
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.macro smp_dmb, opt
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dmb \opt
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.endm
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2018-01-15 12:38:59 -07:00
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/*
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* RAS Error Synchronization barrier
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*/
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.macro esb
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hint #16
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.endm
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2018-02-05 08:34:16 -07:00
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/*
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* Value prediction barrier
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*/
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.macro csdb
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hint #20
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.endm
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2018-06-14 04:21:34 -06:00
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/*
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* Speculation barrier
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*/
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.macro sb
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alternative_if_not ARM64_HAS_SB
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dsb nsh
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isb
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alternative_else
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SB_BARRIER_INSN
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nop
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alternative_endif
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.endm
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2018-02-05 08:34:20 -07:00
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/*
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* Sanitise a 64-bit bounded index wrt speculation, returning zero if out
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* of bounds.
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*/
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.macro mask_nospec64, idx, limit, tmp
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sub \tmp, \idx, \limit
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bic \tmp, \tmp, \idx
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and \idx, \idx, \tmp, asr #63
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csdb
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.endm
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2016-09-06 09:40:23 -06:00
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/*
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* NOP sequence
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*/
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.macro nops, num
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.rept \num
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nop
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.endr
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.endm
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2016-01-01 07:02:12 -07:00
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/*
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* Emit an entry into the exception table
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*/
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.macro _asm_extable, from, to
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.pushsection __ex_table, "a"
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.align 3
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.long (\from - .), (\to - .)
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.popsection
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.endm
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2012-03-05 04:49:26 -07:00
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#define USER(l, x...) \
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9999: x; \
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2016-01-01 07:02:12 -07:00
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_asm_extable 9999b, l
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2012-03-05 04:49:26 -07:00
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/*
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* Register aliases.
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*/
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lr .req x30 // link register
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2012-10-19 10:37:35 -06:00
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/*
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* Vector entry
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*/
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.macro ventry label
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.align 7
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b \label
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.endm
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2013-10-11 07:52:15 -06:00
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/*
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* Select code when configured for BE.
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*/
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define CPU_BE(code...) code
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#else
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#define CPU_BE(code...)
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#endif
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/*
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* Select code when configured for LE.
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*/
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define CPU_LE(code...)
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#else
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#define CPU_LE(code...) code
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#endif
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2013-10-11 07:52:13 -06:00
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/*
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* Define a macro that constructs a 64-bit value by concatenating two
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* 32-bit registers. Note that on big endian systems the order of the
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* registers is swapped.
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*/
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#ifndef CONFIG_CPU_BIG_ENDIAN
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.macro regs_to_64, rd, lbits, hbits
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#else
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.macro regs_to_64, rd, hbits, lbits
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#endif
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orr \rd, \lbits, \hbits, lsl #32
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.endm
|
2015-02-20 06:53:13 -07:00
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2015-03-04 11:45:38 -07:00
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|
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/*
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|
* Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
|
2018-03-10 07:59:29 -07:00
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* <symbol> is within the range +/- 4 GB of the PC.
|
2015-03-04 11:45:38 -07:00
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*/
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/*
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* @dst: destination register (64 bit wide)
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* @sym: name of the symbol
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*/
|
2017-01-11 07:54:53 -07:00
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|
|
.macro adr_l, dst, sym
|
2015-03-04 11:45:38 -07:00
|
|
|
adrp \dst, \sym
|
|
|
|
|
add \dst, \dst, :lo12:\sym
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* @dst: destination register (32 or 64 bit wide)
|
|
|
|
|
* @sym: name of the symbol
|
|
|
|
|
* @tmp: optional 64-bit scratch register to be used if <dst> is a
|
|
|
|
|
* 32-bit wide register, in which case it cannot be used to hold
|
|
|
|
|
* the address
|
|
|
|
|
*/
|
|
|
|
|
.macro ldr_l, dst, sym, tmp=
|
|
|
|
|
.ifb \tmp
|
|
|
|
|
adrp \dst, \sym
|
|
|
|
|
ldr \dst, [\dst, :lo12:\sym]
|
|
|
|
|
.else
|
|
|
|
|
adrp \tmp, \sym
|
|
|
|
|
ldr \dst, [\tmp, :lo12:\sym]
|
|
|
|
|
.endif
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* @src: source register (32 or 64 bit wide)
|
|
|
|
|
* @sym: name of the symbol
|
|
|
|
|
* @tmp: mandatory 64-bit scratch register to calculate the address
|
|
|
|
|
* while <src> needs to be preserved.
|
|
|
|
|
*/
|
|
|
|
|
.macro str_l, src, sym, tmp
|
|
|
|
|
adrp \tmp, \sym
|
|
|
|
|
str \src, [\tmp, :lo12:\sym]
|
|
|
|
|
.endm
|
|
|
|
|
|
2015-12-10 03:22:39 -07:00
|
|
|
/*
|
2018-03-10 07:59:29 -07:00
|
|
|
* @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP)
|
2015-12-10 03:22:39 -07:00
|
|
|
* @sym: The name of the per-cpu variable
|
|
|
|
|
* @tmp: scratch register
|
|
|
|
|
*/
|
2016-11-03 14:23:12 -06:00
|
|
|
.macro adr_this_cpu, dst, sym, tmp
|
2017-07-15 10:23:13 -06:00
|
|
|
adrp \tmp, \sym
|
|
|
|
|
add \dst, \tmp, #:lo12:\sym
|
2018-01-08 08:38:06 -07:00
|
|
|
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
|
2015-12-10 03:22:39 -07:00
|
|
|
mrs \tmp, tpidr_el1
|
2018-01-08 08:38:06 -07:00
|
|
|
alternative_else
|
|
|
|
|
mrs \tmp, tpidr_el2
|
|
|
|
|
alternative_endif
|
2016-11-03 14:23:12 -06:00
|
|
|
add \dst, \dst, \tmp
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
|
|
|
|
|
* @sym: The name of the per-cpu variable
|
|
|
|
|
* @tmp: scratch register
|
|
|
|
|
*/
|
|
|
|
|
.macro ldr_this_cpu dst, sym, tmp
|
|
|
|
|
adr_l \dst, \sym
|
2018-01-08 08:38:06 -07:00
|
|
|
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
|
2016-11-03 14:23:12 -06:00
|
|
|
mrs \tmp, tpidr_el1
|
2018-01-08 08:38:06 -07:00
|
|
|
alternative_else
|
|
|
|
|
mrs \tmp, tpidr_el2
|
|
|
|
|
alternative_endif
|
2016-11-03 14:23:12 -06:00
|
|
|
ldr \dst, [\dst, \tmp]
|
2015-12-10 03:22:39 -07:00
|
|
|
.endm
|
|
|
|
|
|
2016-04-27 10:47:00 -06:00
|
|
|
/*
|
|
|
|
|
* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
|
|
|
|
|
*/
|
|
|
|
|
.macro vma_vm_mm, rd, rn
|
|
|
|
|
ldr \rd, [\rn, #VMA_VM_MM]
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* mmid - get context id from mm pointer (mm->context.id)
|
|
|
|
|
*/
|
|
|
|
|
.macro mmid, rd, rn
|
|
|
|
|
ldr \rd, [\rn, #MM_CONTEXT_ID]
|
|
|
|
|
.endm
|
2016-09-09 07:07:16 -06:00
|
|
|
/*
|
2018-09-19 04:41:21 -06:00
|
|
|
* read_ctr - read CTR_EL0. If the system has mismatched register fields,
|
|
|
|
|
* provide the system wide safe value from arm64_ftr_reg_ctrel0.sys_val
|
2016-09-09 07:07:16 -06:00
|
|
|
*/
|
|
|
|
|
.macro read_ctr, reg
|
2018-09-19 04:41:21 -06:00
|
|
|
alternative_if_not ARM64_MISMATCHED_CACHE_TYPE
|
2016-09-09 07:07:16 -06:00
|
|
|
mrs \reg, ctr_el0 // read CTR
|
|
|
|
|
nop
|
|
|
|
|
alternative_else
|
|
|
|
|
ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
|
|
|
|
|
alternative_endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-04-27 10:47:00 -06:00
|
|
|
|
|
|
|
|
/*
|
2016-09-09 07:07:14 -06:00
|
|
|
* raw_dcache_line_size - get the minimum D-cache line size on this CPU
|
|
|
|
|
* from the CTR register.
|
2016-04-27 10:47:00 -06:00
|
|
|
*/
|
2016-09-09 07:07:14 -06:00
|
|
|
.macro raw_dcache_line_size, reg, tmp
|
2016-04-27 10:47:00 -06:00
|
|
|
mrs \tmp, ctr_el0 // read CTR
|
|
|
|
|
ubfm \tmp, \tmp, #16, #19 // cache line size encoding
|
|
|
|
|
mov \reg, #4 // bytes per word
|
|
|
|
|
lsl \reg, \reg, \tmp // actual cache line size
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
2016-09-09 07:07:14 -06:00
|
|
|
* dcache_line_size - get the safe D-cache line size across all CPUs
|
2016-04-27 10:47:00 -06:00
|
|
|
*/
|
2016-09-09 07:07:14 -06:00
|
|
|
.macro dcache_line_size, reg, tmp
|
2016-09-09 07:07:16 -06:00
|
|
|
read_ctr \tmp
|
|
|
|
|
ubfm \tmp, \tmp, #16, #19 // cache line size encoding
|
|
|
|
|
mov \reg, #4 // bytes per word
|
|
|
|
|
lsl \reg, \reg, \tmp // actual cache line size
|
2016-09-09 07:07:14 -06:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* raw_icache_line_size - get the minimum I-cache line size on this CPU
|
|
|
|
|
* from the CTR register.
|
|
|
|
|
*/
|
|
|
|
|
.macro raw_icache_line_size, reg, tmp
|
2016-04-27 10:47:00 -06:00
|
|
|
mrs \tmp, ctr_el0 // read CTR
|
|
|
|
|
and \tmp, \tmp, #0xf // cache line size encoding
|
|
|
|
|
mov \reg, #4 // bytes per word
|
|
|
|
|
lsl \reg, \reg, \tmp // actual cache line size
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-09-09 07:07:14 -06:00
|
|
|
/*
|
|
|
|
|
* icache_line_size - get the safe I-cache line size across all CPUs
|
|
|
|
|
*/
|
|
|
|
|
.macro icache_line_size, reg, tmp
|
2016-09-09 07:07:16 -06:00
|
|
|
read_ctr \tmp
|
|
|
|
|
and \tmp, \tmp, #0xf // cache line size encoding
|
|
|
|
|
mov \reg, #4 // bytes per word
|
|
|
|
|
lsl \reg, \reg, \tmp // actual cache line size
|
2016-09-09 07:07:14 -06:00
|
|
|
.endm
|
|
|
|
|
|
2016-04-27 10:47:00 -06:00
|
|
|
/*
|
2018-12-06 15:50:41 -07:00
|
|
|
* tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
|
2016-04-27 10:47:00 -06:00
|
|
|
*/
|
2018-12-06 15:50:41 -07:00
|
|
|
.macro tcr_set_t0sz, valreg, t0sz
|
|
|
|
|
bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
|
2016-04-27 10:47:00 -06:00
|
|
|
.endm
|
|
|
|
|
|
2017-12-13 10:07:17 -07:00
|
|
|
/*
|
|
|
|
|
* tcr_compute_pa_size - set TCR.(I)PS to the highest supported
|
|
|
|
|
* ID_AA64MMFR0_EL1.PARange value
|
|
|
|
|
*
|
|
|
|
|
* tcr: register with the TCR_ELx value to be updated
|
2018-01-15 08:23:50 -07:00
|
|
|
* pos: IPS or PS bitfield position
|
2017-12-13 10:07:17 -07:00
|
|
|
* tmp{0,1}: temporary registers
|
|
|
|
|
*/
|
|
|
|
|
.macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
|
|
|
|
|
mrs \tmp0, ID_AA64MMFR0_EL1
|
|
|
|
|
// Narrow PARange to fit the PS field in TCR_ELx
|
|
|
|
|
ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
|
|
|
|
|
mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
|
|
|
|
|
cmp \tmp0, \tmp1
|
|
|
|
|
csel \tmp0, \tmp1, \tmp0, hi
|
|
|
|
|
bfi \tcr, \tmp0, \pos, #3
|
2016-04-27 10:47:00 -06:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Macro to perform a data cache maintenance for the interval
|
|
|
|
|
* [kaddr, kaddr + size)
|
|
|
|
|
*
|
|
|
|
|
* op: operation passed to dc instruction
|
|
|
|
|
* domain: domain used in dsb instruciton
|
|
|
|
|
* kaddr: starting virtual address of the region
|
|
|
|
|
* size: size of the region
|
|
|
|
|
* Corrupts: kaddr, size, tmp1, tmp2
|
|
|
|
|
*/
|
2018-12-10 06:39:48 -07:00
|
|
|
.macro __dcache_op_workaround_clean_cache, op, kaddr
|
|
|
|
|
alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
|
|
|
|
|
dc \op, \kaddr
|
|
|
|
|
alternative_else
|
|
|
|
|
dc civac, \kaddr
|
|
|
|
|
alternative_endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-04-27 10:47:00 -06:00
|
|
|
.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
|
|
|
|
|
dcache_line_size \tmp1, \tmp2
|
|
|
|
|
add \size, \kaddr, \size
|
|
|
|
|
sub \tmp2, \tmp1, #1
|
|
|
|
|
bic \kaddr, \kaddr, \tmp2
|
2016-06-28 11:07:29 -06:00
|
|
|
9998:
|
2018-12-10 06:39:48 -07:00
|
|
|
.ifc \op, cvau
|
|
|
|
|
__dcache_op_workaround_clean_cache \op, \kaddr
|
|
|
|
|
.else
|
|
|
|
|
.ifc \op, cvac
|
|
|
|
|
__dcache_op_workaround_clean_cache \op, \kaddr
|
|
|
|
|
.else
|
|
|
|
|
.ifc \op, cvap
|
|
|
|
|
sys 3, c7, c12, 1, \kaddr // dc cvap
|
2016-06-28 11:07:29 -06:00
|
|
|
.else
|
2019-04-09 03:52:44 -06:00
|
|
|
.ifc \op, cvadp
|
|
|
|
|
sys 3, c7, c13, 1, \kaddr // dc cvadp
|
|
|
|
|
.else
|
2016-06-28 11:07:29 -06:00
|
|
|
dc \op, \kaddr
|
|
|
|
|
.endif
|
2018-12-10 06:39:48 -07:00
|
|
|
.endif
|
|
|
|
|
.endif
|
2019-04-09 03:52:44 -06:00
|
|
|
.endif
|
2016-04-27 10:47:00 -06:00
|
|
|
add \kaddr, \kaddr, \tmp1
|
|
|
|
|
cmp \kaddr, \size
|
|
|
|
|
b.lo 9998b
|
|
|
|
|
dsb \domain
|
|
|
|
|
.endm
|
|
|
|
|
|
2017-10-23 10:11:16 -06:00
|
|
|
/*
|
|
|
|
|
* Macro to perform an instruction cache maintenance for the interval
|
|
|
|
|
* [start, end)
|
|
|
|
|
*
|
|
|
|
|
* start, end: virtual addresses describing the region
|
|
|
|
|
* label: A label to branch to on user fault.
|
|
|
|
|
* Corrupts: tmp1, tmp2
|
|
|
|
|
*/
|
|
|
|
|
.macro invalidate_icache_by_line start, end, tmp1, tmp2, label
|
|
|
|
|
icache_line_size \tmp1, \tmp2
|
|
|
|
|
sub \tmp2, \tmp1, #1
|
|
|
|
|
bic \tmp2, \start, \tmp2
|
|
|
|
|
9997:
|
|
|
|
|
USER(\label, ic ivau, \tmp2) // invalidate I line PoU
|
|
|
|
|
add \tmp2, \tmp2, \tmp1
|
|
|
|
|
cmp \tmp2, \end
|
|
|
|
|
b.lo 9997b
|
|
|
|
|
dsb ish
|
|
|
|
|
isb
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-04-27 10:47:00 -06:00
|
|
|
/*
|
|
|
|
|
* reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
|
|
|
|
|
*/
|
|
|
|
|
.macro reset_pmuserenr_el0, tmpreg
|
2019-04-05 04:20:12 -06:00
|
|
|
mrs \tmpreg, id_aa64dfr0_el1
|
|
|
|
|
sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
|
2016-04-27 10:47:00 -06:00
|
|
|
cmp \tmpreg, #1 // Skip if no PMU present
|
|
|
|
|
b.lt 9000f
|
|
|
|
|
msr pmuserenr_el0, xzr // Disable PMU access from EL0
|
|
|
|
|
9000:
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-04-27 10:47:10 -06:00
|
|
|
/*
|
|
|
|
|
* copy_page - copy src to dest using temp registers t1-t8
|
|
|
|
|
*/
|
|
|
|
|
.macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
|
|
|
|
|
9998: ldp \t1, \t2, [\src]
|
|
|
|
|
ldp \t3, \t4, [\src, #16]
|
|
|
|
|
ldp \t5, \t6, [\src, #32]
|
|
|
|
|
ldp \t7, \t8, [\src, #48]
|
|
|
|
|
add \src, \src, #64
|
|
|
|
|
stnp \t1, \t2, [\dest]
|
|
|
|
|
stnp \t3, \t4, [\dest, #16]
|
|
|
|
|
stnp \t5, \t6, [\dest, #32]
|
|
|
|
|
stnp \t7, \t8, [\dest, #48]
|
|
|
|
|
add \dest, \dest, #64
|
|
|
|
|
tst \src, #(PAGE_SIZE - 1)
|
|
|
|
|
b.ne 9998b
|
|
|
|
|
.endm
|
|
|
|
|
|
2015-10-08 13:02:03 -06:00
|
|
|
/*
|
|
|
|
|
* Annotate a function as position independent, i.e., safe to be called before
|
|
|
|
|
* the kernel virtual mapping is activated.
|
|
|
|
|
*/
|
|
|
|
|
#define ENDPIPROC(x) \
|
|
|
|
|
.globl __pi_##x; \
|
|
|
|
|
.type __pi_##x, %function; \
|
|
|
|
|
.set __pi_##x, x; \
|
|
|
|
|
.size __pi_##x, . - x; \
|
|
|
|
|
ENDPROC(x)
|
|
|
|
|
|
2017-07-26 09:05:20 -06:00
|
|
|
/*
|
|
|
|
|
* Annotate a function as being unsuitable for kprobes.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_KPROBES
|
|
|
|
|
#define NOKPROBE(x) \
|
|
|
|
|
.pushsection "_kprobe_blacklist", "aw"; \
|
|
|
|
|
.quad x; \
|
|
|
|
|
.popsection;
|
|
|
|
|
#else
|
|
|
|
|
#define NOKPROBE(x)
|
|
|
|
|
#endif
|
2018-12-07 11:08:16 -07:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_KASAN
|
|
|
|
|
#define EXPORT_SYMBOL_NOKASAN(name)
|
|
|
|
|
#else
|
|
|
|
|
#define EXPORT_SYMBOL_NOKASAN(name) EXPORT_SYMBOL(name)
|
|
|
|
|
#endif
|
|
|
|
|
|
2015-12-26 05:48:02 -07:00
|
|
|
/*
|
|
|
|
|
* Emit a 64-bit absolute little endian symbol reference in a way that
|
|
|
|
|
* ensures that it will be resolved at build time, even when building a
|
|
|
|
|
* PIE binary. This requires cooperation from the linker script, which
|
|
|
|
|
* must emit the lo32/hi32 halves individually.
|
|
|
|
|
*/
|
|
|
|
|
.macro le64sym, sym
|
|
|
|
|
.long \sym\()_lo32
|
|
|
|
|
.long \sym\()_hi32
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-04-18 09:09:44 -06:00
|
|
|
/*
|
|
|
|
|
* mov_q - move an immediate constant into a 64-bit register using
|
|
|
|
|
* between 2 and 4 movz/movk instructions (depending on the
|
|
|
|
|
* magnitude and sign of the operand)
|
|
|
|
|
*/
|
|
|
|
|
.macro mov_q, reg, val
|
|
|
|
|
.if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
|
|
|
|
|
movz \reg, :abs_g1_s:\val
|
|
|
|
|
.else
|
|
|
|
|
.if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
|
|
|
|
|
movz \reg, :abs_g2_s:\val
|
|
|
|
|
.else
|
|
|
|
|
movz \reg, :abs_g3:\val
|
|
|
|
|
movk \reg, :abs_g2_nc:\val
|
|
|
|
|
.endif
|
|
|
|
|
movk \reg, :abs_g1_nc:\val
|
|
|
|
|
.endif
|
|
|
|
|
movk \reg, :abs_g0_nc:\val
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-07-01 09:53:00 -06:00
|
|
|
/*
|
2019-02-22 02:32:50 -07:00
|
|
|
* Return the current task_struct.
|
2016-07-01 09:53:00 -06:00
|
|
|
*/
|
2019-02-22 02:32:50 -07:00
|
|
|
.macro get_current_task, rd
|
2016-07-01 09:53:00 -06:00
|
|
|
mrs \rd, sp_el0
|
|
|
|
|
.endm
|
|
|
|
|
|
arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 15:50:39 -07:00
|
|
|
/*
|
|
|
|
|
* Offset ttbr1 to allow for 48-bit kernel VAs set with 52-bit PTRS_PER_PGD.
|
|
|
|
|
* orr is used as it can cover the immediate value (and is idempotent).
|
|
|
|
|
* In future this may be nop'ed out when dealing with 52-bit kernel VAs.
|
|
|
|
|
* ttbr: Value of ttbr to set, modified.
|
|
|
|
|
*/
|
|
|
|
|
.macro offset_ttbr1, ttbr
|
2018-12-10 07:15:15 -07:00
|
|
|
#ifdef CONFIG_ARM64_USER_VA_BITS_52
|
arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 15:50:39 -07:00
|
|
|
orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Perform the reverse of offset_ttbr1.
|
|
|
|
|
* bic is used as it can cover the immediate value and, in future, won't need
|
|
|
|
|
* to be nop'ed out when dealing with 52-bit kernel VAs.
|
|
|
|
|
*/
|
|
|
|
|
.macro restore_ttbr1, ttbr
|
2018-12-10 07:15:15 -07:00
|
|
|
#ifdef CONFIG_ARM64_USER_VA_BITS_52
|
arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 15:50:39 -07:00
|
|
|
bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2017-12-13 10:07:18 -07:00
|
|
|
/*
|
|
|
|
|
* Arrange a physical address in a TTBR register, taking care of 52-bit
|
|
|
|
|
* addresses.
|
|
|
|
|
*
|
|
|
|
|
* phys: physical address, preserved
|
|
|
|
|
* ttbr: returns the TTBR value
|
|
|
|
|
*/
|
2018-01-29 04:59:57 -07:00
|
|
|
.macro phys_to_ttbr, ttbr, phys
|
2017-12-13 10:07:18 -07:00
|
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
|
|
|
orr \ttbr, \phys, \phys, lsr #46
|
|
|
|
|
and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
|
|
|
|
|
#else
|
|
|
|
|
mov \ttbr, \phys
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2018-01-29 04:59:59 -07:00
|
|
|
.macro phys_to_pte, pte, phys
|
|
|
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
|
|
|
/*
|
|
|
|
|
* We assume \phys is 64K aligned and this is guaranteed by only
|
|
|
|
|
* supporting this configuration with 64K pages.
|
|
|
|
|
*/
|
|
|
|
|
orr \pte, \phys, \phys, lsr #36
|
|
|
|
|
and \pte, \pte, #PTE_ADDR_MASK
|
|
|
|
|
#else
|
|
|
|
|
mov \pte, \phys
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2018-02-06 15:22:50 -07:00
|
|
|
.macro pte_to_phys, phys, pte
|
|
|
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
|
|
|
ubfiz \phys, \pte, #(48 - 16 - 12), #16
|
|
|
|
|
bfxil \phys, \pte, #16, #32
|
|
|
|
|
lsl \phys, \phys, #16
|
|
|
|
|
#else
|
|
|
|
|
and \phys, \pte, #PTE_ADDR_MASK
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2019-02-26 11:43:41 -07:00
|
|
|
/*
|
|
|
|
|
* tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.
|
|
|
|
|
*/
|
|
|
|
|
.macro tcr_clear_errata_bits, tcr, tmp1, tmp2
|
|
|
|
|
#ifdef CONFIG_FUJITSU_ERRATUM_010001
|
|
|
|
|
mrs \tmp1, midr_el1
|
|
|
|
|
|
|
|
|
|
mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
|
|
|
|
|
and \tmp1, \tmp1, \tmp2
|
|
|
|
|
mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
|
|
|
|
|
cmp \tmp1, \tmp2
|
|
|
|
|
b.ne 10f
|
|
|
|
|
|
|
|
|
|
mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
|
|
|
|
|
bic \tcr, \tcr, \tmp2
|
|
|
|
|
10:
|
|
|
|
|
#endif /* CONFIG_FUJITSU_ERRATUM_010001 */
|
|
|
|
|
.endm
|
|
|
|
|
|
2018-01-29 04:59:52 -07:00
|
|
|
/**
|
|
|
|
|
* Errata workaround prior to disable MMU. Insert an ISB immediately prior
|
|
|
|
|
* to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
|
|
|
|
|
*/
|
|
|
|
|
.macro pre_disable_mmu_workaround
|
|
|
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
|
|
|
|
|
isb
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2018-03-29 07:13:22 -06:00
|
|
|
/*
|
|
|
|
|
* frame_push - Push @regcount callee saved registers to the stack,
|
|
|
|
|
* starting at x19, as well as x29/x30, and set x29 to
|
|
|
|
|
* the new value of sp. Add @extra bytes of stack space
|
|
|
|
|
* for locals.
|
|
|
|
|
*/
|
|
|
|
|
.macro frame_push, regcount:req, extra
|
|
|
|
|
__frame st, \regcount, \extra
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* frame_pop - Pop the callee saved registers from the stack that were
|
|
|
|
|
* pushed in the most recent call to frame_push, as well
|
|
|
|
|
* as x29/x30 and any extra stack space that may have been
|
|
|
|
|
* allocated.
|
|
|
|
|
*/
|
|
|
|
|
.macro frame_pop
|
|
|
|
|
__frame ld
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro __frame_regs, reg1, reg2, op, num
|
|
|
|
|
.if .Lframe_regcount == \num
|
|
|
|
|
\op\()r \reg1, [sp, #(\num + 1) * 8]
|
|
|
|
|
.elseif .Lframe_regcount > \num
|
|
|
|
|
\op\()p \reg1, \reg2, [sp, #(\num + 1) * 8]
|
|
|
|
|
.endif
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro __frame, op, regcount, extra=0
|
|
|
|
|
.ifc \op, st
|
|
|
|
|
.if (\regcount) < 0 || (\regcount) > 10
|
|
|
|
|
.error "regcount should be in the range [0 ... 10]"
|
|
|
|
|
.endif
|
|
|
|
|
.if ((\extra) % 16) != 0
|
|
|
|
|
.error "extra should be a multiple of 16 bytes"
|
|
|
|
|
.endif
|
|
|
|
|
.ifdef .Lframe_regcount
|
|
|
|
|
.if .Lframe_regcount != -1
|
|
|
|
|
.error "frame_push/frame_pop may not be nested"
|
|
|
|
|
.endif
|
|
|
|
|
.endif
|
|
|
|
|
.set .Lframe_regcount, \regcount
|
|
|
|
|
.set .Lframe_extra, \extra
|
|
|
|
|
.set .Lframe_local_offset, ((\regcount + 3) / 2) * 16
|
|
|
|
|
stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]!
|
|
|
|
|
mov x29, sp
|
|
|
|
|
.endif
|
|
|
|
|
|
|
|
|
|
__frame_regs x19, x20, \op, 1
|
|
|
|
|
__frame_regs x21, x22, \op, 3
|
|
|
|
|
__frame_regs x23, x24, \op, 5
|
|
|
|
|
__frame_regs x25, x26, \op, 7
|
|
|
|
|
__frame_regs x27, x28, \op, 9
|
|
|
|
|
|
|
|
|
|
.ifc \op, ld
|
|
|
|
|
.if .Lframe_regcount == -1
|
|
|
|
|
.error "frame_push/frame_pop may not be nested"
|
|
|
|
|
.endif
|
|
|
|
|
ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra
|
|
|
|
|
.set .Lframe_regcount, -1
|
|
|
|
|
.endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2018-03-29 07:13:23 -06:00
|
|
|
/*
|
|
|
|
|
* Check whether to yield to another runnable task from kernel mode NEON code
|
|
|
|
|
* (which runs with preemption disabled).
|
|
|
|
|
*
|
|
|
|
|
* if_will_cond_yield_neon
|
|
|
|
|
* // pre-yield patchup code
|
|
|
|
|
* do_cond_yield_neon
|
|
|
|
|
* // post-yield patchup code
|
|
|
|
|
* endif_yield_neon <label>
|
|
|
|
|
*
|
|
|
|
|
* where <label> is optional, and marks the point where execution will resume
|
|
|
|
|
* after a yield has been performed. If omitted, execution resumes right after
|
|
|
|
|
* the endif_yield_neon invocation. Note that the entire sequence, including
|
|
|
|
|
* the provided patchup code, will be omitted from the image if CONFIG_PREEMPT
|
|
|
|
|
* is not defined.
|
|
|
|
|
*
|
|
|
|
|
* As a convenience, in the case where no patchup code is required, the above
|
|
|
|
|
* sequence may be abbreviated to
|
|
|
|
|
*
|
|
|
|
|
* cond_yield_neon <label>
|
|
|
|
|
*
|
|
|
|
|
* Note that the patchup code does not support assembler directives that change
|
|
|
|
|
* the output section, any use of such directives is undefined.
|
|
|
|
|
*
|
|
|
|
|
* The yield itself consists of the following:
|
2019-05-14 02:34:19 -06:00
|
|
|
* - Check whether the preempt count is exactly 1 and a reschedule is also
|
|
|
|
|
* needed. If so, calling of preempt_enable() in kernel_neon_end() will
|
|
|
|
|
* trigger a reschedule. If it is not the case, yielding is pointless.
|
|
|
|
|
* - Disable and re-enable kernel mode NEON, and branch to the yield fixup
|
|
|
|
|
* code.
|
2018-03-29 07:13:23 -06:00
|
|
|
*
|
|
|
|
|
* This macro sequence may clobber all CPU state that is not guaranteed by the
|
|
|
|
|
* AAPCS to be preserved across an ordinary function call.
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*/
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.macro cond_yield_neon, lbl
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if_will_cond_yield_neon
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do_cond_yield_neon
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endif_yield_neon \lbl
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.endm
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.macro if_will_cond_yield_neon
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#ifdef CONFIG_PREEMPT
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2019-02-22 02:32:50 -07:00
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get_current_task x0
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2018-12-11 06:41:32 -07:00
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ldr x0, [x0, #TSK_TI_PREEMPT]
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sub x0, x0, #PREEMPT_DISABLE_OFFSET
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cbz x0, .Lyield_\@
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2018-03-29 07:13:23 -06:00
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/* fall through to endif_yield_neon */
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.subsection 1
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.Lyield_\@ :
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#else
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.section ".discard.cond_yield_neon", "ax"
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#endif
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.endm
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.macro do_cond_yield_neon
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bl kernel_neon_end
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bl kernel_neon_begin
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.endm
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.macro endif_yield_neon, lbl
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.ifnb \lbl
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b \lbl
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.else
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b .Lyield_out_\@
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.endif
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.previous
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.Lyield_out_\@ :
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.endm
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2015-02-20 06:53:13 -07:00
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#endif /* __ASM_ASSEMBLER_H */
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