2005-09-22 23:31:15 -06:00
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/*
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* EHCI HCD (Host Controller Driver) PCI Bus Glue.
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*
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* Copyright (c) 2000-2004 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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2012-11-01 09:13:04 -06:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include "ehci.h"
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#include "pci-quirks.h"
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#define DRIVER_DESC "EHCI PCI platform driver"
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static const char hcd_name[] = "ehci-pci";
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2005-09-22 23:31:15 -06:00
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2010-11-17 08:43:09 -07:00
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/* defined here to avoid adding to pci_ids.h for single instance use */
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#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
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2005-09-22 23:31:15 -06:00
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/*-------------------------------------------------------------------------*/
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2014-07-02 02:58:18 -06:00
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#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
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static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
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{
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return pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
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}
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/*
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* 0x84 is the offset of in/out threshold register,
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* and it is the same offset as the register of 'hostpc'.
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*/
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#define intel_quark_x1000_insnreg01 hostpc
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/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
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#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
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2005-09-22 23:31:15 -06:00
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2005-11-23 16:45:37 -07:00
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/* called after powerup, by probe or system-pm "wakeup" */
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static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
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{
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int retval;
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2006-01-24 08:15:30 -07:00
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/* we expect static quirk code to handle the "extended capabilities"
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* (currently just BIOS handoff) allowed starting with EHCI 0.96
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*/
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2005-11-23 16:45:37 -07:00
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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retval = pci_set_mwi(pdev);
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if (!retval)
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ehci_dbg(ehci, "MWI active\n");
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2014-07-02 02:58:18 -06:00
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/* Reset the threshold limit */
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if (is_intel_quark_x1000(pdev)) {
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/*
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* For the Intel QUARK X1000, raise the I/O threshold to the
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* maximum usable value in order to improve performance.
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*/
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ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
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ehci->regs->intel_quark_x1000_insnreg01);
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}
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2005-11-23 16:45:37 -07:00
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return 0;
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}
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2005-11-28 09:40:38 -07:00
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/* called during probe() after chip reset completes */
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static int ehci_pci_setup(struct usb_hcd *hcd)
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2005-09-22 23:31:15 -06:00
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{
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2005-11-23 16:45:32 -07:00
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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2005-09-22 23:31:15 -06:00
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u32 temp;
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2005-11-23 16:45:37 -07:00
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int retval;
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2005-09-22 23:31:15 -06:00
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2012-07-09 13:55:14 -06:00
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ehci->caps = hcd->regs;
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/*
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* ehci_init() causes memory for DMA transfers to be
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* allocated. Thus, any vendor-specific workarounds based on
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* limiting the type of memory used for DMA transfers must
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* happen before ehci_setup() is called.
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*
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* Most other workarounds can be done either before or after
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* init and reset; they are located here too.
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*/
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2006-12-14 12:54:08 -07:00
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_TOSHIBA_2:
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/* celleb's companion chip */
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if (pdev->device == 0x01b5) {
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
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ehci->big_endian_mmio = 1;
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#else
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ehci_warn(ehci,
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"unsupported big endian Toshiba quirk\n");
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#endif
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}
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break;
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2006-06-07 11:23:38 -06:00
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case PCI_VENDOR_ID_NVIDIA:
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/* NVidia reports that certain chips don't handle
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* QH, ITD, or SITD addresses above 2GB. (But TD,
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* data buffer, and periodic schedule are normal.)
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*/
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switch (pdev->device) {
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case 0x003c: /* MCP04 */
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case 0x005b: /* CK804 */
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case 0x00d8: /* CK8 */
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case 0x00e8: /* CK8S */
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if (pci_set_consistent_dma_mask(pdev,
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2009-04-06 20:01:16 -06:00
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DMA_BIT_MASK(31)) < 0)
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2006-06-07 11:23:38 -06:00
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ehci_warn(ehci, "can't enable NVidia "
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"workaround for >2GB RAM\n");
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break;
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2005-09-22 23:31:15 -06:00
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2012-07-09 13:55:14 -06:00
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/* Some NForce2 chips have problems with selective suspend;
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* fixed in newer silicon.
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2010-11-08 02:58:35 -07:00
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*/
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2012-07-09 13:55:14 -06:00
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case 0x0068:
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if (pdev->revision < 0xa4)
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ehci->no_selective_suspend = 1;
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break;
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}
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2010-04-06 19:26:03 -06:00
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break;
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2009-07-13 03:30:41 -06:00
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case PCI_VENDOR_ID_INTEL:
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2012-07-09 13:55:14 -06:00
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if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
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2010-11-17 08:43:09 -07:00
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hcd->has_tt = 1;
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2009-07-13 03:30:41 -06:00
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break;
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2005-11-23 16:45:32 -07:00
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case PCI_VENDOR_ID_TDI:
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2012-07-09 13:55:14 -06:00
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if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
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2008-04-03 16:02:56 -06:00
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hcd->has_tt = 1;
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2005-11-23 16:45:32 -07:00
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break;
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case PCI_VENDOR_ID_AMD:
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2011-02-28 23:57:05 -07:00
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/* AMD PLL quirk */
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if (usb_amd_find_chipset_info())
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ehci->amd_pll_fix = 1;
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2005-11-23 16:45:32 -07:00
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/* AMD8111 EHCI doesn't work, according to AMD errata */
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if (pdev->device == 0x7463) {
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ehci_info(ehci, "ignoring AMD8111 (errata)\n");
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2005-11-28 09:40:38 -07:00
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retval = -EIO;
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goto done;
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2005-11-23 16:45:32 -07:00
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}
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2010-11-21 22:15:52 -07:00
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2012-07-09 13:55:14 -06:00
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/*
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* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
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* read/write memory space which does not belong to it when
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* there is NULL pointer with T-bit set to 1 in the frame list
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* table. To avoid the issue, the frame list link pointer
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* should always contain a valid pointer to a inactive qh.
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2010-11-21 22:15:52 -07:00
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*/
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2012-07-09 13:55:14 -06:00
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if (pdev->device == 0x7808) {
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ehci->use_dummy_qh = 1;
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ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
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2005-09-22 23:31:15 -06:00
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}
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2005-11-23 16:45:32 -07:00
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break;
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2008-03-20 01:58:16 -06:00
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case PCI_VENDOR_ID_VIA:
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if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
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u8 tmp;
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/* The VT6212 defaults to a 1 usec EHCI sleep time which
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* hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
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* that sleep time use the conventional 10 usec.
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*/
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pci_read_config_byte(pdev, 0x4b, &tmp);
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if (tmp & 0x20)
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break;
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pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
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}
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break;
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2008-11-13 20:42:29 -07:00
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case PCI_VENDOR_ID_ATI:
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2011-02-28 23:57:05 -07:00
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/* AMD PLL quirk */
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if (usb_amd_find_chipset_info())
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ehci->amd_pll_fix = 1;
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2012-07-09 13:55:14 -06:00
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/*
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* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
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* read/write memory space which does not belong to it when
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* there is NULL pointer with T-bit set to 1 in the frame list
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* table. To avoid the issue, the frame list link pointer
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* should always contain a valid pointer to a inactive qh.
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*/
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if (pdev->device == 0x4396) {
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ehci->use_dummy_qh = 1;
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ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
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}
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2008-11-25 00:12:33 -07:00
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/* SB600 and old version of SB700 have a bug in EHCI controller,
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2008-11-13 20:42:29 -07:00
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* which causes usb devices lose response in some cases.
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*/
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2013-10-03 09:37:12 -06:00
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if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
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usb_amd_hang_symptom_quirk()) {
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u8 tmp;
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ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
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pci_read_config_byte(pdev, 0x53, &tmp);
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pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
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2008-11-13 20:42:29 -07:00
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}
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break;
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2011-10-12 08:39:14 -06:00
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case PCI_VENDOR_ID_NETMOS:
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/* MosChip frame-index-register bug */
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ehci_info(ehci, "applying MosChip frame-index workaround\n");
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ehci->frame_index_bug = 1;
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break;
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2005-11-23 16:45:32 -07:00
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}
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2005-09-22 23:31:15 -06:00
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2012-12-19 09:15:56 -07:00
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if (((temp >> 13) & 7) == 1) {
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u32 hcs_params = ehci_readl(ehci,
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&ehci->caps->hcs_params);
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temp &= 0x1fff;
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ehci->debug = hcd->regs + temp;
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temp = ehci_readl(ehci, &ehci->debug->control);
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ehci_info(ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(hcs_params),
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(temp & DBGP_ENABLED) ? " IN USE" : "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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|
2012-07-09 13:55:14 -06:00
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retval = ehci_setup(hcd);
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if (retval)
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return retval;
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|
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/* These workarounds need to be applied after ehci_setup() */
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_NEC:
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ehci->need_io_watchdog = 0;
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break;
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|
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case PCI_VENDOR_ID_INTEL:
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|
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ehci->need_io_watchdog = 0;
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|
|
break;
|
|
|
|
case PCI_VENDOR_ID_NVIDIA:
|
|
|
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switch (pdev->device) {
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|
|
/* MCP89 chips on the MacBookAir3,1 give EPROTO when
|
|
|
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* fetching device descriptors unless LPM is disabled.
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|
|
* There are also intermittent problems enumerating
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|
|
* devices with PPCD enabled.
|
|
|
|
*/
|
|
|
|
case 0x0d9d:
|
2012-10-31 11:12:11 -06:00
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|
ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
|
2012-07-09 13:55:14 -06:00
|
|
|
ehci->has_ppcd = 0;
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|
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ehci->command &= ~CMD_PPCEE;
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|
|
break;
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|
|
|
}
|
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|
break;
|
|
|
|
}
|
|
|
|
|
2005-09-22 23:31:15 -06:00
|
|
|
/* at least the Genesys GL880S needs fixup here */
|
|
|
|
temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
|
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|
|
temp &= 0x0f;
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|
|
if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
|
2005-11-23 16:45:32 -07:00
|
|
|
ehci_dbg(ehci, "bogus port configuration: "
|
2005-09-22 23:31:15 -06:00
|
|
|
"cc=%d x pcc=%d < ports=%d\n",
|
|
|
|
HCS_N_CC(ehci->hcs_params),
|
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|
|
HCS_N_PCC(ehci->hcs_params),
|
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|
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HCS_N_PORTS(ehci->hcs_params));
|
|
|
|
|
2005-11-23 16:45:32 -07:00
|
|
|
switch (pdev->vendor) {
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|
|
|
case 0x17a0: /* GENESYS */
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|
|
/* GL880S: should be PORTS=2 */
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|
|
temp |= (ehci->hcs_params & ~0xf);
|
|
|
|
ehci->hcs_params = temp;
|
|
|
|
break;
|
|
|
|
case PCI_VENDOR_ID_NVIDIA:
|
|
|
|
/* NF4: should be PCC=10 */
|
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|
|
break;
|
2005-09-22 23:31:15 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-11-23 16:45:32 -07:00
|
|
|
/* Serial Bus Release Number is at PCI 0x60 offset */
|
2012-01-06 05:33:28 -07:00
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_STMICRO
|
|
|
|
&& pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
|
2012-07-09 13:55:14 -06:00
|
|
|
; /* ConneXT has no sbrn register */
|
|
|
|
else
|
|
|
|
pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
|
2005-09-22 23:31:15 -06:00
|
|
|
|
2008-12-17 15:20:38 -07:00
|
|
|
/* Keep this around for a while just in case some EHCI
|
|
|
|
* implementation uses legacy PCI PM support. This test
|
|
|
|
* can be removed on 17 Dec 2009 if the dev_warn() hasn't
|
|
|
|
* been triggered by then.
|
2005-11-07 16:24:46 -07:00
|
|
|
*/
|
|
|
|
if (!device_can_wakeup(&pdev->dev)) {
|
|
|
|
u16 port_wake;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, 0x62, &port_wake);
|
2008-12-17 15:20:38 -07:00
|
|
|
if (port_wake & 0x0001) {
|
|
|
|
dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
|
2009-01-13 09:35:54 -07:00
|
|
|
device_set_wakeup_capable(&pdev->dev, 1);
|
2008-12-17 15:20:38 -07:00
|
|
|
}
|
2005-11-07 16:24:46 -07:00
|
|
|
}
|
2005-09-22 23:31:15 -06:00
|
|
|
|
2013-03-27 14:14:46 -06:00
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
2006-01-20 14:55:14 -07:00
|
|
|
if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
|
|
|
|
ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
|
|
|
|
#endif
|
|
|
|
|
2005-11-23 16:45:37 -07:00
|
|
|
retval = ehci_pci_reinit(ehci, pdev);
|
2005-11-28 09:40:38 -07:00
|
|
|
done:
|
|
|
|
return retval;
|
2005-09-22 23:31:15 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
/* suspend/resume, section 4.3 */
|
|
|
|
|
2005-11-23 16:45:28 -07:00
|
|
|
/* These routines rely on the PCI bus glue
|
2005-09-22 23:31:15 -06:00
|
|
|
* to handle powerdown and wakeup, and currently also on
|
|
|
|
* transceivers that don't need any software attention to set up
|
|
|
|
* the right sort of wakeup.
|
2005-11-23 16:45:28 -07:00
|
|
|
* Also they depend on separate root hub suspend/resume.
|
2005-09-22 23:31:15 -06:00
|
|
|
*/
|
|
|
|
|
2009-04-27 11:33:41 -06:00
|
|
|
static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
|
2005-09-22 23:31:15 -06:00
|
|
|
{
|
2005-11-23 16:45:32 -07:00
|
|
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
2005-11-23 16:45:37 -07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
|
2005-09-22 23:31:15 -06:00
|
|
|
|
2012-06-28 09:19:02 -06:00
|
|
|
if (ehci_resume(hcd, hibernated) != 0)
|
|
|
|
(void) ehci_pci_reinit(ehci, pdev);
|
2006-11-09 12:42:16 -07:00
|
|
|
return 0;
|
2005-09-22 23:31:15 -06:00
|
|
|
}
|
|
|
|
|
2012-11-01 09:13:04 -06:00
|
|
|
#else
|
2005-09-22 23:31:15 -06:00
|
|
|
|
2012-11-01 09:13:04 -06:00
|
|
|
#define ehci_suspend NULL
|
|
|
|
#define ehci_pci_resume NULL
|
|
|
|
#endif /* CONFIG_PM */
|
2005-09-22 23:31:15 -06:00
|
|
|
|
2012-11-01 09:13:04 -06:00
|
|
|
static struct hc_driver __read_mostly ehci_pci_hc_driver;
|
2005-09-22 23:31:15 -06:00
|
|
|
|
2013-04-22 10:44:56 -06:00
|
|
|
static const struct ehci_driver_overrides pci_overrides __initconst = {
|
2012-11-01 09:13:04 -06:00
|
|
|
.reset = ehci_pci_setup,
|
2005-09-22 23:31:15 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
|
|
|
|
/* PCI driver selection metadata; PCI hotplugging uses this */
|
|
|
|
static const struct pci_device_id pci_ids [] = { {
|
|
|
|
/* handle any USB 2.0 EHCI controller */
|
2006-04-09 12:07:35 -06:00
|
|
|
PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
|
2005-09-22 23:31:15 -06:00
|
|
|
.driver_data = (unsigned long) &ehci_pci_hc_driver,
|
2012-01-06 05:33:28 -07:00
|
|
|
}, {
|
|
|
|
PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
|
|
|
|
.driver_data = (unsigned long) &ehci_pci_hc_driver,
|
2005-09-22 23:31:15 -06:00
|
|
|
},
|
|
|
|
{ /* end: all zeroes */ }
|
|
|
|
};
|
2005-11-23 16:45:32 -07:00
|
|
|
MODULE_DEVICE_TABLE(pci, pci_ids);
|
2005-09-22 23:31:15 -06:00
|
|
|
|
|
|
|
/* pci driver glue; this is a "new style" PCI driver module */
|
|
|
|
static struct pci_driver ehci_pci_driver = {
|
|
|
|
.name = (char *) hcd_name,
|
|
|
|
.id_table = pci_ids,
|
|
|
|
|
|
|
|
.probe = usb_hcd_pci_probe,
|
|
|
|
.remove = usb_hcd_pci_remove,
|
2009-04-27 11:33:24 -06:00
|
|
|
.shutdown = usb_hcd_pci_shutdown,
|
2005-09-22 23:31:15 -06:00
|
|
|
|
2013-09-24 13:45:25 -06:00
|
|
|
#ifdef CONFIG_PM
|
2009-04-27 11:33:24 -06:00
|
|
|
.driver = {
|
|
|
|
.pm = &usb_hcd_pci_pm_ops
|
|
|
|
},
|
2005-09-22 23:31:15 -06:00
|
|
|
#endif
|
|
|
|
};
|
2012-11-01 09:13:04 -06:00
|
|
|
|
|
|
|
static int __init ehci_pci_init(void)
|
|
|
|
{
|
|
|
|
if (usb_disabled())
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
pr_info("%s: " DRIVER_DESC "\n", hcd_name);
|
|
|
|
|
2012-11-07 14:12:47 -07:00
|
|
|
ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
|
2012-11-01 09:13:04 -06:00
|
|
|
|
|
|
|
/* Entries for the PCI suspend/resume callbacks are special */
|
|
|
|
ehci_pci_hc_driver.pci_suspend = ehci_suspend;
|
|
|
|
ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
|
|
|
|
|
|
|
|
return pci_register_driver(&ehci_pci_driver);
|
|
|
|
}
|
|
|
|
module_init(ehci_pci_init);
|
|
|
|
|
|
|
|
static void __exit ehci_pci_cleanup(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&ehci_pci_driver);
|
|
|
|
}
|
|
|
|
module_exit(ehci_pci_cleanup);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
|
|
MODULE_AUTHOR("David Brownell");
|
|
|
|
MODULE_AUTHOR("Alan Stern");
|
|
|
|
MODULE_LICENSE("GPL");
|