2007-08-22 11:14:51 -06:00
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/*
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* arch/xtensa/mm/cache.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001-2006 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor
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* Marc Gauthier
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*
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*/
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#include <linux/init.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/bootmem.h>
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#include <linux/swap.h>
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#include <linux/pagemap.h>
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#include <asm/bootparam.h>
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#include <asm/mmu_context.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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//#define printd(x...) printk(x)
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#define printd(x...) do { } while(0)
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/*
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* Note:
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* The kernel provides one architecture bit PG_arch_1 in the page flags that
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* can be used for cache coherency.
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*
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* I$-D$ coherency.
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*
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* The Xtensa architecture doesn't keep the instruction cache coherent with
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* the data cache. We use the architecture bit to indicate if the caches
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* are coherent. The kernel clears this bit whenever a page is added to the
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* page cache. At that time, the caches might not be in sync. We, therefore,
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* define this flag as 'clean' if set.
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*
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* D-cache aliasing.
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*
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* With cache aliasing, we have to always flush the cache when pages are
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* unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
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* page.
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*
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*
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*
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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/*
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* Any time the kernel writes to a user page cache page, or it is about to
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* read from a page cache page this routine is called.
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*
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*/
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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/*
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* If we have a mapping but the page is not mapped to user-space
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* yet, we simply mark this page dirty and defer flushing the
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* caches until update_mmu().
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*/
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if (mapping && !mapping_mapped(mapping)) {
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if (!test_bit(PG_arch_1, &page->flags))
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set_bit(PG_arch_1, &page->flags);
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return;
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} else {
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unsigned long phys = page_to_phys(page);
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unsigned long temp = page->index << PAGE_SHIFT;
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unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
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unsigned long virt;
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/*
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* Flush the page in kernel space and user space.
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* Note that we can omit that step if aliasing is not
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* an issue, but we do have to synchronize I$ and D$
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* if we have a mapping.
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*/
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if (!alias && !mapping)
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return;
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__flush_invalidate_dcache_page((long)page_address(page));
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virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
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if (alias)
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__flush_invalidate_dcache_page_alias(virt, phys);
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if (mapping)
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__invalidate_icache_page_alias(virt, phys);
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}
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/* There shouldn't be an entry in the cache for this page anymore. */
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}
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/*
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* For now, flush the whole cache. FIXME??
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*/
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2012-11-28 17:53:51 -07:00
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void flush_cache_range(struct vm_area_struct* vma,
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2007-08-22 11:14:51 -06:00
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unsigned long start, unsigned long end)
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{
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__flush_invalidate_dcache_all();
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__invalidate_icache_all();
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}
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/*
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* Remove any entry in the cache for this page.
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*
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* Note that this function is only called for user pages, so use the
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* alias versions of the cache flush functions.
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*/
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void flush_cache_page(struct vm_area_struct* vma, unsigned long address,
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unsigned long pfn)
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2007-08-22 11:14:51 -06:00
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{
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/* Note that we have to use the 'alias' address to avoid multi-hit */
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unsigned long phys = page_to_phys(pfn_to_page(pfn));
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unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(virt, phys);
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__invalidate_icache_page_alias(virt, phys);
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}
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#endif
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void
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MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 09:40:18 -07:00
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update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
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2007-08-22 11:14:51 -06:00
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{
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MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 09:40:18 -07:00
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unsigned long pfn = pte_pfn(*ptep);
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2007-08-22 11:14:51 -06:00
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struct page *page;
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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/* Invalidate old entry in TLBs */
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invalidate_itlb_mapping(addr);
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invalidate_dtlb_mapping(addr);
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
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unsigned long paddr = (unsigned long) page_address(page);
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unsigned long phys = page_to_phys(page);
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2012-11-28 17:53:51 -07:00
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unsigned long tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
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2007-08-22 11:14:51 -06:00
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__flush_invalidate_dcache_page(paddr);
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2012-11-28 17:53:51 -07:00
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__flush_invalidate_dcache_page_alias(tmp, phys);
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__invalidate_icache_page_alias(tmp, phys);
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2007-08-22 11:14:51 -06:00
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clear_bit(PG_arch_1, &page->flags);
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}
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#else
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if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
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&& (vma->vm_flags & VM_EXEC) != 0) {
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2007-09-06 02:38:18 -06:00
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unsigned long paddr = (unsigned long) page_address(page);
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__flush_dcache_page(paddr);
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__invalidate_icache_page(paddr);
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2007-08-22 11:14:51 -06:00
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set_bit(PG_arch_1, &page->flags);
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}
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#endif
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}
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/*
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* access_process_vm() has called get_user_pages(), which has done a
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* flush_dcache_page() on the page.
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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2012-11-28 17:53:51 -07:00
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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2007-08-22 11:14:51 -06:00
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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unsigned long phys = page_to_phys(page);
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unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
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/* Flush and invalidate user page if aliased. */
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if (alias) {
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2012-11-28 17:53:51 -07:00
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unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(t, phys);
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2007-08-22 11:14:51 -06:00
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}
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/* Copy data */
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memcpy(dst, src, len);
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/*
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* Flush and invalidate kernel page if aliased and synchronize
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* data and instruction caches for executable pages.
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*/
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if (alias) {
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2012-11-28 17:53:51 -07:00
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unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
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2007-08-22 11:14:51 -06:00
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__flush_invalidate_dcache_range((unsigned long) dst, len);
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2012-11-28 17:53:51 -07:00
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if ((vma->vm_flags & VM_EXEC) != 0)
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__invalidate_icache_page_alias(t, phys);
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2007-08-22 11:14:51 -06:00
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} else if ((vma->vm_flags & VM_EXEC) != 0) {
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__flush_dcache_range((unsigned long)dst,len);
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__invalidate_icache_range((unsigned long) dst, len);
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}
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}
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extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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unsigned long phys = page_to_phys(page);
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unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
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/*
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* Flush user page if aliased.
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* (Note: a simply flush would be sufficient)
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*/
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if (alias) {
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2012-11-28 17:53:51 -07:00
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unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(t, phys);
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2007-08-22 11:14:51 -06:00
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}
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memcpy(dst, src, len);
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}
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#endif
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