2019-06-04 02:11:33 -06:00
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// SPDX-License-Identifier: GPL-2.0-only
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2013-02-03 22:46:29 -07:00
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*/
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#include <linux/clk.h>
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2013-09-10 11:59:47 -06:00
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#include <linux/cpu.h>
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2013-02-03 22:46:29 -07:00
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/module.h>
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2018-10-08 00:07:34 -06:00
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#include <linux/nvmem-consumer.h>
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2013-02-03 22:46:29 -07:00
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#include <linux/of.h>
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2017-09-30 09:16:46 -06:00
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#include <linux/of_address.h>
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2013-09-19 15:03:52 -06:00
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#include <linux/pm_opp.h>
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2013-02-03 22:46:29 -07:00
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#define PU_SOC_VOLTAGE_NORMAL 1250000
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#define PU_SOC_VOLTAGE_HIGH 1275000
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#define FREQ_1P2_GHZ 1200000000
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static struct regulator *arm_reg;
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static struct regulator *pu_reg;
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static struct regulator *soc_reg;
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2017-12-22 21:53:52 -07:00
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enum IMX6_CPUFREQ_CLKS {
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ARM,
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PLL1_SYS,
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STEP,
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PLL1_SW,
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PLL2_PFD2_396M,
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/* MX6UL requires two more clks */
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PLL2_BUS,
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SECONDARY_SEL,
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};
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#define IMX6Q_CPUFREQ_CLK_NUM 5
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#define IMX6UL_CPUFREQ_CLK_NUM 7
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static int num_clks;
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static struct clk_bulk_data clks[] = {
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{ .id = "arm" },
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{ .id = "pll1_sys" },
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{ .id = "step" },
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{ .id = "pll1_sw" },
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{ .id = "pll2_pfd2_396m" },
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{ .id = "pll2_bus" },
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{ .id = "secondary_sel" },
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};
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2015-09-11 09:41:05 -06:00
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2013-02-03 22:46:29 -07:00
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static struct device *cpu_dev;
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2014-11-25 03:34:23 -07:00
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static bool free_opp;
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2013-02-03 22:46:29 -07:00
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static struct cpufreq_frequency_table *freq_table;
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2018-02-25 22:08:44 -07:00
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static unsigned int max_freq;
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2013-02-03 22:46:29 -07:00
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static unsigned int transition_latency;
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
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static u32 *imx6_soc_volt;
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static u32 soc_opp_count;
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2013-10-25 08:15:48 -06:00
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static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
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2013-02-03 22:46:29 -07:00
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{
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2013-09-19 15:03:51 -06:00
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struct dev_pm_opp *opp;
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2013-02-03 22:46:29 -07:00
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unsigned long freq_hz, volt, volt_old;
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2013-08-14 08:08:24 -06:00
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unsigned int old_freq, new_freq;
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2017-08-28 05:05:18 -06:00
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bool pll1_sys_temp_enabled = false;
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2013-02-03 22:46:29 -07:00
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int ret;
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2013-08-14 08:08:24 -06:00
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new_freq = freq_table[index].frequency;
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freq_hz = new_freq * 1000;
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2017-12-22 21:53:52 -07:00
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old_freq = clk_get_rate(clks[ARM].clk) / 1000;
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2013-02-03 22:46:29 -07:00
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2013-09-19 15:03:50 -06:00
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opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
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2013-02-03 22:46:29 -07:00
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if (IS_ERR(opp)) {
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dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
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return PTR_ERR(opp);
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}
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2013-09-19 15:03:50 -06:00
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volt = dev_pm_opp_get_voltage(opp);
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2017-01-22 21:41:47 -07:00
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dev_pm_opp_put(opp);
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2013-02-03 22:46:29 -07:00
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volt_old = regulator_get_voltage(arm_reg);
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dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
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2013-08-14 08:08:24 -06:00
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old_freq / 1000, volt_old / 1000,
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new_freq / 1000, volt / 1000);
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2013-06-18 23:48:20 -06:00
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2013-02-03 22:46:29 -07:00
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/* scaling up? scale voltage before frequency */
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2013-08-14 08:08:24 -06:00
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if (new_freq > old_freq) {
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2014-06-20 01:42:18 -06:00
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if (!IS_ERR(pu_reg)) {
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ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
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return ret;
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}
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
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}
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ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
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if (ret) {
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dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
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return ret;
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}
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2013-02-03 22:46:29 -07:00
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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if (ret) {
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dev_err(cpu_dev,
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"failed to scale vddarm up: %d\n", ret);
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2013-08-14 08:08:24 -06:00
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return ret;
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2013-02-03 22:46:29 -07:00
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}
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}
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/*
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* The setpoints are selected per PLL/PDF frequencies, so we need to
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* reprogram PLL for frequency scaling. The procedure of reprogramming
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* PLL1 is as below.
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2015-09-11 09:41:05 -06:00
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* For i.MX6UL, it has a secondary clk mux, the cpu frequency change
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* flow is slightly different from other i.MX6 OSC.
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* The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
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2013-02-03 22:46:29 -07:00
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* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
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* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
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* - Disable pll2_pfd2_396m_clk
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*/
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2017-05-30 09:57:18 -06:00
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull")) {
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2015-09-11 09:41:05 -06:00
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/*
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* When changing pll1_sw_clk's parent to pll1_sys_clk,
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* CPU may run at higher than 528MHz, this will lead to
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* the system unstable if the voltage is lower than the
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* voltage of 528MHz, so lower the CPU frequency to one
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* half before changing CPU frequency.
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*/
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2017-12-22 21:53:52 -07:00
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clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
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clk_set_parent(clks[SECONDARY_SEL].clk,
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clks[PLL2_BUS].clk);
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2015-09-11 09:41:05 -06:00
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else
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2017-12-22 21:53:52 -07:00
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clk_set_parent(clks[SECONDARY_SEL].clk,
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clks[PLL2_PFD2_396M].clk);
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clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
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clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
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2018-01-07 19:04:51 -07:00
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if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
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clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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}
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2015-09-11 09:41:05 -06:00
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} else {
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2017-12-22 21:53:52 -07:00
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clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
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clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
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if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
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clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
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clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
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2017-08-28 05:05:18 -06:00
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} else {
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/* pll1_sys needs to be enabled for divider rate change to work. */
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pll1_sys_temp_enabled = true;
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2017-12-22 21:53:52 -07:00
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clk_prepare_enable(clks[PLL1_SYS].clk);
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2015-09-11 09:41:05 -06:00
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}
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2013-02-03 22:46:29 -07:00
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}
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/* Ensure the arm clock divider is what we expect */
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2017-12-22 21:53:52 -07:00
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ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
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2013-02-03 22:46:29 -07:00
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if (ret) {
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2018-11-04 17:59:28 -07:00
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int ret1;
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2013-02-03 22:46:29 -07:00
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dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
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2018-11-04 17:59:28 -07:00
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ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
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if (ret1)
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dev_warn(cpu_dev,
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"failed to restore vddarm voltage: %d\n", ret1);
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2013-08-14 08:08:24 -06:00
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return ret;
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2013-02-03 22:46:29 -07:00
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}
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2017-08-28 05:05:18 -06:00
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/* PLL1 is only needed until after ARM-PODF is set. */
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if (pll1_sys_temp_enabled)
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2017-12-22 21:53:52 -07:00
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clk_disable_unprepare(clks[PLL1_SYS].clk);
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2017-08-28 05:05:18 -06:00
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2013-02-03 22:46:29 -07:00
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/* scaling down? scale voltage after frequency */
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2013-08-14 08:08:24 -06:00
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if (new_freq < old_freq) {
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2013-02-03 22:46:29 -07:00
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ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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2018-11-25 19:59:45 -07:00
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if (ret)
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2013-02-03 22:46:29 -07:00
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dev_warn(cpu_dev,
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"failed to scale vddarm down: %d\n", ret);
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
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ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
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2018-11-25 19:59:45 -07:00
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if (ret)
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cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
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dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
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2014-06-20 01:42:18 -06:00
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if (!IS_ERR(pu_reg)) {
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ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
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2018-11-25 19:59:45 -07:00
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if (ret)
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2014-06-20 01:42:18 -06:00
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dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
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2013-02-03 22:46:29 -07:00
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}
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}
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2013-08-14 08:08:24 -06:00
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return 0;
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2013-02-03 22:46:29 -07:00
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}
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static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
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{
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2017-12-22 21:53:52 -07:00
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policy->clk = clks[ARM].clk;
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2019-07-15 22:06:08 -06:00
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cpufreq_generic_init(policy, freq_table, transition_latency);
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2018-02-25 22:08:44 -07:00
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policy->suspend_freq = max_freq;
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2019-02-06 21:34:20 -07:00
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dev_pm_opp_of_register_em(policy->cpus);
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2017-04-04 11:04:12 -06:00
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2019-07-15 22:06:08 -06:00
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return 0;
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2013-02-03 22:46:29 -07:00
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}
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static struct cpufreq_driver imx6q_cpufreq_driver = {
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2019-01-28 21:55:10 -07:00
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.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
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CPUFREQ_IS_COOLING_DEV,
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2013-10-03 08:58:08 -06:00
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.verify = cpufreq_generic_frequency_table_verify,
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2013-10-25 08:15:48 -06:00
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.target_index = imx6q_set_target,
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2014-01-09 08:08:43 -07:00
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.get = cpufreq_generic_get,
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2013-02-03 22:46:29 -07:00
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.init = imx6q_cpufreq_init,
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.name = "imx6q-cpufreq",
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2013-10-03 08:58:08 -06:00
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.attr = cpufreq_generic_attr,
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2017-04-04 11:04:12 -06:00
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.suspend = cpufreq_generic_suspend,
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2013-02-03 22:46:29 -07:00
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};
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2017-09-30 09:16:46 -06:00
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#define OCOTP_CFG3 0x440
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#define OCOTP_CFG3_SPEED_SHIFT 16
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#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
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#define OCOTP_CFG3_SPEED_996MHZ 0x2
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#define OCOTP_CFG3_SPEED_852MHZ 0x1
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static void imx6q_opp_check_speed_grading(struct device *dev)
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{
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struct device_node *np;
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void __iomem *base;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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if (!np)
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return;
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base = of_iomap(np, 0);
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|
|
|
if (!base) {
|
|
|
|
dev_err(dev, "failed to map ocotp\n");
|
|
|
|
goto put_node;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* SPEED_GRADING[1:0] defines the max speed of ARM:
|
|
|
|
* 2b'11: 1200000000Hz;
|
|
|
|
* 2b'10: 996000000Hz;
|
|
|
|
* 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
|
|
|
|
* 2b'00: 792000000Hz;
|
|
|
|
* We need to set the max speed of ARM according to fuse map.
|
|
|
|
*/
|
|
|
|
val = readl_relaxed(base + OCOTP_CFG3);
|
|
|
|
val >>= OCOTP_CFG3_SPEED_SHIFT;
|
|
|
|
val &= 0x3;
|
|
|
|
|
|
|
|
if (val < OCOTP_CFG3_SPEED_996MHZ)
|
|
|
|
if (dev_pm_opp_disable(dev, 996000000))
|
|
|
|
dev_warn(dev, "failed to disable 996MHz OPP\n");
|
2017-12-11 06:19:00 -07:00
|
|
|
|
|
|
|
if (of_machine_is_compatible("fsl,imx6q") ||
|
|
|
|
of_machine_is_compatible("fsl,imx6qp")) {
|
2017-09-30 09:16:46 -06:00
|
|
|
if (val != OCOTP_CFG3_SPEED_852MHZ)
|
|
|
|
if (dev_pm_opp_disable(dev, 852000000))
|
|
|
|
dev_warn(dev, "failed to disable 852MHz OPP\n");
|
2017-12-11 06:19:00 -07:00
|
|
|
if (val != OCOTP_CFG3_SPEED_1P2GHZ)
|
|
|
|
if (dev_pm_opp_disable(dev, 1200000000))
|
|
|
|
dev_warn(dev, "failed to disable 1.2GHz OPP\n");
|
2017-09-30 09:16:46 -06:00
|
|
|
}
|
|
|
|
iounmap(base);
|
|
|
|
put_node:
|
|
|
|
of_node_put(np);
|
|
|
|
}
|
|
|
|
|
2018-01-07 19:04:51 -07:00
|
|
|
#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
|
2018-05-22 00:28:51 -06:00
|
|
|
#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
|
|
|
|
#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
|
2018-01-07 19:04:51 -07:00
|
|
|
|
2018-10-08 00:07:34 -06:00
|
|
|
static int imx6ul_opp_check_speed_grading(struct device *dev)
|
2018-01-07 19:04:51 -07:00
|
|
|
{
|
|
|
|
u32 val;
|
2018-10-08 00:07:34 -06:00
|
|
|
int ret = 0;
|
2018-01-07 19:04:51 -07:00
|
|
|
|
2018-10-08 00:07:34 -06:00
|
|
|
if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
|
|
|
|
ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
} else {
|
|
|
|
struct device_node *np;
|
|
|
|
void __iomem *base;
|
|
|
|
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
|
|
|
|
if (!np)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
base = of_iomap(np, 0);
|
|
|
|
of_node_put(np);
|
|
|
|
if (!base) {
|
|
|
|
dev_err(dev, "failed to map ocotp\n");
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
2018-01-07 19:04:51 -07:00
|
|
|
|
2018-10-08 00:07:34 -06:00
|
|
|
val = readl_relaxed(base + OCOTP_CFG3);
|
|
|
|
iounmap(base);
|
2018-01-07 19:04:51 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Speed GRADING[1:0] defines the max speed of ARM:
|
|
|
|
* 2b'00: Reserved;
|
|
|
|
* 2b'01: 528000000Hz;
|
2018-05-22 00:28:51 -06:00
|
|
|
* 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
|
|
|
|
* 2b'11: 900000000Hz on i.MX6ULL only;
|
2018-01-07 19:04:51 -07:00
|
|
|
* We need to set the max speed of ARM according to fuse map.
|
|
|
|
*/
|
|
|
|
val >>= OCOTP_CFG3_SPEED_SHIFT;
|
|
|
|
val &= 0x3;
|
2018-05-22 00:28:51 -06:00
|
|
|
|
|
|
|
if (of_machine_is_compatible("fsl,imx6ul")) {
|
|
|
|
if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
|
|
|
|
if (dev_pm_opp_disable(dev, 696000000))
|
|
|
|
dev_warn(dev, "failed to disable 696MHz OPP\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_machine_is_compatible("fsl,imx6ull")) {
|
|
|
|
if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
|
|
|
|
if (dev_pm_opp_disable(dev, 792000000))
|
|
|
|
dev_warn(dev, "failed to disable 792MHz OPP\n");
|
|
|
|
|
|
|
|
if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
|
|
|
|
if (dev_pm_opp_disable(dev, 900000000))
|
|
|
|
dev_warn(dev, "failed to disable 900MHz OPP\n");
|
|
|
|
}
|
|
|
|
|
2018-10-08 00:07:34 -06:00
|
|
|
return ret;
|
2018-01-07 19:04:51 -07:00
|
|
|
}
|
|
|
|
|
2013-02-03 22:46:29 -07:00
|
|
|
static int imx6q_cpufreq_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device_node *np;
|
2013-09-19 15:03:51 -06:00
|
|
|
struct dev_pm_opp *opp;
|
2013-02-03 22:46:29 -07:00
|
|
|
unsigned long min_volt, max_volt;
|
|
|
|
int num, ret;
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
|
|
|
const struct property *prop;
|
|
|
|
const __be32 *val;
|
|
|
|
u32 nr, i, j;
|
2013-02-03 22:46:29 -07:00
|
|
|
|
2013-09-10 11:59:47 -06:00
|
|
|
cpu_dev = get_cpu_device(0);
|
|
|
|
if (!cpu_dev) {
|
|
|
|
pr_err("failed to get cpu0 device\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2013-02-03 22:46:29 -07:00
|
|
|
|
2013-06-17 07:58:48 -06:00
|
|
|
np = of_node_get(cpu_dev->of_node);
|
2013-02-03 22:46:29 -07:00
|
|
|
if (!np) {
|
|
|
|
dev_err(cpu_dev, "failed to find cpu0 node\n");
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
2017-05-30 09:57:18 -06:00
|
|
|
if (of_machine_is_compatible("fsl,imx6ul") ||
|
2017-12-22 21:53:52 -07:00
|
|
|
of_machine_is_compatible("fsl,imx6ull"))
|
|
|
|
num_clks = IMX6UL_CPUFREQ_CLK_NUM;
|
|
|
|
else
|
|
|
|
num_clks = IMX6Q_CPUFREQ_CLK_NUM;
|
|
|
|
|
|
|
|
ret = clk_bulk_get(cpu_dev, num_clks, clks);
|
|
|
|
if (ret)
|
|
|
|
goto put_node;
|
2015-09-11 09:41:05 -06:00
|
|
|
|
2014-05-14 10:02:23 -06:00
|
|
|
arm_reg = regulator_get(cpu_dev, "arm");
|
2014-06-20 01:42:18 -06:00
|
|
|
pu_reg = regulator_get_optional(cpu_dev, "pu");
|
2014-05-14 10:02:23 -06:00
|
|
|
soc_reg = regulator_get(cpu_dev, "soc");
|
2017-04-04 11:04:11 -06:00
|
|
|
if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
|
|
|
|
PTR_ERR(soc_reg) == -EPROBE_DEFER ||
|
|
|
|
PTR_ERR(pu_reg) == -EPROBE_DEFER) {
|
|
|
|
ret = -EPROBE_DEFER;
|
|
|
|
dev_dbg(cpu_dev, "regulators not ready, defer\n");
|
|
|
|
goto put_reg;
|
|
|
|
}
|
2014-06-20 01:42:18 -06:00
|
|
|
if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
|
2013-02-03 22:46:29 -07:00
|
|
|
dev_err(cpu_dev, "failed to get regulators\n");
|
|
|
|
ret = -ENOENT;
|
2014-05-14 10:02:23 -06:00
|
|
|
goto put_reg;
|
2013-02-03 22:46:29 -07:00
|
|
|
}
|
|
|
|
|
2017-09-30 09:16:46 -06:00
|
|
|
ret = dev_pm_opp_of_add_table(cpu_dev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
|
|
|
|
goto put_reg;
|
|
|
|
}
|
2013-12-19 23:56:28 -07:00
|
|
|
|
2018-05-22 00:28:51 -06:00
|
|
|
if (of_machine_is_compatible("fsl,imx6ul") ||
|
2018-10-08 00:07:34 -06:00
|
|
|
of_machine_is_compatible("fsl,imx6ull")) {
|
|
|
|
ret = imx6ul_opp_check_speed_grading(cpu_dev);
|
|
|
|
if (ret) {
|
2018-11-25 19:59:48 -07:00
|
|
|
if (ret == -EPROBE_DEFER)
|
2019-03-31 19:37:49 -06:00
|
|
|
goto put_node;
|
2018-11-25 19:59:48 -07:00
|
|
|
|
2018-10-08 00:07:34 -06:00
|
|
|
dev_err(cpu_dev, "failed to read ocotp: %d\n",
|
|
|
|
ret);
|
2019-03-31 19:37:49 -06:00
|
|
|
goto put_node;
|
2018-10-08 00:07:34 -06:00
|
|
|
}
|
|
|
|
} else {
|
2018-01-07 19:04:51 -07:00
|
|
|
imx6q_opp_check_speed_grading(cpu_dev);
|
2018-10-08 00:07:34 -06:00
|
|
|
}
|
2014-11-25 03:34:23 -07:00
|
|
|
|
2017-09-30 09:16:46 -06:00
|
|
|
/* Because we have added the OPPs here, we must free them */
|
|
|
|
free_opp = true;
|
|
|
|
num = dev_pm_opp_get_opp_count(cpu_dev);
|
|
|
|
if (num < 0) {
|
|
|
|
ret = num;
|
|
|
|
dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
|
|
|
|
goto out_free_opp;
|
2013-02-03 22:46:29 -07:00
|
|
|
}
|
|
|
|
|
2013-09-19 15:03:50 -06:00
|
|
|
ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
|
2013-02-03 22:46:29 -07:00
|
|
|
if (ret) {
|
|
|
|
dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
|
2017-04-09 01:33:52 -06:00
|
|
|
goto out_free_opp;
|
2013-02-03 22:46:29 -07:00
|
|
|
}
|
|
|
|
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
|
|
|
/* Make imx6_soc_volt array's size same as arm opp number */
|
treewide: devm_kzalloc() -> devm_kcalloc()
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:
devm_kzalloc(handle, a * b, gfp)
with:
devm_kcalloc(handle, a * b, gfp)
as well as handling cases of:
devm_kzalloc(handle, a * b * c, gfp)
with:
devm_kzalloc(handle, array3_size(a, b, c), gfp)
as it's slightly less ugly than:
devm_kcalloc(handle, array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
devm_kzalloc(handle, 4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@
(
devm_kzalloc(HANDLE,
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
devm_kzalloc(HANDLE,
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@
(
devm_kzalloc(HANDLE,
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@
(
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE,
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
|
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * E2
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * (E2)
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-12 15:07:58 -06:00
|
|
|
imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
|
|
|
|
GFP_KERNEL);
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
|
|
|
if (imx6_soc_volt == NULL) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto free_freq_table;
|
|
|
|
}
|
|
|
|
|
|
|
|
prop = of_find_property(np, "fsl,soc-operating-points", NULL);
|
|
|
|
if (!prop || !prop->value)
|
|
|
|
goto soc_opp_out;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Each OPP is a set of tuples consisting of frequency and
|
|
|
|
* voltage like <freq-kHz vol-uV>.
|
|
|
|
*/
|
|
|
|
nr = prop->length / sizeof(u32);
|
|
|
|
if (nr % 2 || (nr / 2) < num)
|
|
|
|
goto soc_opp_out;
|
|
|
|
|
|
|
|
for (j = 0; j < num; j++) {
|
|
|
|
val = prop->value;
|
|
|
|
for (i = 0; i < nr / 2; i++) {
|
|
|
|
unsigned long freq = be32_to_cpup(val++);
|
|
|
|
unsigned long volt = be32_to_cpup(val++);
|
|
|
|
if (freq_table[j].frequency == freq) {
|
|
|
|
imx6_soc_volt[soc_opp_count++] = volt;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
soc_opp_out:
|
|
|
|
/* use fixed soc opp volt if no valid soc opp info found in dtb */
|
|
|
|
if (soc_opp_count != num) {
|
|
|
|
dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
|
|
|
|
for (j = 0; j < num; j++)
|
|
|
|
imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
|
|
|
|
if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
|
|
|
|
imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
|
|
|
|
}
|
|
|
|
|
2013-02-03 22:46:29 -07:00
|
|
|
if (of_property_read_u32(np, "clock-latency", &transition_latency))
|
|
|
|
transition_latency = CPUFREQ_ETERNAL;
|
|
|
|
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
|
|
|
/*
|
|
|
|
* Calculate the ramp time for max voltage change in the
|
|
|
|
* VDDSOC and VDDPU regulators.
|
|
|
|
*/
|
|
|
|
ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
|
|
|
|
if (ret > 0)
|
|
|
|
transition_latency += ret * 1000;
|
2014-06-20 01:42:18 -06:00
|
|
|
if (!IS_ERR(pu_reg)) {
|
|
|
|
ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
|
|
|
|
if (ret > 0)
|
|
|
|
transition_latency += ret * 1000;
|
|
|
|
}
|
cpufreq: imx6q: correct VDDSOC/PU voltage scaling when cpufreq is changed
on i.MX6Q, cpu freq change need to follow below flows:
1. each setpoint has different VDDARM, VDDSOC/PU voltage, get the setpoint
table from dts;
2. when cpu freq is scaling up, need to increase VDDSOC/PU voltage before
VDDARM, if VDDPU is off, no need to change it;
3. when cpu freq is scaling down, need to decrease VDDARM voltage before
VDDSOC/PU, if VDDPU is off, no need to change it;
normally dts will pass vddsoc/pu freq/volt info to kernel, if not, will
use fixed value for vddsoc/pu voltage setting.
Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-12-19 07:16:47 -07:00
|
|
|
|
2013-02-03 22:46:29 -07:00
|
|
|
/*
|
|
|
|
* OPP is maintained in order of increasing frequency, and
|
|
|
|
* freq_table initialised from OPP is therefore sorted in the
|
|
|
|
* same order.
|
|
|
|
*/
|
2018-02-25 22:08:44 -07:00
|
|
|
max_freq = freq_table[--num].frequency;
|
2013-09-19 15:03:50 -06:00
|
|
|
opp = dev_pm_opp_find_freq_exact(cpu_dev,
|
2013-02-03 22:46:29 -07:00
|
|
|
freq_table[0].frequency * 1000, true);
|
2013-09-19 15:03:50 -06:00
|
|
|
min_volt = dev_pm_opp_get_voltage(opp);
|
2017-01-22 21:41:47 -07:00
|
|
|
dev_pm_opp_put(opp);
|
2018-02-25 22:08:44 -07:00
|
|
|
opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
|
2013-09-19 15:03:50 -06:00
|
|
|
max_volt = dev_pm_opp_get_voltage(opp);
|
2017-01-22 21:41:47 -07:00
|
|
|
dev_pm_opp_put(opp);
|
|
|
|
|
2013-02-03 22:46:29 -07:00
|
|
|
ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
|
|
|
|
if (ret > 0)
|
|
|
|
transition_latency += ret * 1000;
|
|
|
|
|
|
|
|
ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(cpu_dev, "failed register driver: %d\n", ret);
|
|
|
|
goto free_freq_table;
|
|
|
|
}
|
|
|
|
|
|
|
|
of_node_put(np);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
free_freq_table:
|
2013-09-19 15:03:50 -06:00
|
|
|
dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
|
2014-11-25 03:34:23 -07:00
|
|
|
out_free_opp:
|
|
|
|
if (free_opp)
|
2015-09-04 02:17:24 -06:00
|
|
|
dev_pm_opp_of_remove_table(cpu_dev);
|
2014-05-14 10:02:23 -06:00
|
|
|
put_reg:
|
|
|
|
if (!IS_ERR(arm_reg))
|
|
|
|
regulator_put(arm_reg);
|
|
|
|
if (!IS_ERR(pu_reg))
|
|
|
|
regulator_put(pu_reg);
|
|
|
|
if (!IS_ERR(soc_reg))
|
|
|
|
regulator_put(soc_reg);
|
2017-12-22 21:53:52 -07:00
|
|
|
|
|
|
|
clk_bulk_put(num_clks, clks);
|
|
|
|
put_node:
|
2013-02-03 22:46:29 -07:00
|
|
|
of_node_put(np);
|
2017-12-22 21:53:52 -07:00
|
|
|
|
2013-02-03 22:46:29 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx6q_cpufreq_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
cpufreq_unregister_driver(&imx6q_cpufreq_driver);
|
2013-09-19 15:03:50 -06:00
|
|
|
dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
|
2014-11-25 03:34:23 -07:00
|
|
|
if (free_opp)
|
2015-09-04 02:17:24 -06:00
|
|
|
dev_pm_opp_of_remove_table(cpu_dev);
|
2014-05-14 10:02:23 -06:00
|
|
|
regulator_put(arm_reg);
|
2014-06-20 01:42:18 -06:00
|
|
|
if (!IS_ERR(pu_reg))
|
|
|
|
regulator_put(pu_reg);
|
2014-05-14 10:02:23 -06:00
|
|
|
regulator_put(soc_reg);
|
2017-12-22 21:53:52 -07:00
|
|
|
|
|
|
|
clk_bulk_put(num_clks, clks);
|
2013-02-03 22:46:29 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver imx6q_cpufreq_platdrv = {
|
|
|
|
.driver = {
|
|
|
|
.name = "imx6q-cpufreq",
|
|
|
|
},
|
|
|
|
.probe = imx6q_cpufreq_probe,
|
|
|
|
.remove = imx6q_cpufreq_remove,
|
|
|
|
};
|
|
|
|
module_platform_driver(imx6q_cpufreq_platdrv);
|
|
|
|
|
2018-01-30 02:55:26 -07:00
|
|
|
MODULE_ALIAS("platform:imx6q-cpufreq");
|
2013-02-03 22:46:29 -07:00
|
|
|
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
|
|
|
|
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
|
|
|
|
MODULE_LICENSE("GPL");
|