2016-09-29 10:21:53 -06:00
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/*
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* Marvell 88E6xxx Switch Global (1) Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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2017-03-28 13:10:36 -06:00
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* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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2016-09-29 10:21:53 -06:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _MV88E6XXX_GLOBAL1_H
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#define _MV88E6XXX_GLOBAL1_H
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#include "mv88e6xxx.h"
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int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
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int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
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int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
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2016-12-05 15:30:27 -07:00
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int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
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int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
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2016-12-05 15:30:28 -07:00
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int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
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int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
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2016-11-21 15:27:05 -07:00
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int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
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2016-11-21 15:26:58 -07:00
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int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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2016-11-21 15:27:00 -07:00
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int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
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2016-11-21 15:27:01 -07:00
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int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
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2016-11-21 15:27:05 -07:00
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void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
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2016-12-02 20:35:17 -07:00
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int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
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int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
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int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
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int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
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2016-12-02 20:45:16 -07:00
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int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
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2016-09-29 10:21:53 -06:00
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2017-03-11 14:12:51 -07:00
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int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
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2017-03-11 14:12:48 -07:00
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int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
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unsigned int msecs);
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2017-03-11 14:12:53 -07:00
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int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
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struct mv88e6xxx_atu_entry *entry);
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2017-03-11 14:12:52 -07:00
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int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
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struct mv88e6xxx_atu_entry *entry);
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2017-03-11 14:12:54 -07:00
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int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
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2017-03-11 14:12:55 -07:00
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int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
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bool all);
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2017-03-11 14:12:48 -07:00
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2017-05-01 12:05:22 -06:00
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int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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2017-05-01 12:05:23 -06:00
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int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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2017-05-01 12:05:22 -06:00
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int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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2017-05-01 12:05:23 -06:00
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int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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2017-05-01 12:05:27 -06:00
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int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry);
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2017-05-01 12:05:13 -06:00
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int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
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2017-05-01 12:05:12 -06:00
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2016-09-29 10:21:53 -06:00
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#endif /* _MV88E6XXX_GLOBAL1_H */
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