2006-08-13 15:44:09 -06:00
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/*
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* TI OMAP I2C master mode driver
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*
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* Copyright (C) 2003 MontaVista Software, Inc.
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* Copyright (C) 2004 Texas Instruments.
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*
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* Updated to work with multiple I2C interfaces on 24xx by
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* Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
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* Copyright (C) 2005 Nokia Corporation
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*
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* Cleaned up by Juha Yrj<EFBFBD>l<EFBFBD> <juha.yrjola@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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/* timeout waiting for the controller to respond */
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#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
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#define OMAP_I2C_REV_REG 0x00
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#define OMAP_I2C_IE_REG 0x04
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#define OMAP_I2C_STAT_REG 0x08
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#define OMAP_I2C_IV_REG 0x0c
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#define OMAP_I2C_SYSS_REG 0x10
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#define OMAP_I2C_BUF_REG 0x14
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#define OMAP_I2C_CNT_REG 0x18
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#define OMAP_I2C_DATA_REG 0x1c
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#define OMAP_I2C_SYSC_REG 0x20
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#define OMAP_I2C_CON_REG 0x24
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#define OMAP_I2C_OA_REG 0x28
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#define OMAP_I2C_SA_REG 0x2c
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#define OMAP_I2C_PSC_REG 0x30
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#define OMAP_I2C_SCLL_REG 0x34
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#define OMAP_I2C_SCLH_REG 0x38
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#define OMAP_I2C_SYSTEST_REG 0x3c
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/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
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#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
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#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
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#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
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#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
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#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
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/* I2C Status Register (OMAP_I2C_STAT): */
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#define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */
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#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
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#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
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#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
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#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
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#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
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#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
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#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
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#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
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#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
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#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
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/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
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#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
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#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
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/* I2C Configuration Register (OMAP_I2C_CON): */
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#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
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#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
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#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
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#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
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#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
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#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
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#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
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#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
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#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
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/* I2C System Test Register (OMAP_I2C_SYSTEST): */
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#ifdef DEBUG
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#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
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#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
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#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
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#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
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#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
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#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
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#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
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#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
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#endif
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/* I2C System Status register (OMAP_I2C_SYSS): */
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#define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
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/* I2C System Configuration Register (OMAP_I2C_SYSC): */
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#define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
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/* REVISIT: Use platform_data instead of module parameters */
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/* Fast Mode = 400 kHz, Standard = 100 kHz */
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static int clock = 100; /* Default: 100 kHz */
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module_param(clock, int, 0);
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MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
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struct omap_i2c_dev {
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struct device *dev;
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void __iomem *base; /* virtual */
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int irq;
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struct clk *iclk; /* Interface clock */
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struct clk *fclk; /* Functional clock */
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struct completion cmd_complete;
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struct resource *ioarea;
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u16 cmd_err;
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u8 *buf;
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size_t buf_len;
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struct i2c_adapter adapter;
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unsigned rev1:1;
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};
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static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
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int reg, u16 val)
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{
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__raw_writew(val, i2c_dev->base + reg);
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}
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static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
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{
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return __raw_readw(i2c_dev->base + reg);
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}
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static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
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{
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if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
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dev->iclk = clk_get(dev->dev, "i2c_ick");
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if (IS_ERR(dev->iclk)) {
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dev->iclk = NULL;
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return -ENODEV;
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}
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}
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dev->fclk = clk_get(dev->dev, "i2c_fck");
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if (IS_ERR(dev->fclk)) {
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if (dev->iclk != NULL) {
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clk_put(dev->iclk);
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dev->iclk = NULL;
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}
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dev->fclk = NULL;
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return -ENODEV;
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}
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return 0;
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}
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static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
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{
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clk_put(dev->fclk);
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dev->fclk = NULL;
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if (dev->iclk != NULL) {
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clk_put(dev->iclk);
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dev->iclk = NULL;
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}
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}
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static void omap_i2c_enable_clocks(struct omap_i2c_dev *dev)
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{
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if (dev->iclk != NULL)
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clk_enable(dev->iclk);
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clk_enable(dev->fclk);
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}
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static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
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{
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if (dev->iclk != NULL)
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clk_disable(dev->iclk);
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clk_disable(dev->fclk);
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}
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static int omap_i2c_init(struct omap_i2c_dev *dev)
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{
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u16 psc = 0;
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unsigned long fclk_rate = 12000000;
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unsigned long timeout;
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if (!dev->rev1) {
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omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
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/* For some reason we need to set the EN bit before the
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* reset done bit gets set. */
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timeout = jiffies + OMAP_I2C_TIMEOUT;
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
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while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
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OMAP_I2C_SYSS_RDONE)) {
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if (time_after(jiffies, timeout)) {
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dev_warn(dev->dev, "timeout waiting"
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"for controller reset\n");
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return -ETIMEDOUT;
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}
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msleep(1);
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}
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}
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
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if (cpu_class_is_omap1()) {
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struct clk *armxor_ck;
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armxor_ck = clk_get(NULL, "armxor_ck");
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if (IS_ERR(armxor_ck))
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dev_warn(dev->dev, "Could not get armxor_ck\n");
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else {
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fclk_rate = clk_get_rate(armxor_ck);
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clk_put(armxor_ck);
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}
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/* TRM for 5912 says the I2C clock must be prescaled to be
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* between 7 - 12 MHz. The XOR input clock is typically
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* 12, 13 or 19.2 MHz. So we should have code that produces:
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*
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* XOR MHz Divider Prescaler
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* 12 1 0
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* 13 2 1
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* 19.2 2 1
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*/
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if (fclk_rate > 16000000)
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psc = (fclk_rate + 8000000) / 12000000;
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}
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/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
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omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
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/* Program desired operating rate */
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fclk_rate /= (psc + 1) * 1000;
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if (psc > 2)
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psc = 2;
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omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
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fclk_rate / (clock * 2) - 7 + psc);
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omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
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fclk_rate / (clock * 2) - 7 + psc);
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/* Take the I2C module out of reset: */
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
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/* Enable interrupts */
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omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
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(OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
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OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
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OMAP_I2C_IE_AL));
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return 0;
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}
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/*
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* Waiting on Bus Busy
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*/
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static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
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{
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unsigned long timeout;
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timeout = jiffies + OMAP_I2C_TIMEOUT;
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while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
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if (time_after(jiffies, timeout)) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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return -ETIMEDOUT;
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}
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msleep(1);
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}
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return 0;
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}
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/*
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* Low level master read/write transaction.
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*/
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static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
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struct i2c_msg *msg, int stop)
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{
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struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
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int r;
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u16 w;
|
|
|
|
|
|
|
|
|
|
dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
|
|
|
|
|
msg->addr, msg->len, msg->flags, stop);
|
|
|
|
|
|
|
|
|
|
if (msg->len == 0)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
|
|
|
|
|
|
|
|
|
|
/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
|
|
|
|
|
dev->buf = msg->buf;
|
|
|
|
|
dev->buf_len = msg->len;
|
|
|
|
|
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
|
|
|
|
|
|
|
|
|
|
init_completion(&dev->cmd_complete);
|
|
|
|
|
dev->cmd_err = 0;
|
|
|
|
|
|
|
|
|
|
w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
|
|
|
|
|
if (msg->flags & I2C_M_TEN)
|
|
|
|
|
w |= OMAP_I2C_CON_XA;
|
|
|
|
|
if (!(msg->flags & I2C_M_RD))
|
|
|
|
|
w |= OMAP_I2C_CON_TRX;
|
|
|
|
|
if (stop)
|
|
|
|
|
w |= OMAP_I2C_CON_STP;
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
|
|
|
|
|
|
|
|
|
|
r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
|
|
|
|
|
OMAP_I2C_TIMEOUT);
|
|
|
|
|
dev->buf_len = 0;
|
|
|
|
|
if (r < 0)
|
|
|
|
|
return r;
|
|
|
|
|
if (r == 0) {
|
|
|
|
|
dev_err(dev->dev, "controller timed out\n");
|
|
|
|
|
omap_i2c_init(dev);
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (likely(!dev->cmd_err))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
/* We have an error */
|
|
|
|
|
if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
|
|
|
|
|
OMAP_I2C_STAT_XUDF)) {
|
|
|
|
|
omap_i2c_init(dev);
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
|
|
|
|
|
if (msg->flags & I2C_M_IGNORE_NAK)
|
|
|
|
|
return 0;
|
|
|
|
|
if (stop) {
|
|
|
|
|
w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
|
|
|
|
|
w |= OMAP_I2C_CON_STP;
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
|
|
|
|
|
}
|
|
|
|
|
return -EREMOTEIO;
|
|
|
|
|
}
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Prepare controller for a transaction and call omap_i2c_xfer_msg
|
|
|
|
|
* to do the work during IRQ processing.
|
|
|
|
|
*/
|
|
|
|
|
static int
|
|
|
|
|
omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
|
|
|
|
{
|
|
|
|
|
struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
|
int i;
|
|
|
|
|
int r;
|
|
|
|
|
|
|
|
|
|
omap_i2c_enable_clocks(dev);
|
|
|
|
|
|
|
|
|
|
/* REVISIT: initialize and use adap->retries. This is an optional
|
|
|
|
|
* feature */
|
|
|
|
|
if ((r = omap_i2c_wait_for_bb(dev)) < 0)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < num; i++) {
|
|
|
|
|
r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
|
|
|
|
|
if (r != 0)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (r == 0)
|
|
|
|
|
r = num;
|
|
|
|
|
out:
|
|
|
|
|
omap_i2c_disable_clocks(dev);
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u32
|
|
|
|
|
omap_i2c_func(struct i2c_adapter *adap)
|
|
|
|
|
{
|
|
|
|
|
return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
|
omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
|
|
|
|
|
{
|
|
|
|
|
dev->cmd_err |= err;
|
|
|
|
|
complete(&dev->cmd_complete);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
|
omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
|
|
|
|
|
{
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t
|
|
|
|
|
omap_i2c_rev1_isr(int this_irq, void *dev_id, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
struct omap_i2c_dev *dev = dev_id;
|
|
|
|
|
u16 iv, w;
|
|
|
|
|
|
|
|
|
|
iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
|
|
|
|
|
switch (iv) {
|
|
|
|
|
case 0x00: /* None */
|
|
|
|
|
break;
|
|
|
|
|
case 0x01: /* Arbitration lost */
|
|
|
|
|
dev_err(dev->dev, "Arbitration lost\n");
|
|
|
|
|
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
|
|
|
|
|
break;
|
|
|
|
|
case 0x02: /* No acknowledgement */
|
|
|
|
|
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
|
|
|
|
|
break;
|
|
|
|
|
case 0x03: /* Register access ready */
|
|
|
|
|
omap_i2c_complete_cmd(dev, 0);
|
|
|
|
|
break;
|
|
|
|
|
case 0x04: /* Receive data ready */
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
|
|
|
|
|
*dev->buf++ = w;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
*dev->buf++ = w >> 8;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
dev_err(dev->dev, "RRDY IRQ while no data requested\n");
|
|
|
|
|
break;
|
|
|
|
|
case 0x05: /* Transmit data ready */
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
w = *dev->buf++;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
w |= *dev->buf++ << 8;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
}
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
|
|
|
|
|
} else
|
|
|
|
|
dev_err(dev->dev, "XRDY IRQ while no data to send\n");
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t
|
|
|
|
|
omap_i2c_isr(int this_irq, void *dev_id, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
struct omap_i2c_dev *dev = dev_id;
|
|
|
|
|
u16 bits;
|
|
|
|
|
u16 stat, w;
|
|
|
|
|
int count = 0;
|
|
|
|
|
|
|
|
|
|
bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
|
|
|
|
|
while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
|
|
|
|
|
dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
|
|
|
|
|
if (count++ == 100) {
|
|
|
|
|
dev_warn(dev->dev, "Too much work in one IRQ\n");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
|
|
|
|
|
|
|
|
|
|
if (stat & OMAP_I2C_STAT_ARDY) {
|
|
|
|
|
omap_i2c_complete_cmd(dev, 0);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
if (stat & OMAP_I2C_STAT_RRDY) {
|
|
|
|
|
w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
*dev->buf++ = w;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
*dev->buf++ = w >> 8;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
dev_err(dev->dev, "RRDY IRQ while no data"
|
|
|
|
|
"requested\n");
|
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
if (stat & OMAP_I2C_STAT_XRDY) {
|
|
|
|
|
w = 0;
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
w = *dev->buf++;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
if (dev->buf_len) {
|
|
|
|
|
w |= *dev->buf++ << 8;
|
|
|
|
|
dev->buf_len--;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
dev_err(dev->dev, "XRDY IRQ while no"
|
|
|
|
|
"data to send\n");
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
|
|
|
|
|
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
if (stat & OMAP_I2C_STAT_ROVR) {
|
|
|
|
|
dev_err(dev->dev, "Receive overrun\n");
|
|
|
|
|
dev->cmd_err |= OMAP_I2C_STAT_ROVR;
|
|
|
|
|
}
|
|
|
|
|
if (stat & OMAP_I2C_STAT_XUDF) {
|
|
|
|
|
dev_err(dev->dev, "Transmit overflow\n");
|
|
|
|
|
dev->cmd_err |= OMAP_I2C_STAT_XUDF;
|
|
|
|
|
}
|
|
|
|
|
if (stat & OMAP_I2C_STAT_NACK) {
|
|
|
|
|
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
|
|
|
|
|
OMAP_I2C_CON_STP);
|
|
|
|
|
}
|
|
|
|
|
if (stat & OMAP_I2C_STAT_AL) {
|
|
|
|
|
dev_err(dev->dev, "Arbitration lost\n");
|
|
|
|
|
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return count ? IRQ_HANDLED : IRQ_NONE;
|
|
|
|
|
}
|
|
|
|
|
|
2006-09-03 14:39:46 -06:00
|
|
|
|
static const struct i2c_algorithm omap_i2c_algo = {
|
2006-08-13 15:44:09 -06:00
|
|
|
|
.master_xfer = omap_i2c_xfer,
|
|
|
|
|
.functionality = omap_i2c_func,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
omap_i2c_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct omap_i2c_dev *dev;
|
|
|
|
|
struct i2c_adapter *adap;
|
|
|
|
|
struct resource *mem, *irq, *ioarea;
|
|
|
|
|
int r;
|
|
|
|
|
|
|
|
|
|
/* NOTE: driver uses the static register mapping */
|
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
if (!mem) {
|
|
|
|
|
dev_err(&pdev->dev, "no mem resource?\n");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
|
if (!irq) {
|
|
|
|
|
dev_err(&pdev->dev, "no irq resource?\n");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
|
|
|
|
|
pdev->name);
|
|
|
|
|
if (!ioarea) {
|
|
|
|
|
dev_err(&pdev->dev, "I2C region already claimed\n");
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (clock > 200)
|
|
|
|
|
clock = 400; /* Fast mode */
|
|
|
|
|
else
|
|
|
|
|
clock = 100; /* Standard mode */
|
|
|
|
|
|
|
|
|
|
dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
|
|
|
|
|
if (!dev) {
|
|
|
|
|
r = -ENOMEM;
|
|
|
|
|
goto err_release_region;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev->dev = &pdev->dev;
|
|
|
|
|
dev->irq = irq->start;
|
|
|
|
|
dev->base = (void __iomem *) IO_ADDRESS(mem->start);
|
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
|
|
|
|
|
|
if ((r = omap_i2c_get_clocks(dev)) != 0)
|
|
|
|
|
goto err_free_mem;
|
|
|
|
|
|
|
|
|
|
omap_i2c_enable_clocks(dev);
|
|
|
|
|
|
|
|
|
|
if (cpu_is_omap15xx())
|
|
|
|
|
dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
|
|
|
|
|
|
|
|
|
|
/* reset ASAP, clearing any IRQs */
|
|
|
|
|
omap_i2c_init(dev);
|
|
|
|
|
|
|
|
|
|
r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
|
|
|
|
|
0, pdev->name, dev);
|
|
|
|
|
|
|
|
|
|
if (r) {
|
|
|
|
|
dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
|
|
|
|
|
goto err_unuse_clocks;
|
|
|
|
|
}
|
|
|
|
|
r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
|
|
|
|
|
dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
|
|
|
|
|
pdev->id, r >> 4, r & 0xf, clock);
|
|
|
|
|
|
|
|
|
|
adap = &dev->adapter;
|
|
|
|
|
i2c_set_adapdata(adap, dev);
|
|
|
|
|
adap->owner = THIS_MODULE;
|
|
|
|
|
adap->class = I2C_CLASS_HWMON;
|
|
|
|
|
strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
|
|
|
|
|
adap->algo = &omap_i2c_algo;
|
|
|
|
|
adap->dev.parent = &pdev->dev;
|
|
|
|
|
|
|
|
|
|
/* i2c device drivers may be active on return from add_adapter() */
|
|
|
|
|
r = i2c_add_adapter(adap);
|
|
|
|
|
if (r) {
|
|
|
|
|
dev_err(dev->dev, "failure adding adapter\n");
|
|
|
|
|
goto err_free_irq;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
omap_i2c_disable_clocks(dev);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_free_irq:
|
|
|
|
|
free_irq(dev->irq, dev);
|
|
|
|
|
err_unuse_clocks:
|
|
|
|
|
omap_i2c_disable_clocks(dev);
|
|
|
|
|
omap_i2c_put_clocks(dev);
|
|
|
|
|
err_free_mem:
|
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
kfree(dev);
|
|
|
|
|
err_release_region:
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
|
|
|
|
|
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
|
|
|
|
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
omap_i2c_remove(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
|
|
|
|
|
struct resource *mem;
|
|
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
|
|
|
|
|
free_irq(dev->irq, dev);
|
|
|
|
|
i2c_del_adapter(&dev->adapter);
|
|
|
|
|
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
|
|
|
|
|
omap_i2c_put_clocks(dev);
|
|
|
|
|
kfree(dev);
|
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct platform_driver omap_i2c_driver = {
|
|
|
|
|
.probe = omap_i2c_probe,
|
|
|
|
|
.remove = omap_i2c_remove,
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "i2c_omap",
|
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* I2C may be needed to bring up other drivers */
|
|
|
|
|
static int __init
|
|
|
|
|
omap_i2c_init_driver(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_register(&omap_i2c_driver);
|
|
|
|
|
}
|
|
|
|
|
subsys_initcall(omap_i2c_init_driver);
|
|
|
|
|
|
|
|
|
|
static void __exit omap_i2c_exit_driver(void)
|
|
|
|
|
{
|
|
|
|
|
platform_driver_unregister(&omap_i2c_driver);
|
|
|
|
|
}
|
|
|
|
|
module_exit(omap_i2c_exit_driver);
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
|
|
|
|
|
MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
|
|
|
|
|
MODULE_LICENSE("GPL");
|