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alistair23-linux/sound/firewire/fireface/ff.c

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// SPDX-License-Identifier: GPL-2.0-only
/*
* ff.c - a part of driver for RME Fireface series
*
* Copyright (c) 2015-2017 Takashi Sakamoto
*/
#include "ff.h"
#define OUI_RME 0x000a35
MODULE_DESCRIPTION("RME Fireface series Driver");
MODULE_AUTHOR("Takashi Sakamoto <o-takashi@sakamocchi.jp>");
MODULE_LICENSE("GPL v2");
static void name_card(struct snd_ff *ff)
{
struct fw_device *fw_dev = fw_parent_device(ff->unit);
strcpy(ff->card->driver, "Fireface");
strcpy(ff->card->shortname, ff->spec->name);
strcpy(ff->card->mixername, ff->spec->name);
snprintf(ff->card->longname, sizeof(ff->card->longname),
"RME %s, GUID %08x%08x at %s, S%d", ff->spec->name,
fw_dev->config_rom[3], fw_dev->config_rom[4],
dev_name(&ff->unit->device), 100 << fw_dev->max_speed);
}
static void ff_card_free(struct snd_card *card)
{
struct snd_ff *ff = card->private_data;
snd_ff_stream_destroy_duplex(ff);
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 06:17:02 -07:00
snd_ff_transaction_unregister(ff);
}
static void do_registration(struct work_struct *work)
{
struct snd_ff *ff = container_of(work, struct snd_ff, dwork.work);
int err;
if (ff->registered)
return;
err = snd_card_new(&ff->unit->device, -1, NULL, THIS_MODULE, 0,
&ff->card);
if (err < 0)
return;
ff->card->private_free = ff_card_free;
ff->card->private_data = ff;
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 06:17:02 -07:00
err = snd_ff_transaction_register(ff);
if (err < 0)
goto error;
ALSA: fireface: add transaction support As long as investigating Fireface 400, MIDI messages are transferred by asynchronous communication over IEEE 1394 bus. Fireface 400 receives MIDI messages by write transactions to two addresses; 0x'0000'0801'8000 and 0x'0000'0801'9000. Each of two seems to correspond to MIDI port 1 and 2. Fireface 400 transfers MIDI messages by write transactions to certain addresses which configured by drivers. The drivers can decide upper 4 byte of the addresses by write transactions to 0x'0000'0801'03f4. For the rest part of the address, drivers can select from below options: * 0x'0000'0000 * 0x'0000'0080 * 0x'0000'0100 * 0x'0000'0180 Selected options are represented in register 0x'0000'0801'051c as bit flags. Due to this mechanism, drivers are restricted to use addresses on 'Memory space' of IEEE 1222, even if transactions to the address have some side effects. This commit adds transaction support for MIDI messaging, based on my assumption that the similar mechanism is used on the other protocols. To receive asynchronous transactions, the driver allocates a range of address in 'Memory space'. I apply a strategy to use 0x'0000'0000 as lower 4 byte of the address. When getting failure from Linux FireWire subsystem, this driver retries to allocate addresses. Unfortunately, read transaction to address 0x'0000'0801'051c returns zero always, however write transactions have effects to the other features such as status of sampling clock. For this reason, this commit delegates a task to configure this register to user space applications. The applications should set 3rd bit in LSB in little endian order. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 07:06:03 -06:00
name_card(ff);
err = snd_ff_stream_init_duplex(ff);
if (err < 0)
goto error;
snd_ff_proc_init(ff);
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 06:17:02 -07:00
err = snd_ff_create_midi_devices(ff);
if (err < 0)
goto error;
err = snd_ff_create_pcm_devices(ff);
if (err < 0)
goto error;
ALSA: fireface: add support for PCM functionality This commit adds PCM functionality to transmit/receive PCM frames on isochronous packet streaming. This commit enables userspace applications to start/stop packet streaming via ALSA PCM interface. Sampling rate requested by applications is used as sampling transmission frequency of IEC 61883-1/6packet streaming. As I described in followed commits, units in this series manages sampling clock frequency independently of sampling transmission frequency, and they supports resampling between their packet streaming/data block processing layer and sampling data processing layer. This commit take this driver to utilize these features for usability. When internal clock is selected as source signal of sampling clock, this driver allows user space applications to start PCM substreams at any rate which packet streaming engine supports as sampling transmission frequency. In this case, this driver expects units to perform resampling PCM frames for rx/tx packets when sampling clock frequency and sampling transmission frequency are mismatched. This is for daily use cases. When any external clock is selected as the source signal, this driver gets configured sampling rate from units, then restricts available sampling rate to the rate for PCM applications. This is for studio use cases. Models in this series supports 64.0/128.0 kHz of sampling rate, however these frequencies are not supported by IEC 61883-6 as sampling transmission frequency. Therefore, packet streaming engine of ALSA firewire stack can't handle them. When units are configured to use any external clock as source signal of sampling clock and one of these unsupported rate is configured as rate of the sampling clock, this driver returns EIO to user space applications. Anyway, this driver doesn't voluntarily configure parameters of sampling clock. It's better for users to work with appropriate user space implementations to configure the parameters in advance of usage. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 07:06:10 -06:00
err = snd_ff_create_hwdep_devices(ff);
if (err < 0)
goto error;
err = snd_card_register(ff->card);
if (err < 0)
goto error;
ff->registered = true;
return;
error:
snd_card_free(ff->card);
dev_info(&ff->unit->device,
"Sound card registration failed: %d\n", err);
}
static int snd_ff_probe(struct fw_unit *unit,
const struct ieee1394_device_id *entry)
{
struct snd_ff *ff;
ff = devm_kzalloc(&unit->device, sizeof(struct snd_ff), GFP_KERNEL);
if (!ff)
return -ENOMEM;
ff->unit = fw_unit_get(unit);
dev_set_drvdata(&unit->device, ff);
mutex_init(&ff->mutex);
spin_lock_init(&ff->lock);
init_waitqueue_head(&ff->hwdep_wait);
ff->spec = (const struct snd_ff_spec *)entry->driver_data;
/* Register this sound card later. */
INIT_DEFERRABLE_WORK(&ff->dwork, do_registration);
snd_fw_schedule_registration(unit, &ff->dwork);
return 0;
}
static void snd_ff_update(struct fw_unit *unit)
{
struct snd_ff *ff = dev_get_drvdata(&unit->device);
/* Postpone a workqueue for deferred registration. */
if (!ff->registered)
snd_fw_schedule_registration(unit, &ff->dwork);
ALSA: fireface: add transaction support As long as investigating Fireface 400, MIDI messages are transferred by asynchronous communication over IEEE 1394 bus. Fireface 400 receives MIDI messages by write transactions to two addresses; 0x'0000'0801'8000 and 0x'0000'0801'9000. Each of two seems to correspond to MIDI port 1 and 2. Fireface 400 transfers MIDI messages by write transactions to certain addresses which configured by drivers. The drivers can decide upper 4 byte of the addresses by write transactions to 0x'0000'0801'03f4. For the rest part of the address, drivers can select from below options: * 0x'0000'0000 * 0x'0000'0080 * 0x'0000'0100 * 0x'0000'0180 Selected options are represented in register 0x'0000'0801'051c as bit flags. Due to this mechanism, drivers are restricted to use addresses on 'Memory space' of IEEE 1222, even if transactions to the address have some side effects. This commit adds transaction support for MIDI messaging, based on my assumption that the similar mechanism is used on the other protocols. To receive asynchronous transactions, the driver allocates a range of address in 'Memory space'. I apply a strategy to use 0x'0000'0000 as lower 4 byte of the address. When getting failure from Linux FireWire subsystem, this driver retries to allocate addresses. Unfortunately, read transaction to address 0x'0000'0801'051c returns zero always, however write transactions have effects to the other features such as status of sampling clock. For this reason, this commit delegates a task to configure this register to user space applications. The applications should set 3rd bit in LSB in little endian order. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 07:06:03 -06:00
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 06:17:02 -07:00
snd_ff_transaction_reregister(ff);
if (ff->registered)
snd_ff_stream_update_duplex(ff);
}
static void snd_ff_remove(struct fw_unit *unit)
{
struct snd_ff *ff = dev_get_drvdata(&unit->device);
/*
* Confirm to stop the work for registration before the sound card is
* going to be released. The work is not scheduled again because bus
* reset handler is not called anymore.
*/
cancel_work_sync(&ff->dwork.work);
if (ff->registered) {
// Block till all of ALSA character devices are released.
snd_card_free(ff->card);
}
mutex_destroy(&ff->mutex);
fw_unit_put(ff->unit);
}
static const struct snd_ff_spec spec_ff800 = {
.name = "Fireface800",
.pcm_capture_channels = {28, 20, 12},
.pcm_playback_channels = {28, 20, 12},
.midi_in_ports = 1,
.midi_out_ports = 1,
.protocol = &snd_ff_protocol_ff800,
.midi_high_addr = 0x000200000320ull,
.midi_addr_range = 12,
.midi_rx_addrs = {0x000080180000ull, 0},
};
static const struct snd_ff_spec spec_ff400 = {
ALSA: fireface: add support for Fireface 400 Fireface 400 is a second model of RME Fireface series, released in 2006. This commit adds support for this model. This model supports 8 analog channels, 2 S/PDIF channels and 8 ADAT channels in both of tx/rx packet. The number of ADAT channels differs depending on each mode of sampling transmission frequency. $ python2 linux-firewire-utils/src/crpp < /sys/bus/firewire/devices/fw1/config_rom ROM header and bus information block ----------------------------------------------------------------- 400 04107768 bus_info_length 4, crc_length 16, crc 30568 (should be 61311) 404 31333934 bus_name "1394" 408 20009002 irmc 0, cmc 0, isc 1, bmc 0, cyc_clk_acc 0, max_rec 9 (1024) 40c 000a3501 company_id 000a35 | 410 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a root directory ----------------------------------------------------------------- 414 000485ec directory_length 4, crc 34284 418 03000a35 vendor 41c 0c0083c0 node capabilities per IEEE 1394 420 8d000006 --> eui-64 leaf at 438 424 d1000001 --> unit directory at 428 unit directory at 428 ----------------------------------------------------------------- 428 000314c4 directory_length 3, crc 5316 42c 12000a35 specifier id 430 13000002 version 434 17101800 model eui-64 leaf at 438 ----------------------------------------------------------------- 438 000261a8 leaf_length 2, crc 25000 43c 000a3501 company_id 000a35 | 440 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 07:06:12 -06:00
.name = "Fireface400",
.pcm_capture_channels = {18, 14, 10},
.pcm_playback_channels = {18, 14, 10},
.midi_in_ports = 2,
.midi_out_ports = 2,
.protocol = &snd_ff_protocol_ff400,
.midi_high_addr = 0x0000801003f4ull,
.midi_addr_range = SND_FF_MAXIMIM_MIDI_QUADS * 4,
.midi_rx_addrs = {0x000080180000ull, 0x000080190000ull},
ALSA: fireface: add support for Fireface 400 Fireface 400 is a second model of RME Fireface series, released in 2006. This commit adds support for this model. This model supports 8 analog channels, 2 S/PDIF channels and 8 ADAT channels in both of tx/rx packet. The number of ADAT channels differs depending on each mode of sampling transmission frequency. $ python2 linux-firewire-utils/src/crpp < /sys/bus/firewire/devices/fw1/config_rom ROM header and bus information block ----------------------------------------------------------------- 400 04107768 bus_info_length 4, crc_length 16, crc 30568 (should be 61311) 404 31333934 bus_name "1394" 408 20009002 irmc 0, cmc 0, isc 1, bmc 0, cyc_clk_acc 0, max_rec 9 (1024) 40c 000a3501 company_id 000a35 | 410 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a root directory ----------------------------------------------------------------- 414 000485ec directory_length 4, crc 34284 418 03000a35 vendor 41c 0c0083c0 node capabilities per IEEE 1394 420 8d000006 --> eui-64 leaf at 438 424 d1000001 --> unit directory at 428 unit directory at 428 ----------------------------------------------------------------- 428 000314c4 directory_length 3, crc 5316 42c 12000a35 specifier id 430 13000002 version 434 17101800 model eui-64 leaf at 438 ----------------------------------------------------------------- 438 000261a8 leaf_length 2, crc 25000 43c 000a3501 company_id 000a35 | 440 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 07:06:12 -06:00
};
static const struct snd_ff_spec spec_ucx = {
.name = "FirefaceUCX",
.pcm_capture_channels = {18, 14, 12},
.pcm_playback_channels = {18, 14, 12},
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 06:17:02 -07:00
.midi_in_ports = 2,
ALSA: fireface: support rx MIDI functionality for Fireface UCX In latter model of Fireface series, asynchronous transaction includes a prefix byte to indicate the way to decode included MIDI bytes. Upper 4 bits of the prefix byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI messages. Basically the rest bits indicates the number of bytes for MIDI message. However, if the last byte of each MIDi message is included, the rest bits are 0xf. For example: message: f0 00 00 66 14 20 00 00 f7 offset: content (big endian, port 0) '0030: 0x02f00000 '0030: 0x03006614 '0030: 0x03200000 '0030: 0x0ff70000 This commit supports encoding scheme for the above and allows applications to transfer MIDI messages via ALSA rawmidi interface. An unused member (running_status) is reused to keep state of transmission of system exclusive messages. For your information, this is a dump of config rom. $ sudo ./hinawa-config-rom-printer /dev/fw1 { 'bus-info': { 'bmc': False, 'chip_ID': 13225063715, 'cmc': False, 'cyc_clk_acc': 0, 'imc': False, 'isc': True, 'max_rec': 512, 'name': '1394', 'node_vendor_ID': 2613}, 'root-directory': [ [ 'NODE_CAPABILITIES', { 'addressing': {'64': True, 'fix': True, 'prv': False}, 'misc': {'int': False, 'ms': False, 'spt': True}, 'state': { 'atn': False, 'ded': False, 'drq': True, 'elo': False, 'init': False, 'lst': True, 'off': False}, 'testing': {'bas': False, 'ext': False}}], ['VENDOR', 2613], ['DESCRIPTOR', 'RME!'], ['EUI_64', 2873037108442403], [ 'UNIT', [ ['SPECIFIER_ID', 2613], ['VERSION', 4], ['MODEL', 1054720], ['DESCRIPTOR', 'Fireface UCX']]]]} Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 06:17:05 -07:00
.midi_out_ports = 2,
.protocol = &snd_ff_protocol_latter,
ALSA: fireface: support tx MIDI functionality of Fireface UCX Fireface UCX transfers asynchronous transactions for MIDI messages. One transaction includes quadlet data therefore it can transfer 3 message bytes as maximum. Base address of the destination is configured by two settings; a register for higher 8 byte of the address, and a bitflag to option register indicates lower 8byte. The register for higher address is 0x'ffff'0000'0034. Unfortunately, firmware v24 includes a bug to ignore registered value for the destination address and transfers to 0x0001xxxxxxxx always. This driver doesn't work well if the bug exists, therefore users should install the latest firmware (v27). The bitflag is a part of value to be written to option register (0x'ffff'0000'0014). lower addr: bitflag (little endian) '0000'0000: 0x00002000 '0000'0080: 0x00004000 '0000'0100: 0x00008000 '0000'0180: 0x00010000 This register includes more options but they are not relevant to packet streaming or MIDI functionality. This driver don't touch it. Furthermore, the transaction is sent to address offset incremented by 4 byte to the offset in previous time. When it reaches base address plus 0x7c, next offset is the base address. Content of the transaction includes a prefix byte. Upper 4 bits of the byte indicates port number, and the rest 4 bits indicate the way to decode rest of bytes for MIDI message. Except for system exclusive messages, the rest bits are the same as status bits of the message without channel bits. For system exclusive messages, the rest bits are encoded according to included message bytes. For example: message: f0 7e 7f 09 01 f7 offset: content (little endian, port 0) '0000: 0x04f07e7f '0004: 0x070901f7 message: f0 00 00 66 14 20 00 00 00 f7 offset: content (little endian, port 1) '0014: 0x14f00000 '0018: 0x14661420 '001c: 0x14000000 '0020: 0x15f70000 message: f0 00 00 66 14 20 00 00 f7 offset: content (little endian, port 0) '0078: 0x04f00000 '007c: 0x04661420 '0000: 0x070000f7 This commit supports decoding scheme for the above and allows applications to receive MIDI messages via ALSA rawmidi interface. The lower 8 bytes of destination address is fixed to 0x'0000'0000, thus this driver expects userspace applications to configure option register with bitflag 0x00002000 in advance. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 06:17:02 -07:00
.midi_high_addr = 0xffff00000034ull,
.midi_addr_range = 0x80,
.midi_rx_addrs = {0xffff00000030ull, 0xffff00000030ull},
};
static const struct ieee1394_device_id snd_ff_id_table[] = {
/* Fireface 800 */
{
.match_flags = IEEE1394_MATCH_VENDOR_ID |
IEEE1394_MATCH_SPECIFIER_ID |
IEEE1394_MATCH_VERSION |
IEEE1394_MATCH_MODEL_ID,
.vendor_id = OUI_RME,
.specifier_id = OUI_RME,
.version = 0x000001,
.model_id = 0x101800,
.driver_data = (kernel_ulong_t)&spec_ff800,
},
ALSA: fireface: add support for Fireface 400 Fireface 400 is a second model of RME Fireface series, released in 2006. This commit adds support for this model. This model supports 8 analog channels, 2 S/PDIF channels and 8 ADAT channels in both of tx/rx packet. The number of ADAT channels differs depending on each mode of sampling transmission frequency. $ python2 linux-firewire-utils/src/crpp < /sys/bus/firewire/devices/fw1/config_rom ROM header and bus information block ----------------------------------------------------------------- 400 04107768 bus_info_length 4, crc_length 16, crc 30568 (should be 61311) 404 31333934 bus_name "1394" 408 20009002 irmc 0, cmc 0, isc 1, bmc 0, cyc_clk_acc 0, max_rec 9 (1024) 40c 000a3501 company_id 000a35 | 410 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a root directory ----------------------------------------------------------------- 414 000485ec directory_length 4, crc 34284 418 03000a35 vendor 41c 0c0083c0 node capabilities per IEEE 1394 420 8d000006 --> eui-64 leaf at 438 424 d1000001 --> unit directory at 428 unit directory at 428 ----------------------------------------------------------------- 428 000314c4 directory_length 3, crc 5316 42c 12000a35 specifier id 430 13000002 version 434 17101800 model eui-64 leaf at 438 ----------------------------------------------------------------- 438 000261a8 leaf_length 2, crc 25000 43c 000a3501 company_id 000a35 | 440 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 07:06:12 -06:00
/* Fireface 400 */
{
.match_flags = IEEE1394_MATCH_VENDOR_ID |
IEEE1394_MATCH_SPECIFIER_ID |
IEEE1394_MATCH_VERSION |
IEEE1394_MATCH_MODEL_ID,
.vendor_id = OUI_RME,
.specifier_id = OUI_RME,
ALSA: fireface: add support for Fireface 400 Fireface 400 is a second model of RME Fireface series, released in 2006. This commit adds support for this model. This model supports 8 analog channels, 2 S/PDIF channels and 8 ADAT channels in both of tx/rx packet. The number of ADAT channels differs depending on each mode of sampling transmission frequency. $ python2 linux-firewire-utils/src/crpp < /sys/bus/firewire/devices/fw1/config_rom ROM header and bus information block ----------------------------------------------------------------- 400 04107768 bus_info_length 4, crc_length 16, crc 30568 (should be 61311) 404 31333934 bus_name "1394" 408 20009002 irmc 0, cmc 0, isc 1, bmc 0, cyc_clk_acc 0, max_rec 9 (1024) 40c 000a3501 company_id 000a35 | 410 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a root directory ----------------------------------------------------------------- 414 000485ec directory_length 4, crc 34284 418 03000a35 vendor 41c 0c0083c0 node capabilities per IEEE 1394 420 8d000006 --> eui-64 leaf at 438 424 d1000001 --> unit directory at 428 unit directory at 428 ----------------------------------------------------------------- 428 000314c4 directory_length 3, crc 5316 42c 12000a35 specifier id 430 13000002 version 434 17101800 model eui-64 leaf at 438 ----------------------------------------------------------------- 438 000261a8 leaf_length 2, crc 25000 43c 000a3501 company_id 000a35 | 440 1bd0862a device_id 011bd0862a | EUI-64 000a35011bd0862a Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 07:06:12 -06:00
.version = 0x000002,
.model_id = 0x101800,
.driver_data = (kernel_ulong_t)&spec_ff400,
},
// Fireface UCX.
{
.match_flags = IEEE1394_MATCH_VENDOR_ID |
IEEE1394_MATCH_SPECIFIER_ID |
IEEE1394_MATCH_VERSION |
IEEE1394_MATCH_MODEL_ID,
.vendor_id = OUI_RME,
.specifier_id = OUI_RME,
.version = 0x000004,
.model_id = 0x101800,
.driver_data = (kernel_ulong_t)&spec_ucx,
},
{}
};
MODULE_DEVICE_TABLE(ieee1394, snd_ff_id_table);
static struct fw_driver ff_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "snd-fireface",
.bus = &fw_bus_type,
},
.probe = snd_ff_probe,
.update = snd_ff_update,
.remove = snd_ff_remove,
.id_table = snd_ff_id_table,
};
static int __init snd_ff_init(void)
{
return driver_register(&ff_driver.driver);
}
static void __exit snd_ff_exit(void)
{
driver_unregister(&ff_driver.driver);
}
module_init(snd_ff_init);
module_exit(snd_ff_exit);