2008-07-30 13:06:12 -06:00
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/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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2009-08-25 04:15:50 -06:00
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#include "i915_trace.h"
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2009-08-17 14:31:43 -06:00
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#include "intel_drv.h"
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2011-06-27 17:18:18 -06:00
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#include <linux/shmem_fs.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2008-07-30 13:06:12 -06:00
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#include <linux/swap.h>
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
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#include <linux/pci.h>
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2008-07-30 13:06:12 -06:00
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2011-01-07 10:09:48 -07:00
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static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
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2010-11-08 12:18:58 -07:00
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static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
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2011-01-07 10:09:48 -07:00
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static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
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bool write);
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static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
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uint64_t offset,
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uint64_t size);
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2010-11-08 12:18:58 -07:00
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static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
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2011-01-07 10:09:48 -07:00
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static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
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unsigned alignment,
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bool map_and_fenceable);
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2010-11-10 09:40:20 -07:00
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static void i915_gem_clear_fence_reg(struct drm_device *dev,
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struct drm_i915_fence_reg *reg);
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2010-11-08 12:18:58 -07:00
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static int i915_gem_phys_pwrite(struct drm_device *dev,
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struct drm_i915_gem_object *obj,
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2008-12-30 03:31:46 -07:00
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struct drm_i915_gem_pwrite *args,
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2010-11-08 12:18:58 -07:00
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struct drm_file *file);
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static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
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2008-07-30 13:06:12 -06:00
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2010-10-28 05:51:39 -06:00
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static int i915_gem_inactive_shrink(struct shrinker *shrinker,
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2011-05-24 18:12:27 -06:00
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struct shrink_control *sc);
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2009-09-14 09:50:28 -06:00
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2010-09-30 04:46:12 -06:00
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/* some bookkeeping */
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static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
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size_t size)
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{
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dev_priv->mm.object_count++;
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dev_priv->mm.object_memory += size;
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}
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static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
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size_t size)
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{
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dev_priv->mm.object_count--;
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dev_priv->mm.object_memory -= size;
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}
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2011-01-26 08:55:56 -07:00
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static int
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i915_gem_wait_for_error(struct drm_device *dev)
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2010-09-25 03:19:17 -06:00
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct completion *x = &dev_priv->error_completion;
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unsigned long flags;
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int ret;
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if (!atomic_read(&dev_priv->mm.wedged))
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return 0;
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ret = wait_for_completion_interruptible(x);
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if (ret)
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return ret;
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2011-01-26 08:55:56 -07:00
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if (atomic_read(&dev_priv->mm.wedged)) {
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/* GPU is hung, bump the completion count to account for
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* the token we just consumed so that we never hit zero and
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* end up waiting upon a subsequent completion event that
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* will never happen.
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*/
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spin_lock_irqsave(&x->wait.lock, flags);
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x->done++;
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spin_unlock_irqrestore(&x->wait.lock, flags);
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}
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return 0;
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2010-09-25 03:19:17 -06:00
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}
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2010-11-25 11:00:26 -07:00
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int i915_mutex_lock_interruptible(struct drm_device *dev)
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2010-09-25 04:22:51 -06:00
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{
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int ret;
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2011-01-26 08:55:56 -07:00
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ret = i915_gem_wait_for_error(dev);
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2010-09-25 04:22:51 -06:00
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if (ret)
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return ret;
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ret = mutex_lock_interruptible(&dev->struct_mutex);
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if (ret)
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return ret;
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2010-09-29 09:10:57 -06:00
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WARN_ON(i915_verify_lists(dev));
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2010-09-25 04:22:51 -06:00
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return 0;
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}
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2010-09-25 03:19:17 -06:00
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2010-08-07 14:45:03 -06:00
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static inline bool
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2010-11-08 12:18:58 -07:00
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i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
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2010-08-07 14:45:03 -06:00
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{
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2010-11-08 12:18:58 -07:00
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return obj->gtt_space && !obj->active && obj->pin_count == 0;
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2010-08-07 14:45:03 -06:00
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}
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2010-11-23 08:26:33 -07:00
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void i915_gem_do_init(struct drm_device *dev,
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unsigned long start,
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unsigned long mappable_end,
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unsigned long end)
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2008-07-30 13:06:12 -06:00
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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2011-01-21 03:54:32 -07:00
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drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
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2008-07-30 13:06:12 -06:00
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2011-01-21 03:54:32 -07:00
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dev_priv->mm.gtt_start = start;
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dev_priv->mm.gtt_mappable_end = mappable_end;
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dev_priv->mm.gtt_end = end;
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2010-09-30 04:46:12 -06:00
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dev_priv->mm.gtt_total = end - start;
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2010-10-01 14:05:20 -06:00
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dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
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2011-01-21 03:54:32 -07:00
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/* Take over this portion of the GTT */
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intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
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}
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2008-07-30 13:06:12 -06:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
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int
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i915_gem_init_ioctl(struct drm_device *dev, void *data,
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2010-11-08 12:18:58 -07:00
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struct drm_file *file)
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
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{
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struct drm_i915_gem_init *args = data;
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2010-11-23 08:26:33 -07:00
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if (args->gtt_start >= args->gtt_end ||
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(args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
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return -EINVAL;
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
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mutex_lock(&dev->struct_mutex);
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2010-11-23 08:26:33 -07:00
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i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
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2008-07-30 13:06:12 -06:00
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mutex_unlock(&dev->struct_mutex);
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2010-11-23 08:26:33 -07:00
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return 0;
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2008-07-30 13:06:12 -06:00
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}
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2008-10-22 22:40:13 -06:00
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int
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i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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2010-11-08 12:18:58 -07:00
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struct drm_file *file)
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2008-10-22 22:40:13 -06:00
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{
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2010-09-30 04:46:12 -06:00
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struct drm_i915_private *dev_priv = dev->dev_private;
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2008-10-22 22:40:13 -06:00
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struct drm_i915_gem_get_aperture *args = data;
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2010-11-24 05:23:44 -07:00
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struct drm_i915_gem_object *obj;
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size_t pinned;
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2008-10-22 22:40:13 -06:00
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if (!(dev->driver->driver_features & DRIVER_GEM))
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return -ENODEV;
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2010-11-24 05:23:44 -07:00
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pinned = 0;
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2010-09-30 04:46:12 -06:00
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mutex_lock(&dev->struct_mutex);
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2010-11-24 05:23:44 -07:00
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list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
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pinned += obj->gtt_space->size;
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2010-09-30 04:46:12 -06:00
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mutex_unlock(&dev->struct_mutex);
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2008-10-22 22:40:13 -06:00
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2010-11-24 05:23:44 -07:00
|
|
|
args->aper_size = dev_priv->mm.gtt_total;
|
2011-08-16 13:34:10 -06:00
|
|
|
args->aper_available_size = args->aper_size - pinned;
|
2010-11-24 05:23:44 -07:00
|
|
|
|
2008-10-22 22:40:13 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
static int
|
|
|
|
i915_gem_create(struct drm_file *file,
|
|
|
|
struct drm_device *dev,
|
|
|
|
uint64_t size,
|
|
|
|
uint32_t *handle_p)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2009-08-23 03:40:55 -06:00
|
|
|
int ret;
|
|
|
|
u32 handle;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
size = roundup(size, PAGE_SIZE);
|
2011-09-14 06:14:28 -06:00
|
|
|
if (size == 0)
|
|
|
|
return -EINVAL;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
/* Allocate the new object */
|
2011-02-06 19:16:14 -07:00
|
|
|
obj = i915_gem_alloc_object(dev, size);
|
2008-07-30 13:06:12 -06:00
|
|
|
if (obj == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
ret = drm_gem_handle_create(file, &obj->base, &handle);
|
2010-09-06 07:44:14 -06:00
|
|
|
if (ret) {
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_release(&obj->base);
|
|
|
|
i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
|
2010-10-14 06:20:40 -06:00
|
|
|
kfree(obj);
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
2010-09-06 07:44:14 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-14 06:20:40 -06:00
|
|
|
/* drop reference from allocate - handle holds it now */
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-14 06:20:40 -06:00
|
|
|
trace_i915_gem_object_create(obj);
|
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
*handle_p = handle;
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
int
|
|
|
|
i915_gem_dumb_create(struct drm_file *file,
|
|
|
|
struct drm_device *dev,
|
|
|
|
struct drm_mode_create_dumb *args)
|
|
|
|
{
|
|
|
|
/* have to work out size/pitch and return them */
|
2011-03-19 02:21:45 -06:00
|
|
|
args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
|
2011-02-06 19:16:14 -07:00
|
|
|
args->size = args->pitch * args->height;
|
|
|
|
return i915_gem_create(file, dev,
|
|
|
|
args->size, &args->handle);
|
|
|
|
}
|
|
|
|
|
|
|
|
int i915_gem_dumb_destroy(struct drm_file *file,
|
|
|
|
struct drm_device *dev,
|
|
|
|
uint32_t handle)
|
|
|
|
{
|
|
|
|
return drm_gem_handle_delete(file, handle);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Creates a new mm object and returns a handle to it.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
i915_gem_create_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_create *args = data;
|
|
|
|
return i915_gem_create(file, dev,
|
|
|
|
args->size, &args->handle);
|
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
|
2009-03-12 17:56:27 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
|
2009-03-12 17:56:27 -06:00
|
|
|
|
|
|
|
return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->tiling_mode != I915_TILING_NONE;
|
2009-03-12 17:56:27 -06:00
|
|
|
}
|
|
|
|
|
2010-05-27 07:15:34 -06:00
|
|
|
static inline void
|
2009-03-09 14:42:30 -06:00
|
|
|
slow_shmem_copy(struct page *dst_page,
|
|
|
|
int dst_offset,
|
|
|
|
struct page *src_page,
|
|
|
|
int src_offset,
|
|
|
|
int length)
|
|
|
|
{
|
|
|
|
char *dst_vaddr, *src_vaddr;
|
|
|
|
|
2010-05-27 07:15:34 -06:00
|
|
|
dst_vaddr = kmap(dst_page);
|
|
|
|
src_vaddr = kmap(src_page);
|
2009-03-09 14:42:30 -06:00
|
|
|
|
|
|
|
memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
|
|
|
|
|
2010-05-27 07:15:34 -06:00
|
|
|
kunmap(src_page);
|
|
|
|
kunmap(dst_page);
|
2009-03-09 14:42:30 -06:00
|
|
|
}
|
|
|
|
|
2010-05-27 07:15:34 -06:00
|
|
|
static inline void
|
2009-03-12 17:56:27 -06:00
|
|
|
slow_shmem_bit17_copy(struct page *gpu_page,
|
|
|
|
int gpu_offset,
|
|
|
|
struct page *cpu_page,
|
|
|
|
int cpu_offset,
|
|
|
|
int length,
|
|
|
|
int is_read)
|
|
|
|
{
|
|
|
|
char *gpu_vaddr, *cpu_vaddr;
|
|
|
|
|
|
|
|
/* Use the unswizzled path if this page isn't affected. */
|
|
|
|
if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
|
|
|
|
if (is_read)
|
|
|
|
return slow_shmem_copy(cpu_page, cpu_offset,
|
|
|
|
gpu_page, gpu_offset, length);
|
|
|
|
else
|
|
|
|
return slow_shmem_copy(gpu_page, gpu_offset,
|
|
|
|
cpu_page, cpu_offset, length);
|
|
|
|
}
|
|
|
|
|
2010-05-27 07:15:34 -06:00
|
|
|
gpu_vaddr = kmap(gpu_page);
|
|
|
|
cpu_vaddr = kmap(cpu_page);
|
2009-03-12 17:56:27 -06:00
|
|
|
|
|
|
|
/* Copy the data, XORing A6 with A17 (1). The user already knows he's
|
|
|
|
* XORing with the other bits (A9 for Y, A9 and A10 for X)
|
|
|
|
*/
|
|
|
|
while (length > 0) {
|
|
|
|
int cacheline_end = ALIGN(gpu_offset + 1, 64);
|
|
|
|
int this_length = min(cacheline_end - gpu_offset, length);
|
|
|
|
int swizzled_gpu_offset = gpu_offset ^ 64;
|
|
|
|
|
|
|
|
if (is_read) {
|
|
|
|
memcpy(cpu_vaddr + cpu_offset,
|
|
|
|
gpu_vaddr + swizzled_gpu_offset,
|
|
|
|
this_length);
|
|
|
|
} else {
|
|
|
|
memcpy(gpu_vaddr + swizzled_gpu_offset,
|
|
|
|
cpu_vaddr + cpu_offset,
|
|
|
|
this_length);
|
|
|
|
}
|
|
|
|
cpu_offset += this_length;
|
|
|
|
gpu_offset += this_length;
|
|
|
|
length -= this_length;
|
|
|
|
}
|
|
|
|
|
2010-05-27 07:15:34 -06:00
|
|
|
kunmap(cpu_page);
|
|
|
|
kunmap(gpu_page);
|
2009-03-12 17:56:27 -06:00
|
|
|
}
|
|
|
|
|
2009-03-10 12:44:52 -06:00
|
|
|
/**
|
|
|
|
* This is the fast shmem pread path, which attempts to copy_from_user directly
|
|
|
|
* from the backing pages of the object to the user's address space. On a
|
|
|
|
* fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
|
|
|
|
*/
|
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_shmem_pread_fast(struct drm_device *dev,
|
|
|
|
struct drm_i915_gem_object *obj,
|
2009-03-10 12:44:52 -06:00
|
|
|
struct drm_i915_gem_pread *args,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2009-03-10 12:44:52 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
|
2009-03-10 12:44:52 -06:00
|
|
|
ssize_t remain;
|
2010-10-28 06:45:36 -06:00
|
|
|
loff_t offset;
|
2009-03-10 12:44:52 -06:00
|
|
|
char __user *user_data;
|
|
|
|
int page_offset, page_length;
|
|
|
|
|
|
|
|
user_data = (char __user *) (uintptr_t) args->data_ptr;
|
|
|
|
remain = args->size;
|
|
|
|
|
|
|
|
offset = args->offset;
|
|
|
|
|
|
|
|
while (remain > 0) {
|
2010-10-28 06:45:36 -06:00
|
|
|
struct page *page;
|
|
|
|
char *vaddr;
|
|
|
|
int ret;
|
|
|
|
|
2009-03-10 12:44:52 -06:00
|
|
|
/* Operation in this page
|
|
|
|
*
|
|
|
|
* page_offset = offset within page
|
|
|
|
* page_length = bytes to copy for this page
|
|
|
|
*/
|
2011-05-12 15:17:11 -06:00
|
|
|
page_offset = offset_in_page(offset);
|
2009-03-10 12:44:52 -06:00
|
|
|
page_length = remain;
|
|
|
|
if ((page_offset + remain) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - page_offset;
|
|
|
|
|
2011-06-27 17:18:18 -06:00
|
|
|
page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
|
2010-10-28 06:45:36 -06:00
|
|
|
if (IS_ERR(page))
|
|
|
|
return PTR_ERR(page);
|
|
|
|
|
|
|
|
vaddr = kmap_atomic(page);
|
|
|
|
ret = __copy_to_user_inatomic(user_data,
|
|
|
|
vaddr + page_offset,
|
|
|
|
page_length);
|
|
|
|
kunmap_atomic(vaddr);
|
|
|
|
|
|
|
|
mark_page_accessed(page);
|
|
|
|
page_cache_release(page);
|
|
|
|
if (ret)
|
2010-10-14 08:26:45 -06:00
|
|
|
return -EFAULT;
|
2009-03-10 12:44:52 -06:00
|
|
|
|
|
|
|
remain -= page_length;
|
|
|
|
user_data += page_length;
|
|
|
|
offset += page_length;
|
|
|
|
}
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
return 0;
|
2009-03-10 12:44:52 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* This is the fallback shmem pread path, which allocates temporary storage
|
|
|
|
* in kernel space to copy_to_user into outside of the struct_mutex, so we
|
|
|
|
* can copy out of the object's backing pages while holding the struct mutex
|
|
|
|
* and not take page faults.
|
|
|
|
*/
|
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_shmem_pread_slow(struct drm_device *dev,
|
|
|
|
struct drm_i915_gem_object *obj,
|
2009-03-10 12:44:52 -06:00
|
|
|
struct drm_i915_gem_pread *args,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2009-03-10 12:44:52 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
|
2009-03-10 12:44:52 -06:00
|
|
|
struct mm_struct *mm = current->mm;
|
|
|
|
struct page **user_pages;
|
|
|
|
ssize_t remain;
|
|
|
|
loff_t offset, pinned_pages, i;
|
|
|
|
loff_t first_data_page, last_data_page, num_pages;
|
2010-10-28 06:45:36 -06:00
|
|
|
int shmem_page_offset;
|
|
|
|
int data_page_index, data_page_offset;
|
2009-03-10 12:44:52 -06:00
|
|
|
int page_length;
|
|
|
|
int ret;
|
|
|
|
uint64_t data_ptr = args->data_ptr;
|
2009-03-12 17:56:27 -06:00
|
|
|
int do_bit17_swizzling;
|
2009-03-10 12:44:52 -06:00
|
|
|
|
|
|
|
remain = args->size;
|
|
|
|
|
|
|
|
/* Pin the user pages containing the data. We can't fault while
|
|
|
|
* holding the struct mutex, yet we want to hold it while
|
|
|
|
* dereferencing the user data.
|
|
|
|
*/
|
|
|
|
first_data_page = data_ptr / PAGE_SIZE;
|
|
|
|
last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
|
|
|
|
num_pages = last_data_page - first_data_page + 1;
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
|
2009-03-10 12:44:52 -06:00
|
|
|
if (user_pages == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-03-10 12:44:52 -06:00
|
|
|
down_read(&mm->mmap_sem);
|
|
|
|
pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
|
2009-04-07 17:01:22 -06:00
|
|
|
num_pages, 1, 0, user_pages, NULL);
|
2009-03-10 12:44:52 -06:00
|
|
|
up_read(&mm->mmap_sem);
|
2010-10-14 08:26:45 -06:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2009-03-10 12:44:52 -06:00
|
|
|
if (pinned_pages < num_pages) {
|
|
|
|
ret = -EFAULT;
|
2010-10-14 08:26:45 -06:00
|
|
|
goto out;
|
2009-03-10 12:44:52 -06:00
|
|
|
}
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
ret = i915_gem_object_set_cpu_read_domain_range(obj,
|
|
|
|
args->offset,
|
|
|
|
args->size);
|
2009-09-14 09:50:30 -06:00
|
|
|
if (ret)
|
2010-10-14 08:26:45 -06:00
|
|
|
goto out;
|
2009-03-10 12:44:52 -06:00
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
|
2009-03-10 12:44:52 -06:00
|
|
|
|
|
|
|
offset = args->offset;
|
|
|
|
|
|
|
|
while (remain > 0) {
|
2010-10-28 06:45:36 -06:00
|
|
|
struct page *page;
|
|
|
|
|
2009-03-10 12:44:52 -06:00
|
|
|
/* Operation in this page
|
|
|
|
*
|
|
|
|
* shmem_page_offset = offset within page in shmem file
|
|
|
|
* data_page_index = page number in get_user_pages return
|
|
|
|
* data_page_offset = offset with data_page_index page.
|
|
|
|
* page_length = bytes to copy for this page
|
|
|
|
*/
|
2011-05-12 15:17:11 -06:00
|
|
|
shmem_page_offset = offset_in_page(offset);
|
2009-03-10 12:44:52 -06:00
|
|
|
data_page_index = data_ptr / PAGE_SIZE - first_data_page;
|
2011-05-12 15:17:11 -06:00
|
|
|
data_page_offset = offset_in_page(data_ptr);
|
2009-03-10 12:44:52 -06:00
|
|
|
|
|
|
|
page_length = remain;
|
|
|
|
if ((shmem_page_offset + page_length) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - shmem_page_offset;
|
|
|
|
if ((data_page_offset + page_length) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - data_page_offset;
|
|
|
|
|
2011-06-27 17:18:18 -06:00
|
|
|
page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
|
2011-06-12 14:53:44 -06:00
|
|
|
if (IS_ERR(page)) {
|
|
|
|
ret = PTR_ERR(page);
|
|
|
|
goto out;
|
|
|
|
}
|
2010-10-28 06:45:36 -06:00
|
|
|
|
2009-03-12 17:56:27 -06:00
|
|
|
if (do_bit17_swizzling) {
|
2010-10-28 06:45:36 -06:00
|
|
|
slow_shmem_bit17_copy(page,
|
2009-03-12 17:56:27 -06:00
|
|
|
shmem_page_offset,
|
2010-05-27 07:15:34 -06:00
|
|
|
user_pages[data_page_index],
|
|
|
|
data_page_offset,
|
|
|
|
page_length,
|
|
|
|
1);
|
|
|
|
} else {
|
|
|
|
slow_shmem_copy(user_pages[data_page_index],
|
|
|
|
data_page_offset,
|
2010-10-28 06:45:36 -06:00
|
|
|
page,
|
2010-05-27 07:15:34 -06:00
|
|
|
shmem_page_offset,
|
|
|
|
page_length);
|
2009-03-12 17:56:27 -06:00
|
|
|
}
|
2009-03-10 12:44:52 -06:00
|
|
|
|
2010-10-28 06:45:36 -06:00
|
|
|
mark_page_accessed(page);
|
|
|
|
page_cache_release(page);
|
|
|
|
|
2009-03-10 12:44:52 -06:00
|
|
|
remain -= page_length;
|
|
|
|
data_ptr += page_length;
|
|
|
|
offset += page_length;
|
|
|
|
}
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
out:
|
2009-03-10 12:44:52 -06:00
|
|
|
for (i = 0; i < pinned_pages; i++) {
|
|
|
|
SetPageDirty(user_pages[i]);
|
2010-10-28 06:45:36 -06:00
|
|
|
mark_page_accessed(user_pages[i]);
|
2009-03-10 12:44:52 -06:00
|
|
|
page_cache_release(user_pages[i]);
|
|
|
|
}
|
2009-05-08 17:13:25 -06:00
|
|
|
drm_free_large(user_pages);
|
2009-03-10 12:44:52 -06:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/**
|
|
|
|
* Reads data from the object referenced by handle.
|
|
|
|
*
|
|
|
|
* On error, the contents of *data are undefined.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_pread *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-26 13:23:38 -06:00
|
|
|
int ret = 0;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-17 02:10:42 -07:00
|
|
|
if (args->size == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!access_ok(VERIFY_WRITE,
|
|
|
|
(char __user *)(uintptr_t)args->data_ptr,
|
|
|
|
args->size))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
|
|
|
|
args->size);
|
|
|
|
if (ret)
|
|
|
|
return -EFAULT;
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
2010-10-14 08:26:45 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2010-10-14 08:26:45 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-26 13:21:44 -06:00
|
|
|
/* Bounds check source. */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (args->offset > obj->base.size ||
|
|
|
|
args->size > obj->base.size - args->offset) {
|
2010-09-26 13:50:05 -06:00
|
|
|
ret = -EINVAL;
|
2010-09-26 13:23:38 -06:00
|
|
|
goto out;
|
2010-09-26 13:50:05 -06:00
|
|
|
}
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_object_pread(obj, args->offset, args->size);
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
ret = i915_gem_object_set_cpu_read_domain_range(obj,
|
|
|
|
args->offset,
|
|
|
|
args->size);
|
|
|
|
if (ret)
|
2010-10-28 06:45:36 -06:00
|
|
|
goto out;
|
2010-10-14 08:26:45 -06:00
|
|
|
|
|
|
|
ret = -EFAULT;
|
|
|
|
if (!i915_gem_object_needs_bit17_swizzle(obj))
|
2010-11-08 12:18:58 -07:00
|
|
|
ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
|
2010-10-14 08:26:45 -06:00
|
|
|
if (ret == -EFAULT)
|
2010-11-08 12:18:58 -07:00
|
|
|
ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-26 13:23:38 -06:00
|
|
|
out:
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2010-10-14 08:26:45 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-03-10 12:44:52 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2008-10-30 20:38:48 -06:00
|
|
|
/* This is the fast write path which cannot handle
|
|
|
|
* page faults in the source data
|
2008-10-20 15:16:43 -06:00
|
|
|
*/
|
2008-10-30 20:38:48 -06:00
|
|
|
|
|
|
|
static inline int
|
|
|
|
fast_user_write(struct io_mapping *mapping,
|
|
|
|
loff_t page_base, int page_offset,
|
|
|
|
char __user *user_data,
|
|
|
|
int length)
|
2008-10-20 15:16:43 -06:00
|
|
|
{
|
|
|
|
char *vaddr_atomic;
|
2008-10-30 20:38:48 -06:00
|
|
|
unsigned long unwritten;
|
2008-10-20 15:16:43 -06:00
|
|
|
|
2010-10-26 15:21:51 -06:00
|
|
|
vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
|
2008-10-30 20:38:48 -06:00
|
|
|
unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
|
|
|
|
user_data, length);
|
2010-10-26 15:21:51 -06:00
|
|
|
io_mapping_unmap_atomic(vaddr_atomic);
|
2010-10-14 08:03:58 -06:00
|
|
|
return unwritten;
|
2008-10-30 20:38:48 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Here's the write path which can sleep for
|
|
|
|
* page faults
|
|
|
|
*/
|
|
|
|
|
2010-05-27 07:15:35 -06:00
|
|
|
static inline void
|
2009-03-09 10:42:23 -06:00
|
|
|
slow_kernel_write(struct io_mapping *mapping,
|
|
|
|
loff_t gtt_base, int gtt_offset,
|
|
|
|
struct page *user_page, int user_offset,
|
|
|
|
int length)
|
2008-10-30 20:38:48 -06:00
|
|
|
{
|
2010-05-27 07:15:35 -06:00
|
|
|
char __iomem *dst_vaddr;
|
|
|
|
char *src_vaddr;
|
2008-10-30 20:38:48 -06:00
|
|
|
|
2010-05-27 07:15:35 -06:00
|
|
|
dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
|
|
|
|
src_vaddr = kmap(user_page);
|
|
|
|
|
|
|
|
memcpy_toio(dst_vaddr + gtt_offset,
|
|
|
|
src_vaddr + user_offset,
|
|
|
|
length);
|
|
|
|
|
|
|
|
kunmap(user_page);
|
|
|
|
io_mapping_unmap(dst_vaddr);
|
2008-10-20 15:16:43 -06:00
|
|
|
}
|
|
|
|
|
2009-03-09 10:42:23 -06:00
|
|
|
/**
|
|
|
|
* This is the fast pwrite path, where we copy the data directly from the
|
|
|
|
* user into the GTT, uncached.
|
|
|
|
*/
|
2008-07-30 13:06:12 -06:00
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_gtt_pwrite_fast(struct drm_device *dev,
|
|
|
|
struct drm_i915_gem_object *obj,
|
2009-03-09 10:42:23 -06:00
|
|
|
struct drm_i915_gem_pwrite *args,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2008-10-30 20:38:48 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2008-07-30 13:06:12 -06:00
|
|
|
ssize_t remain;
|
2008-10-30 20:38:48 -06:00
|
|
|
loff_t offset, page_base;
|
2008-07-30 13:06:12 -06:00
|
|
|
char __user *user_data;
|
2008-10-30 20:38:48 -06:00
|
|
|
int page_offset, page_length;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
user_data = (char __user *) (uintptr_t) args->data_ptr;
|
|
|
|
remain = args->size;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
offset = obj->gtt_offset + args->offset;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
while (remain > 0) {
|
|
|
|
/* Operation in this page
|
|
|
|
*
|
2008-10-30 20:38:48 -06:00
|
|
|
* page_base = page offset within aperture
|
|
|
|
* page_offset = offset within page
|
|
|
|
* page_length = bytes to copy for this page
|
2008-07-30 13:06:12 -06:00
|
|
|
*/
|
2011-05-12 15:17:11 -06:00
|
|
|
page_base = offset & PAGE_MASK;
|
|
|
|
page_offset = offset_in_page(offset);
|
2008-10-30 20:38:48 -06:00
|
|
|
page_length = remain;
|
|
|
|
if ((page_offset + remain) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - page_offset;
|
|
|
|
|
|
|
|
/* If we get a fault while copying data, then (presumably) our
|
2009-03-09 10:42:23 -06:00
|
|
|
* source page isn't available. Return the error and we'll
|
|
|
|
* retry in the slow path.
|
2008-10-30 20:38:48 -06:00
|
|
|
*/
|
2010-10-14 08:03:58 -06:00
|
|
|
if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
|
|
|
|
page_offset, user_data, page_length))
|
|
|
|
return -EFAULT;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2008-10-30 20:38:48 -06:00
|
|
|
remain -= page_length;
|
|
|
|
user_data += page_length;
|
|
|
|
offset += page_length;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
return 0;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2009-03-09 10:42:23 -06:00
|
|
|
/**
|
|
|
|
* This is the fallback GTT pwrite path, which uses get_user_pages to pin
|
|
|
|
* the memory and maps it using kmap_atomic for copying.
|
|
|
|
*
|
|
|
|
* This code resulted in x11perf -rgb10text consuming about 10% more CPU
|
|
|
|
* than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
|
|
|
|
*/
|
2008-10-02 13:24:47 -06:00
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_gtt_pwrite_slow(struct drm_device *dev,
|
|
|
|
struct drm_i915_gem_object *obj,
|
2009-03-09 10:42:23 -06:00
|
|
|
struct drm_i915_gem_pwrite *args,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2009-03-09 10:42:23 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
ssize_t remain;
|
|
|
|
loff_t gtt_page_base, offset;
|
|
|
|
loff_t first_data_page, last_data_page, num_pages;
|
|
|
|
loff_t pinned_pages, i;
|
|
|
|
struct page **user_pages;
|
|
|
|
struct mm_struct *mm = current->mm;
|
|
|
|
int gtt_page_offset, data_page_offset, data_page_index, page_length;
|
2008-07-30 13:06:12 -06:00
|
|
|
int ret;
|
2009-03-09 10:42:23 -06:00
|
|
|
uint64_t data_ptr = args->data_ptr;
|
|
|
|
|
|
|
|
remain = args->size;
|
|
|
|
|
|
|
|
/* Pin the user pages containing the data. We can't fault while
|
|
|
|
* holding the struct mutex, and all of the pwrite implementations
|
|
|
|
* want to hold it while dereferencing the user data.
|
|
|
|
*/
|
|
|
|
first_data_page = data_ptr / PAGE_SIZE;
|
|
|
|
last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
|
|
|
|
num_pages = last_data_page - first_data_page + 1;
|
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
|
2009-03-09 10:42:23 -06:00
|
|
|
if (user_pages == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-03-09 10:42:23 -06:00
|
|
|
down_read(&mm->mmap_sem);
|
|
|
|
pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
|
|
|
|
num_pages, 0, 0, user_pages, NULL);
|
|
|
|
up_read(&mm->mmap_sem);
|
2010-10-14 08:03:58 -06:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2009-03-09 10:42:23 -06:00
|
|
|
if (pinned_pages < num_pages) {
|
|
|
|
ret = -EFAULT;
|
|
|
|
goto out_unpin_pages;
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
ret = i915_gem_object_set_to_gtt_domain(obj, true);
|
|
|
|
if (ret)
|
|
|
|
goto out_unpin_pages;
|
|
|
|
|
|
|
|
ret = i915_gem_object_put_fence(obj);
|
2009-03-09 10:42:23 -06:00
|
|
|
if (ret)
|
2010-10-14 08:03:58 -06:00
|
|
|
goto out_unpin_pages;
|
2009-03-09 10:42:23 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
offset = obj->gtt_offset + args->offset;
|
2009-03-09 10:42:23 -06:00
|
|
|
|
|
|
|
while (remain > 0) {
|
|
|
|
/* Operation in this page
|
|
|
|
*
|
|
|
|
* gtt_page_base = page offset within aperture
|
|
|
|
* gtt_page_offset = offset within page in aperture
|
|
|
|
* data_page_index = page number in get_user_pages return
|
|
|
|
* data_page_offset = offset with data_page_index page.
|
|
|
|
* page_length = bytes to copy for this page
|
|
|
|
*/
|
|
|
|
gtt_page_base = offset & PAGE_MASK;
|
2011-05-12 15:17:11 -06:00
|
|
|
gtt_page_offset = offset_in_page(offset);
|
2009-03-09 10:42:23 -06:00
|
|
|
data_page_index = data_ptr / PAGE_SIZE - first_data_page;
|
2011-05-12 15:17:11 -06:00
|
|
|
data_page_offset = offset_in_page(data_ptr);
|
2009-03-09 10:42:23 -06:00
|
|
|
|
|
|
|
page_length = remain;
|
|
|
|
if ((gtt_page_offset + page_length) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - gtt_page_offset;
|
|
|
|
if ((data_page_offset + page_length) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - data_page_offset;
|
|
|
|
|
2010-05-27 07:15:35 -06:00
|
|
|
slow_kernel_write(dev_priv->mm.gtt_mapping,
|
|
|
|
gtt_page_base, gtt_page_offset,
|
|
|
|
user_pages[data_page_index],
|
|
|
|
data_page_offset,
|
|
|
|
page_length);
|
2009-03-09 10:42:23 -06:00
|
|
|
|
|
|
|
remain -= page_length;
|
|
|
|
offset += page_length;
|
|
|
|
data_ptr += page_length;
|
|
|
|
}
|
|
|
|
|
|
|
|
out_unpin_pages:
|
|
|
|
for (i = 0; i < pinned_pages; i++)
|
|
|
|
page_cache_release(user_pages[i]);
|
2009-05-08 17:13:25 -06:00
|
|
|
drm_free_large(user_pages);
|
2009-03-09 10:42:23 -06:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-03-09 14:42:30 -06:00
|
|
|
/**
|
|
|
|
* This is the fast shmem pwrite path, which attempts to directly
|
|
|
|
* copy_from_user into the kmapped pages backing the object.
|
|
|
|
*/
|
2008-10-02 13:24:47 -06:00
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_shmem_pwrite_fast(struct drm_device *dev,
|
|
|
|
struct drm_i915_gem_object *obj,
|
2009-03-09 14:42:30 -06:00
|
|
|
struct drm_i915_gem_pwrite *args,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
|
2009-03-09 14:42:30 -06:00
|
|
|
ssize_t remain;
|
2010-10-28 06:45:36 -06:00
|
|
|
loff_t offset;
|
2009-03-09 14:42:30 -06:00
|
|
|
char __user *user_data;
|
|
|
|
int page_offset, page_length;
|
|
|
|
|
|
|
|
user_data = (char __user *) (uintptr_t) args->data_ptr;
|
|
|
|
remain = args->size;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2009-03-09 14:42:30 -06:00
|
|
|
offset = args->offset;
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->dirty = 1;
|
2009-03-09 14:42:30 -06:00
|
|
|
|
|
|
|
while (remain > 0) {
|
2010-10-28 06:45:36 -06:00
|
|
|
struct page *page;
|
|
|
|
char *vaddr;
|
|
|
|
int ret;
|
|
|
|
|
2009-03-09 14:42:30 -06:00
|
|
|
/* Operation in this page
|
|
|
|
*
|
|
|
|
* page_offset = offset within page
|
|
|
|
* page_length = bytes to copy for this page
|
|
|
|
*/
|
2011-05-12 15:17:11 -06:00
|
|
|
page_offset = offset_in_page(offset);
|
2009-03-09 14:42:30 -06:00
|
|
|
page_length = remain;
|
|
|
|
if ((page_offset + remain) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - page_offset;
|
|
|
|
|
2011-06-27 17:18:18 -06:00
|
|
|
page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
|
2010-10-28 06:45:36 -06:00
|
|
|
if (IS_ERR(page))
|
|
|
|
return PTR_ERR(page);
|
|
|
|
|
2011-09-17 12:55:46 -06:00
|
|
|
vaddr = kmap_atomic(page);
|
2010-10-28 06:45:36 -06:00
|
|
|
ret = __copy_from_user_inatomic(vaddr + page_offset,
|
|
|
|
user_data,
|
|
|
|
page_length);
|
2011-09-17 12:55:46 -06:00
|
|
|
kunmap_atomic(vaddr);
|
2010-10-28 06:45:36 -06:00
|
|
|
|
|
|
|
set_page_dirty(page);
|
|
|
|
mark_page_accessed(page);
|
|
|
|
page_cache_release(page);
|
|
|
|
|
|
|
|
/* If we get a fault while copying data, then (presumably) our
|
|
|
|
* source page isn't available. Return the error and we'll
|
|
|
|
* retry in the slow path.
|
|
|
|
*/
|
|
|
|
if (ret)
|
2010-10-14 08:03:58 -06:00
|
|
|
return -EFAULT;
|
2009-03-09 14:42:30 -06:00
|
|
|
|
|
|
|
remain -= page_length;
|
|
|
|
user_data += page_length;
|
|
|
|
offset += page_length;
|
|
|
|
}
|
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
return 0;
|
2009-03-09 14:42:30 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* This is the fallback shmem pwrite path, which uses get_user_pages to pin
|
|
|
|
* the memory and maps it using kmap_atomic for copying.
|
|
|
|
*
|
|
|
|
* This avoids taking mmap_sem for faulting on the user's address while the
|
|
|
|
* struct_mutex is held.
|
|
|
|
*/
|
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_shmem_pwrite_slow(struct drm_device *dev,
|
|
|
|
struct drm_i915_gem_object *obj,
|
2009-03-09 14:42:30 -06:00
|
|
|
struct drm_i915_gem_pwrite *args,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2009-03-09 14:42:30 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
|
2009-03-09 14:42:30 -06:00
|
|
|
struct mm_struct *mm = current->mm;
|
|
|
|
struct page **user_pages;
|
|
|
|
ssize_t remain;
|
|
|
|
loff_t offset, pinned_pages, i;
|
|
|
|
loff_t first_data_page, last_data_page, num_pages;
|
2010-10-28 06:45:36 -06:00
|
|
|
int shmem_page_offset;
|
2009-03-09 14:42:30 -06:00
|
|
|
int data_page_index, data_page_offset;
|
|
|
|
int page_length;
|
|
|
|
int ret;
|
|
|
|
uint64_t data_ptr = args->data_ptr;
|
2009-03-12 17:56:27 -06:00
|
|
|
int do_bit17_swizzling;
|
2009-03-09 14:42:30 -06:00
|
|
|
|
|
|
|
remain = args->size;
|
|
|
|
|
|
|
|
/* Pin the user pages containing the data. We can't fault while
|
|
|
|
* holding the struct mutex, and all of the pwrite implementations
|
|
|
|
* want to hold it while dereferencing the user data.
|
|
|
|
*/
|
|
|
|
first_data_page = data_ptr / PAGE_SIZE;
|
|
|
|
last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
|
|
|
|
num_pages = last_data_page - first_data_page + 1;
|
|
|
|
|
2010-10-14 08:26:45 -06:00
|
|
|
user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
|
2009-03-09 14:42:30 -06:00
|
|
|
if (user_pages == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-03-09 14:42:30 -06:00
|
|
|
down_read(&mm->mmap_sem);
|
|
|
|
pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
|
|
|
|
num_pages, 0, 0, user_pages, NULL);
|
|
|
|
up_read(&mm->mmap_sem);
|
2010-10-14 08:03:58 -06:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2009-03-09 14:42:30 -06:00
|
|
|
if (pinned_pages < num_pages) {
|
|
|
|
ret = -EFAULT;
|
2010-10-14 08:03:58 -06:00
|
|
|
goto out;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
ret = i915_gem_object_set_to_cpu_domain(obj, 1);
|
2009-09-14 09:50:30 -06:00
|
|
|
if (ret)
|
2010-10-14 08:03:58 -06:00
|
|
|
goto out;
|
2009-03-09 14:42:30 -06:00
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
|
2009-03-09 14:42:30 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
offset = args->offset;
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->dirty = 1;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2009-03-09 14:42:30 -06:00
|
|
|
while (remain > 0) {
|
2010-10-28 06:45:36 -06:00
|
|
|
struct page *page;
|
|
|
|
|
2009-03-09 14:42:30 -06:00
|
|
|
/* Operation in this page
|
|
|
|
*
|
|
|
|
* shmem_page_offset = offset within page in shmem file
|
|
|
|
* data_page_index = page number in get_user_pages return
|
|
|
|
* data_page_offset = offset with data_page_index page.
|
|
|
|
* page_length = bytes to copy for this page
|
|
|
|
*/
|
2011-05-12 15:17:11 -06:00
|
|
|
shmem_page_offset = offset_in_page(offset);
|
2009-03-09 14:42:30 -06:00
|
|
|
data_page_index = data_ptr / PAGE_SIZE - first_data_page;
|
2011-05-12 15:17:11 -06:00
|
|
|
data_page_offset = offset_in_page(data_ptr);
|
2009-03-09 14:42:30 -06:00
|
|
|
|
|
|
|
page_length = remain;
|
|
|
|
if ((shmem_page_offset + page_length) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - shmem_page_offset;
|
|
|
|
if ((data_page_offset + page_length) > PAGE_SIZE)
|
|
|
|
page_length = PAGE_SIZE - data_page_offset;
|
|
|
|
|
2011-06-27 17:18:18 -06:00
|
|
|
page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
|
2010-10-28 06:45:36 -06:00
|
|
|
if (IS_ERR(page)) {
|
|
|
|
ret = PTR_ERR(page);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2009-03-12 17:56:27 -06:00
|
|
|
if (do_bit17_swizzling) {
|
2010-10-28 06:45:36 -06:00
|
|
|
slow_shmem_bit17_copy(page,
|
2009-03-12 17:56:27 -06:00
|
|
|
shmem_page_offset,
|
|
|
|
user_pages[data_page_index],
|
|
|
|
data_page_offset,
|
2010-05-27 07:15:34 -06:00
|
|
|
page_length,
|
|
|
|
0);
|
|
|
|
} else {
|
2010-10-28 06:45:36 -06:00
|
|
|
slow_shmem_copy(page,
|
2010-05-27 07:15:34 -06:00
|
|
|
shmem_page_offset,
|
|
|
|
user_pages[data_page_index],
|
|
|
|
data_page_offset,
|
|
|
|
page_length);
|
2009-03-12 17:56:27 -06:00
|
|
|
}
|
2009-03-09 14:42:30 -06:00
|
|
|
|
2010-10-28 06:45:36 -06:00
|
|
|
set_page_dirty(page);
|
|
|
|
mark_page_accessed(page);
|
|
|
|
page_cache_release(page);
|
|
|
|
|
2009-03-09 14:42:30 -06:00
|
|
|
remain -= page_length;
|
|
|
|
data_ptr += page_length;
|
|
|
|
offset += page_length;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
out:
|
2009-03-09 14:42:30 -06:00
|
|
|
for (i = 0; i < pinned_pages; i++)
|
|
|
|
page_cache_release(user_pages[i]);
|
2009-05-08 17:13:25 -06:00
|
|
|
drm_free_large(user_pages);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2009-03-09 14:42:30 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Writes data to the object referenced by handle.
|
|
|
|
*
|
|
|
|
* On error, the contents of the buffer that were to be modified are undefined.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
|
2010-10-14 08:03:58 -06:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_pwrite *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-11-17 02:10:42 -07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (args->size == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!access_ok(VERIFY_READ,
|
|
|
|
(char __user *)(uintptr_t)args->data_ptr,
|
|
|
|
args->size))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
|
|
|
|
args->size);
|
|
|
|
if (ret)
|
|
|
|
return -EFAULT;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
2010-10-14 08:03:58 -06:00
|
|
|
return ret;
|
2010-10-17 02:45:41 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2010-10-14 08:03:58 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-26 13:21:44 -06:00
|
|
|
/* Bounds check destination. */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (args->offset > obj->base.size ||
|
|
|
|
args->size > obj->base.size - args->offset) {
|
2010-09-26 13:50:05 -06:00
|
|
|
ret = -EINVAL;
|
2010-09-26 13:23:38 -06:00
|
|
|
goto out;
|
2010-09-26 13:50:05 -06:00
|
|
|
}
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_object_pwrite(obj, args->offset, args->size);
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/* We can only do the GTT pwrite on untiled buffers, as otherwise
|
|
|
|
* it would end up going through the fenced access, and we'll get
|
|
|
|
* different detiling behavior between reading and writing.
|
|
|
|
* pread/pwrite currently are reading and writing from the CPU
|
|
|
|
* perspective, requiring manual detiling by the client.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->phys_obj)
|
2010-10-14 08:03:58 -06:00
|
|
|
ret = i915_gem_phys_pwrite(dev, obj, args, file);
|
2010-11-10 09:40:20 -07:00
|
|
|
else if (obj->gtt_space &&
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
|
2010-11-04 10:11:09 -06:00
|
|
|
ret = i915_gem_object_pin(obj, 0, true);
|
2010-10-14 08:03:58 -06:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
ret = i915_gem_object_set_to_gtt_domain(obj, true);
|
|
|
|
if (ret)
|
|
|
|
goto out_unpin;
|
|
|
|
|
|
|
|
ret = i915_gem_object_put_fence(obj);
|
2010-10-14 08:03:58 -06:00
|
|
|
if (ret)
|
|
|
|
goto out_unpin;
|
|
|
|
|
|
|
|
ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
|
|
|
|
if (ret == -EFAULT)
|
|
|
|
ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
|
|
|
|
|
|
|
|
out_unpin:
|
|
|
|
i915_gem_object_unpin(obj);
|
2009-03-09 14:42:30 -06:00
|
|
|
} else {
|
2010-10-14 08:03:58 -06:00
|
|
|
ret = i915_gem_object_set_to_cpu_domain(obj, 1);
|
|
|
|
if (ret)
|
2010-10-28 06:45:36 -06:00
|
|
|
goto out;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-14 08:03:58 -06:00
|
|
|
ret = -EFAULT;
|
|
|
|
if (!i915_gem_object_needs_bit17_swizzle(obj))
|
|
|
|
ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
|
|
|
|
if (ret == -EFAULT)
|
|
|
|
ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-26 13:23:38 -06:00
|
|
|
out:
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2010-10-14 08:03:58 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-11-10 11:53:25 -07:00
|
|
|
* Called when user space prepares to use an object with the CPU, either
|
|
|
|
* through the mmap ioctl's mapping or a GTT mapping.
|
2008-07-30 13:06:12 -06:00
|
|
|
*/
|
|
|
|
int
|
|
|
|
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_set_domain *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2008-11-10 11:53:25 -07:00
|
|
|
uint32_t read_domains = args->read_domains;
|
|
|
|
uint32_t write_domain = args->write_domain;
|
2008-07-30 13:06:12 -06:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(dev->driver->driver_features & DRIVER_GEM))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2008-11-10 11:53:25 -07:00
|
|
|
/* Only handle setting domains to types used by the CPU. */
|
2009-06-06 02:46:02 -06:00
|
|
|
if (write_domain & I915_GEM_GPU_DOMAINS)
|
2008-11-10 11:53:25 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2009-06-06 02:46:02 -06:00
|
|
|
if (read_domains & I915_GEM_GPU_DOMAINS)
|
2008-11-10 11:53:25 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Having something in the write domain implies it's in the read
|
|
|
|
* domain, and only that read domain. Enforce that in the request.
|
|
|
|
*/
|
|
|
|
if (write_domain != 0 && read_domains != write_domain)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2010-09-25 04:22:51 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
2010-09-25 04:22:51 -06:00
|
|
|
return ret;
|
2010-10-17 02:45:41 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2010-09-25 04:22:51 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2008-11-10 11:53:25 -07:00
|
|
|
if (read_domains & I915_GEM_DOMAIN_GTT) {
|
|
|
|
ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
|
2008-11-26 14:58:13 -07:00
|
|
|
|
|
|
|
/* Silently promote "you're not bound, there was nothing to do"
|
|
|
|
* to success, since the client was just asking us to
|
|
|
|
* make sure everything was done.
|
|
|
|
*/
|
|
|
|
if (ret == -EINVAL)
|
|
|
|
ret = 0;
|
2008-11-10 11:53:25 -07:00
|
|
|
} else {
|
2008-11-14 14:35:19 -07:00
|
|
|
ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
|
2008-11-10 11:53:25 -07:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2008-07-30 13:06:12 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Called when user space has done writes to this buffer
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_sw_finish *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2008-07-30 13:06:12 -06:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (!(dev->driver->driver_features & DRIVER_GEM))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2010-09-25 04:22:51 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
2010-09-25 04:22:51 -06:00
|
|
|
return ret;
|
2010-10-17 02:45:41 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Pinned buffers may be scanout, so flush the cache */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->pin_count)
|
2008-11-14 14:35:19 -07:00
|
|
|
i915_gem_object_flush_cpu_write_domain(obj);
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2008-07-30 13:06:12 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Maps the contents of an object, returning the address it is mapped
|
|
|
|
* into.
|
|
|
|
*
|
|
|
|
* While the mapping holds a reference on the contents of the object, it doesn't
|
|
|
|
* imply a ref on the object itself.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-10-27 10:37:08 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-07-30 13:06:12 -06:00
|
|
|
struct drm_i915_gem_mmap *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
|
|
|
unsigned long addr;
|
|
|
|
|
|
|
|
if (!(dev->driver->driver_features & DRIVER_GEM))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = drm_gem_object_lookup(dev, file, args->handle);
|
2008-07-30 13:06:12 -06:00
|
|
|
if (obj == NULL)
|
2010-08-04 07:19:46 -06:00
|
|
|
return -ENOENT;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-27 10:37:08 -06:00
|
|
|
if (obj->size > dev_priv->mm.gtt_mappable_end) {
|
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
|
|
|
return -E2BIG;
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
down_write(¤t->mm->mmap_sem);
|
|
|
|
addr = do_mmap(obj->filp, 0, args->size,
|
|
|
|
PROT_READ | PROT_WRITE, MAP_SHARED,
|
|
|
|
args->offset);
|
|
|
|
up_write(¤t->mm->mmap_sem);
|
2010-02-08 22:49:12 -07:00
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
2008-07-30 13:06:12 -06:00
|
|
|
if (IS_ERR((void *)addr))
|
|
|
|
return addr;
|
|
|
|
|
|
|
|
args->addr_ptr = (uint64_t) addr;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-11-12 11:03:55 -07:00
|
|
|
/**
|
|
|
|
* i915_gem_fault - fault a page into the GTT
|
|
|
|
* vma: VMA in question
|
|
|
|
* vmf: fault info
|
|
|
|
*
|
|
|
|
* The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
|
|
|
|
* from userspace. The fault handler takes care of binding the object to
|
|
|
|
* the GTT (if needed), allocating and programming a fence register (again,
|
|
|
|
* only if needed based on whether the old reg is still valid or the object
|
|
|
|
* is tiled) and inserting a new PTE into the faulting process.
|
|
|
|
*
|
|
|
|
* Note that the faulting process may involve evicting existing objects
|
|
|
|
* from the GTT and/or fence registers to make room. So performance may
|
|
|
|
* suffer if the GTT working set is large or there are few fence registers
|
|
|
|
* left.
|
|
|
|
*/
|
|
|
|
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
|
|
|
|
struct drm_device *dev = obj->base.dev;
|
2010-08-07 14:45:03 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2008-11-12 11:03:55 -07:00
|
|
|
pgoff_t page_offset;
|
|
|
|
unsigned long pfn;
|
|
|
|
int ret = 0;
|
2009-01-26 18:10:45 -07:00
|
|
|
bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
|
2008-11-12 11:03:55 -07:00
|
|
|
|
|
|
|
/* We don't use vmf->pgoff since that has the fake offset */
|
|
|
|
page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
|
|
|
|
PAGE_SHIFT;
|
|
|
|
|
2011-02-07 06:09:31 -07:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
2010-09-24 14:15:47 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_object_fault(obj, page_offset, true, write);
|
|
|
|
|
2011-02-07 06:09:31 -07:00
|
|
|
/* Now bind it into the GTT if needed */
|
2010-11-12 06:42:53 -07:00
|
|
|
if (!obj->map_and_fenceable) {
|
|
|
|
ret = i915_gem_object_unbind(obj);
|
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
2010-09-24 14:15:47 -06:00
|
|
|
}
|
2010-11-08 12:18:58 -07:00
|
|
|
if (!obj->gtt_space) {
|
2010-11-04 10:11:09 -06:00
|
|
|
ret = i915_gem_object_bind_to_gtt(obj, 0, true);
|
2009-09-22 17:43:56 -06:00
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2011-06-14 17:43:09 -06:00
|
|
|
ret = i915_gem_object_set_to_gtt_domain(obj, write);
|
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
|
|
|
}
|
2010-10-28 07:44:08 -06:00
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
if (obj->tiling_mode == I915_TILING_NONE)
|
|
|
|
ret = i915_gem_object_put_fence(obj);
|
|
|
|
else
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_get_fence(obj, NULL);
|
2010-11-10 09:40:20 -07:00
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (i915_gem_object_is_inactive(obj))
|
|
|
|
list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
|
2010-08-07 14:45:03 -06:00
|
|
|
|
2010-11-24 05:23:44 -07:00
|
|
|
obj->fault_mappable = true;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
|
2008-11-12 11:03:55 -07:00
|
|
|
page_offset;
|
|
|
|
|
|
|
|
/* Finally, remap it using the new GTT offset */
|
|
|
|
ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
|
2009-09-22 17:43:56 -06:00
|
|
|
unlock:
|
2008-11-12 11:03:55 -07:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2011-02-07 06:09:31 -07:00
|
|
|
out:
|
2008-11-12 11:03:55 -07:00
|
|
|
switch (ret) {
|
2011-02-07 06:09:31 -07:00
|
|
|
case -EIO:
|
2010-11-07 02:18:22 -07:00
|
|
|
case -EAGAIN:
|
2011-02-07 06:09:31 -07:00
|
|
|
/* Give the error handler a chance to run and move the
|
|
|
|
* objects off the GPU active list. Next time we service the
|
|
|
|
* fault, we should be able to transition the page into the
|
|
|
|
* GTT without touching the GPU (and so avoid further
|
|
|
|
* EIO/EGAIN). If the GPU is wedged, then there is no issue
|
|
|
|
* with coherency, just lost writes.
|
|
|
|
*/
|
2010-11-07 02:18:22 -07:00
|
|
|
set_need_resched();
|
2009-09-22 17:43:56 -06:00
|
|
|
case 0:
|
|
|
|
case -ERESTARTSYS:
|
2011-02-11 13:31:19 -07:00
|
|
|
case -EINTR:
|
2009-09-22 17:43:56 -06:00
|
|
|
return VM_FAULT_NOPAGE;
|
2008-11-12 11:03:55 -07:00
|
|
|
case -ENOMEM:
|
|
|
|
return VM_FAULT_OOM;
|
|
|
|
default:
|
2009-09-22 17:43:56 -06:00
|
|
|
return VM_FAULT_SIGBUS;
|
2008-11-12 11:03:55 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-10 01:18:50 -06:00
|
|
|
/**
|
|
|
|
* i915_gem_release_mmap - remove physical page mappings
|
|
|
|
* @obj: obj in question
|
|
|
|
*
|
tree-wide: fix assorted typos all over the place
That is "success", "unknown", "through", "performance", "[re|un]mapping"
, "access", "default", "reasonable", "[con]currently", "temperature"
, "channel", "[un]used", "application", "example","hierarchy", "therefore"
, "[over|under]flow", "contiguous", "threshold", "enough" and others.
Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2009-11-14 08:09:05 -07:00
|
|
|
* Preserve the reservation of the mmapping with the DRM core code, but
|
2009-07-10 01:18:50 -06:00
|
|
|
* relinquish ownership of the pages back to the system.
|
|
|
|
*
|
|
|
|
* It is vital that we remove the page mapping if we have mapped a tiled
|
|
|
|
* object through the GTT and then lose the fence register due to
|
|
|
|
* resource pressure. Similarly if the object has been moved out of the
|
|
|
|
* aperture, than pages mapped into userspace must be revoked. Removing the
|
|
|
|
* mapping will then trigger a page fault on the next user access, allowing
|
|
|
|
* fixup by i915_gem_fault().
|
|
|
|
*/
|
2009-07-10 14:02:26 -06:00
|
|
|
void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_release_mmap(struct drm_i915_gem_object *obj)
|
2009-07-10 01:18:50 -06:00
|
|
|
{
|
2010-11-24 05:23:44 -07:00
|
|
|
if (!obj->fault_mappable)
|
|
|
|
return;
|
2009-07-10 01:18:50 -06:00
|
|
|
|
2011-03-20 15:09:12 -06:00
|
|
|
if (obj->base.dev->dev_mapping)
|
|
|
|
unmap_mapping_range(obj->base.dev->dev_mapping,
|
|
|
|
(loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
|
|
|
|
obj->base.size, 1);
|
2010-10-01 14:05:20 -06:00
|
|
|
|
2010-11-24 05:23:44 -07:00
|
|
|
obj->fault_mappable = false;
|
2009-07-10 01:18:50 -06:00
|
|
|
}
|
|
|
|
|
2010-11-09 04:47:32 -07:00
|
|
|
static uint32_t
|
2011-07-18 14:11:49 -06:00
|
|
|
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
|
2010-11-09 04:47:32 -07:00
|
|
|
{
|
2011-07-18 14:11:49 -06:00
|
|
|
uint32_t gtt_size;
|
2010-11-09 04:47:32 -07:00
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4 ||
|
2011-07-18 14:11:49 -06:00
|
|
|
tiling_mode == I915_TILING_NONE)
|
|
|
|
return size;
|
2010-11-09 04:47:32 -07:00
|
|
|
|
|
|
|
/* Previous chips need a power-of-two fence region when tiling */
|
|
|
|
if (INTEL_INFO(dev)->gen == 3)
|
2011-07-18 14:11:49 -06:00
|
|
|
gtt_size = 1024*1024;
|
2010-11-09 04:47:32 -07:00
|
|
|
else
|
2011-07-18 14:11:49 -06:00
|
|
|
gtt_size = 512*1024;
|
2010-11-09 04:47:32 -07:00
|
|
|
|
2011-07-18 14:11:49 -06:00
|
|
|
while (gtt_size < size)
|
|
|
|
gtt_size <<= 1;
|
2010-11-09 04:47:32 -07:00
|
|
|
|
2011-07-18 14:11:49 -06:00
|
|
|
return gtt_size;
|
2010-11-09 04:47:32 -07:00
|
|
|
}
|
|
|
|
|
2008-11-12 11:03:55 -07:00
|
|
|
/**
|
|
|
|
* i915_gem_get_gtt_alignment - return required GTT alignment for an object
|
|
|
|
* @obj: object to check
|
|
|
|
*
|
|
|
|
* Return the required GTT alignment for an object, taking into account
|
2010-11-14 14:32:36 -07:00
|
|
|
* potential fence register mapping.
|
2008-11-12 11:03:55 -07:00
|
|
|
*/
|
|
|
|
static uint32_t
|
2011-07-18 14:11:49 -06:00
|
|
|
i915_gem_get_gtt_alignment(struct drm_device *dev,
|
|
|
|
uint32_t size,
|
|
|
|
int tiling_mode)
|
2008-11-12 11:03:55 -07:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Minimum alignment is 4k (GTT page size), but might be greater
|
|
|
|
* if a fence register is needed for the object.
|
|
|
|
*/
|
2010-09-24 14:15:47 -06:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4 ||
|
2011-07-18 14:11:49 -06:00
|
|
|
tiling_mode == I915_TILING_NONE)
|
2008-11-12 11:03:55 -07:00
|
|
|
return 4096;
|
|
|
|
|
2010-09-24 14:15:47 -06:00
|
|
|
/*
|
|
|
|
* Previous chips need to be aligned to the size of the smallest
|
|
|
|
* fence register that can contain the object.
|
|
|
|
*/
|
2011-07-18 14:11:49 -06:00
|
|
|
return i915_gem_get_gtt_size(dev, size, tiling_mode);
|
2010-09-24 14:15:47 -06:00
|
|
|
}
|
|
|
|
|
2010-11-14 14:32:36 -07:00
|
|
|
/**
|
|
|
|
* i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
|
|
|
|
* unfenced object
|
2011-07-18 14:11:49 -06:00
|
|
|
* @dev: the device
|
|
|
|
* @size: size of the object
|
|
|
|
* @tiling_mode: tiling mode of the object
|
2010-11-14 14:32:36 -07:00
|
|
|
*
|
|
|
|
* Return the required GTT alignment for an object, only taking into account
|
|
|
|
* unfenced tiled surface requirements.
|
|
|
|
*/
|
2011-03-07 03:42:03 -07:00
|
|
|
uint32_t
|
2011-07-18 14:11:49 -06:00
|
|
|
i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
|
|
|
|
uint32_t size,
|
|
|
|
int tiling_mode)
|
2010-11-14 14:32:36 -07:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Minimum alignment is 4k (GTT page size) for sane hw.
|
|
|
|
*/
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
|
2011-07-18 14:11:49 -06:00
|
|
|
tiling_mode == I915_TILING_NONE)
|
2010-11-14 14:32:36 -07:00
|
|
|
return 4096;
|
|
|
|
|
2011-07-18 14:11:49 -06:00
|
|
|
/* Previous hardware however needs to be aligned to a power-of-two
|
|
|
|
* tile height. The simplest method for determining this is to reuse
|
|
|
|
* the power-of-tile object size.
|
2010-11-14 14:32:36 -07:00
|
|
|
*/
|
2011-07-18 14:11:49 -06:00
|
|
|
return i915_gem_get_gtt_size(dev, size, tiling_mode);
|
2010-11-14 14:32:36 -07:00
|
|
|
}
|
|
|
|
|
2008-11-12 11:03:55 -07:00
|
|
|
int
|
2011-02-06 19:16:14 -07:00
|
|
|
i915_gem_mmap_gtt(struct drm_file *file,
|
|
|
|
struct drm_device *dev,
|
|
|
|
uint32_t handle,
|
|
|
|
uint64_t *offset)
|
2008-11-12 11:03:55 -07:00
|
|
|
{
|
2010-10-27 10:37:08 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2008-11-12 11:03:55 -07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(dev->driver->driver_features & DRIVER_GEM))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2010-09-25 04:22:51 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
2010-09-25 04:22:51 -06:00
|
|
|
return ret;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
|
|
|
}
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
|
2010-10-27 10:37:08 -06:00
|
|
|
ret = -E2BIG;
|
2011-11-01 00:16:21 -06:00
|
|
|
goto out;
|
2010-10-27 10:37:08 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->madv != I915_MADV_WILLNEED) {
|
2009-09-22 11:46:17 -06:00
|
|
|
DRM_ERROR("Attempting to mmap a purgeable buffer\n");
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
2009-09-22 11:46:17 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (!obj->base.map_list.map) {
|
2011-08-10 07:09:08 -06:00
|
|
|
ret = drm_gem_create_mmap_offset(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
2008-11-12 11:03:55 -07:00
|
|
|
}
|
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
*offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-10-17 02:45:41 -06:00
|
|
|
out:
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2008-11-12 11:03:55 -07:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-10-17 02:45:41 -06:00
|
|
|
return ret;
|
2008-11-12 11:03:55 -07:00
|
|
|
}
|
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
/**
|
|
|
|
* i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
|
|
|
|
* @dev: DRM device
|
|
|
|
* @data: GTT mapping ioctl data
|
|
|
|
* @file: GEM object info
|
|
|
|
*
|
|
|
|
* Simply returns the fake offset to userspace so it can mmap it.
|
|
|
|
* The mmap call will end up in drm_gem_mmap(), which will set things
|
|
|
|
* up so we can get faults in the handler above.
|
|
|
|
*
|
|
|
|
* The fault handler will take care of binding the object into the GTT
|
|
|
|
* (since it may have been evicted to make room for something), allocating
|
|
|
|
* a fence register, and mapping the appropriate aperture address into
|
|
|
|
* userspace.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_mmap_gtt *args = data;
|
|
|
|
|
|
|
|
if (!(dev->driver->driver_features & DRIVER_GEM))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-10-28 06:45:36 -06:00
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
|
2010-10-28 06:45:36 -06:00
|
|
|
gfp_t gfpmask)
|
|
|
|
{
|
|
|
|
int page_count, i;
|
|
|
|
struct address_space *mapping;
|
|
|
|
struct inode *inode;
|
|
|
|
struct page *page;
|
|
|
|
|
|
|
|
/* Get the list of pages out of our struct file. They'll be pinned
|
|
|
|
* at this point until we release them.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
page_count = obj->base.size / PAGE_SIZE;
|
|
|
|
BUG_ON(obj->pages != NULL);
|
|
|
|
obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
|
|
|
|
if (obj->pages == NULL)
|
2010-10-28 06:45:36 -06:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
inode = obj->base.filp->f_path.dentry->d_inode;
|
2010-10-28 06:45:36 -06:00
|
|
|
mapping = inode->i_mapping;
|
2011-06-27 17:18:18 -06:00
|
|
|
gfpmask |= mapping_gfp_mask(mapping);
|
|
|
|
|
2010-10-28 06:45:36 -06:00
|
|
|
for (i = 0; i < page_count; i++) {
|
2011-06-27 17:18:18 -06:00
|
|
|
page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
|
2010-10-28 06:45:36 -06:00
|
|
|
if (IS_ERR(page))
|
|
|
|
goto err_pages;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->pages[i] = page;
|
2010-10-28 06:45:36 -06:00
|
|
|
}
|
|
|
|
|
2011-09-12 13:30:02 -06:00
|
|
|
if (i915_gem_object_needs_bit17_swizzle(obj))
|
2010-10-28 06:45:36 -06:00
|
|
|
i915_gem_object_do_bit_17_swizzle(obj);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_pages:
|
|
|
|
while (i--)
|
2010-11-08 12:18:58 -07:00
|
|
|
page_cache_release(obj->pages[i]);
|
2010-10-28 06:45:36 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_free_large(obj->pages);
|
|
|
|
obj->pages = NULL;
|
2010-10-28 06:45:36 -06:00
|
|
|
return PTR_ERR(page);
|
|
|
|
}
|
|
|
|
|
2010-09-27 08:51:07 -06:00
|
|
|
static void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
int page_count = obj->base.size / PAGE_SIZE;
|
2008-07-30 13:06:12 -06:00
|
|
|
int i;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON(obj->madv == __I915_MADV_PURGED);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-09-12 13:30:02 -06:00
|
|
|
if (i915_gem_object_needs_bit17_swizzle(obj))
|
2009-03-12 17:56:27 -06:00
|
|
|
i915_gem_object_save_bit_17_swizzle(obj);
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->madv == I915_MADV_DONTNEED)
|
|
|
|
obj->dirty = 0;
|
2009-09-14 09:50:29 -06:00
|
|
|
|
|
|
|
for (i = 0; i < page_count; i++) {
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->dirty)
|
|
|
|
set_page_dirty(obj->pages[i]);
|
2009-09-14 09:50:29 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->madv == I915_MADV_WILLNEED)
|
|
|
|
mark_page_accessed(obj->pages[i]);
|
2009-09-14 09:50:29 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
page_cache_release(obj->pages[i]);
|
2009-09-14 09:50:29 -06:00
|
|
|
}
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->dirty = 0;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_free_large(obj->pages);
|
|
|
|
obj->pages = NULL;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-11-25 11:00:26 -07:00
|
|
|
void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
|
2010-12-04 04:30:53 -07:00
|
|
|
struct intel_ring_buffer *ring,
|
|
|
|
u32 seqno)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2010-10-19 03:36:51 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-02-11 14:16:02 -07:00
|
|
|
|
2010-05-20 19:08:56 -06:00
|
|
|
BUG_ON(ring == NULL);
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->ring = ring;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
/* Add a reference if we're newly entering the active list. */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (!obj->active) {
|
|
|
|
drm_gem_object_reference(&obj->base);
|
|
|
|
obj->active = 1;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
drm/i915: allow lazy emitting of requests
Sometimes (like when flushing in preparation of batchbuffer execution)
we know that we'll emit a request but haven't yet done so. Allow this
case by simply taking the next seqno by default. Ensure that a request
is eventually emitted before waiting for an request by issuing it
in i915_wait_request iff this is not yet done.
Also replace one open-coded version of i915_gem_object_wait_rendering,
to prevent future code-diversion.
Chris Wilson asked me to explain and clarify what this patch does and why.
Here it goes:
Old way of moving objects onto the active list and associating them with a
reques:
1. i915_add_request + store the returned seqno somewhere
2. i915_gem_object_move_to_active (with the stored seqno as parameter)
For the current users, this is all fine. But I'd like to associate objects
(and fence regs) with the batchbuffer request deep down in the execbuf
call-chain. I thought about three ways of implementing this.
a) Don't care, just emit request when we need a new seqno. When heavily
pipelining fence reg changes, this would have caused tons of superflous
request (and corresponding irqs).
b) Thread all changed fences, objects, whatever through the execbuf-maze,
so that when we emit a request, we can store the new seqno at all the right
places.
c) Kill that seqno-threading-around business by simply storing the next
seqno, i.e. allow 2. to be done before 1. in the above sequence.
I've decided to implement c) (in this patch). The following patches are
just fall-out that resulted from this small conceptual change.
* We can handle the flushing list processing where we actually emit a flush
(i915_gem_flush and i915_retire_commands) instead of in i915_add_request.
The code makes IMHO more sense this way (and i915_add_request looses the
flush_domains parameter, obviously).
* We can avoid emitting unnecessary requests. IMHO there's no point in
emitting more than one request per batchbuffer (with or without an
corresponding irq).
* By enforcing 2. before 1. ordering in the above sequence the seqno
argument of i915_gem_object_move_to_active is redundant and can be
dropped.
v2: Now i915_wait_request issues request if it is not yet emitted.
Also introduce i915_gem_next_request_seqno(dev) just in case we ever
need to do some prep work before using a new seqno.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[ickle: Keep i915_gem_object_set_to_display_plane() uninterruptible.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-02-11 14:13:59 -07:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/* Move from whatever list we were on to the tail of execution. */
|
2010-11-08 12:18:58 -07:00
|
|
|
list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
|
|
|
|
list_move_tail(&obj->ring_list, &ring->active_list);
|
2010-11-12 06:53:37 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->last_rendering_seqno = seqno;
|
2010-11-12 06:53:37 -07:00
|
|
|
if (obj->fenced_gpu_access) {
|
|
|
|
struct drm_i915_fence_reg *reg;
|
|
|
|
|
|
|
|
BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
|
|
|
|
|
|
|
|
obj->last_fenced_seqno = seqno;
|
|
|
|
obj->last_fenced_ring = ring;
|
|
|
|
|
|
|
|
reg = &dev_priv->fence_regs[obj->fence_reg];
|
|
|
|
list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
|
|
|
|
{
|
|
|
|
list_del_init(&obj->ring_list);
|
|
|
|
obj->last_rendering_seqno = 0;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2008-11-06 17:00:31 -07:00
|
|
|
static void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
|
2008-11-06 17:00:31 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2008-11-06 17:00:31 -07:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON(!obj->active);
|
|
|
|
list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
|
2010-11-12 06:53:37 -07:00
|
|
|
|
|
|
|
i915_gem_object_move_off_active(obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = obj->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (obj->pin_count != 0)
|
|
|
|
list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
|
|
|
|
else
|
|
|
|
list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
|
|
|
|
|
|
|
|
BUG_ON(!list_empty(&obj->gpu_write_list));
|
|
|
|
BUG_ON(!obj->active);
|
|
|
|
obj->ring = NULL;
|
|
|
|
|
|
|
|
i915_gem_object_move_off_active(obj);
|
|
|
|
obj->fenced_gpu_access = false;
|
|
|
|
|
|
|
|
obj->active = 0;
|
2010-12-02 02:42:56 -07:00
|
|
|
obj->pending_gpu_write = false;
|
2010-11-12 06:53:37 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
|
|
|
|
|
|
WARN_ON(i915_verify_lists(dev));
|
2008-11-06 17:00:31 -07:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2009-09-20 16:03:54 -06:00
|
|
|
/* Immediately discard the backing storage */
|
|
|
|
static void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_truncate(struct drm_i915_gem_object *obj)
|
2009-09-20 16:03:54 -06:00
|
|
|
{
|
2009-09-22 07:24:13 -06:00
|
|
|
struct inode *inode;
|
2009-09-20 16:03:54 -06:00
|
|
|
|
2010-08-07 04:01:30 -06:00
|
|
|
/* Our goal here is to return as much of the memory as
|
|
|
|
* is possible back to the system as we are called from OOM.
|
|
|
|
* To do this we must instruct the shmfs to drop all of its
|
2011-06-27 17:18:19 -06:00
|
|
|
* backing pages, *now*.
|
2010-08-07 04:01:30 -06:00
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
inode = obj->base.filp->f_path.dentry->d_inode;
|
2011-06-27 17:18:19 -06:00
|
|
|
shmem_truncate_range(inode, 0, (loff_t)-1);
|
2009-09-22 07:24:13 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->madv = __I915_MADV_PURGED;
|
2009-09-20 16:03:54 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
|
2009-09-20 16:03:54 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
return obj->madv == I915_MADV_DONTNEED;
|
2009-09-20 16:03:54 -06:00
|
|
|
}
|
|
|
|
|
2010-02-19 03:51:59 -07:00
|
|
|
static void
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
|
|
|
|
uint32_t flush_domains)
|
2010-02-19 03:51:59 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj, *next;
|
2010-02-19 03:51:59 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
list_for_each_entry_safe(obj, next,
|
2010-10-24 05:38:05 -06:00
|
|
|
&ring->gpu_write_list,
|
2010-02-19 03:51:59 -07:00
|
|
|
gpu_write_list) {
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.write_domain & flush_domains) {
|
|
|
|
uint32_t old_write_domain = obj->base.write_domain;
|
2010-02-19 03:51:59 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.write_domain = 0;
|
|
|
|
list_del_init(&obj->gpu_write_list);
|
2010-12-04 04:30:53 -07:00
|
|
|
i915_gem_object_move_to_active(obj, ring,
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_gem_next_request_seqno(ring));
|
2010-02-19 03:51:59 -07:00
|
|
|
|
|
|
|
trace_i915_gem_object_change_domain(obj,
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains,
|
2010-02-19 03:51:59 -07:00
|
|
|
old_write_domain);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-05-20 19:08:55 -06:00
|
|
|
|
2010-10-27 09:11:02 -06:00
|
|
|
int
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_add_request(struct intel_ring_buffer *ring,
|
2010-09-24 09:02:42 -06:00
|
|
|
struct drm_file *file,
|
2011-02-03 04:57:46 -07:00
|
|
|
struct drm_i915_gem_request *request)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2011-02-03 04:57:46 -07:00
|
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
2008-07-30 13:06:12 -06:00
|
|
|
uint32_t seqno;
|
|
|
|
int was_empty;
|
2010-10-27 09:11:02 -06:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
BUG_ON(request == NULL);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-27 09:11:02 -06:00
|
|
|
ret = ring->add_request(ring, &seqno);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_request_add(ring, seqno);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
request->seqno = seqno;
|
2010-05-20 19:08:56 -06:00
|
|
|
request->ring = ring;
|
2008-07-30 13:06:12 -06:00
|
|
|
request->emitted_jiffies = jiffies;
|
2010-05-20 19:08:56 -06:00
|
|
|
was_empty = list_empty(&ring->request_list);
|
|
|
|
list_add_tail(&request->list, &ring->request_list);
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
if (file) {
|
|
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
|
|
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_lock(&file_priv->mm.lock);
|
2010-09-24 09:02:42 -06:00
|
|
|
request->file_priv = file_priv;
|
2009-06-03 01:27:35 -06:00
|
|
|
list_add_tail(&request->client_list,
|
2010-09-24 09:02:42 -06:00
|
|
|
&file_priv->mm.request_list);
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_unlock(&file_priv->mm.lock);
|
2009-06-03 01:27:35 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
ring->outstanding_lazy_request = false;
|
|
|
|
|
2009-09-14 15:48:44 -06:00
|
|
|
if (!dev_priv->mm.suspended) {
|
2011-06-29 11:26:42 -06:00
|
|
|
if (i915_enable_hangcheck) {
|
|
|
|
mod_timer(&dev_priv->hangcheck_timer,
|
|
|
|
jiffies +
|
|
|
|
msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
|
|
|
|
}
|
2009-09-14 15:48:44 -06:00
|
|
|
if (was_empty)
|
2010-09-13 16:44:34 -06:00
|
|
|
queue_delayed_work(dev_priv->wq,
|
|
|
|
&dev_priv->mm.retire_work, HZ);
|
2009-09-14 15:48:44 -06:00
|
|
|
}
|
2010-10-27 09:11:02 -06:00
|
|
|
return 0;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-09-24 09:02:42 -06:00
|
|
|
static inline void
|
|
|
|
i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-09-26 04:03:27 -06:00
|
|
|
struct drm_i915_file_private *file_priv = request->file_priv;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-26 04:03:27 -06:00
|
|
|
if (!file_priv)
|
|
|
|
return;
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_lock(&file_priv->mm.lock);
|
drm/i915: Prevent racy removal of request from client list
When i915_gem_retire_requests_ring calls i915_gem_request_remove_from_client,
the client_list for that request may already be removed in i915_gem_release.
So we may call twice list_del(&request->client_list), resulting in an
oops like this report:
[126167.230394] BUG: unable to handle kernel paging request at 00100104
[126167.230699] IP: [<f8c2ce44>] i915_gem_retire_requests_ring+0xd4/0x240 [i915]
[126167.231042] *pdpt = 00000000314c1001 *pde = 0000000000000000
[126167.231314] Oops: 0002 [#1] SMP
[126167.231471] last sysfs file: /sys/devices/LNXSYSTM:00/device:00/PNP0C0A:00/power_supply/BAT1/current_now
[126167.231901] Modules linked in: snd_seq_dummy nls_utf8 isofs btrfs zlib_deflate libcrc32c ufs qnx4 hfsplus hfs minix ntfs vfat msdos fat jfs xfs exportfs reiserfs cryptd aes_i586 aes_generic binfmt_misc vboxnetadp vboxnetflt vboxdrv parport_pc ppdev snd_hda_codec_hdmi snd_hda_codec_conexant snd_hda_intel snd_hda_codec snd_hwdep arc4 snd_pcm snd_seq_midi snd_rawmidi snd_seq_midi_event snd_seq uvcvideo videodev snd_timer snd_seq_device joydev iwlagn iwlcore mac80211 snd cfg80211 soundcore i915 drm_kms_helper snd_page_alloc psmouse drm serio_raw i2c_algo_bit video lp parport usbhid hid sky2 sdhci_pci ahci sdhci libahci
[126167.232018]
[126167.232018] Pid: 1101, comm: Xorg Not tainted 2.6.38-6-generic-pae #34-Ubuntu Gateway MC7833U /
[126167.232018] EIP: 0060:[<f8c2ce44>] EFLAGS: 00213246 CPU: 0
[126167.232018] EIP is at i915_gem_retire_requests_ring+0xd4/0x240 [i915]
[126167.232018] EAX: 00200200 EBX: f1ac25b0 ECX: 00000040 EDX: 00100100
[126167.232018] ESI: f1a2801c EDI: e87fc060 EBP: ef4d7dd8 ESP: ef4d7db0
[126167.232018] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
[126167.232018] Process Xorg (pid: 1101, ti=ef4d6000 task=f1ba6500 task.ti=ef4d6000)
[126167.232018] Stack:
[126167.232018] f1a28000 f1a2809c f1a28094 0058bd97 f1aa2400 f1a2801c 0058bd7b 0058bd85
[126167.232018] f1a2801c f1a28000 ef4d7e38 f8c2e995 ef4d7e30 ef4d7e60 c14d1ebc f6b3a040
[126167.232018] f1522cc0 000000db 00000000 f1ba6500 ffffffa1 00000000 00000001 f1a29214
[126167.232018] Call Trace:
Unfortunately the call trace reported was cut, but looking at debug
symbols the crash is at __list_del, when probably list_del is called
twice on the same request->client_list, as the dereferenced value is
LIST_POISON1 + 4, and by looking more at the debug symbols before
list_del call it should have being called by
i915_gem_request_remove_from_client
And as I can see in the code, it seems we indeed have the possibility
to remove a request->client_list twice, which would cause the above,
because we do list_del(&request->client_list) on both
i915_gem_request_remove_from_client and i915_gem_release
As Chris Wilson pointed out, it's indeed the case:
"(...) I had thought that the actual insertion/deletion was serialised
under the struct mutex and the intention of the spinlock was to protect
the unlocked list traversal during throttling. However, I missed that
i915_gem_release() is also called without struct mutex and so we do need
the double check for i915_gem_request_remove_from_client()."
This change does the required check to avoid the duplicate remove of
request->client_list.
Bugzilla: http://bugs.launchpad.net/bugs/733780
Cc: stable@kernel.org # 2.6.38
Signed-off-by: Herton Ronaldo Krzesinski <herton.krzesinski@canonical.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-17 07:45:12 -06:00
|
|
|
if (request->file_priv) {
|
|
|
|
list_del(&request->client_list);
|
|
|
|
request->file_priv = NULL;
|
|
|
|
}
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_unlock(&file_priv->mm.lock);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-09-22 03:31:52 -06:00
|
|
|
static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_ring_buffer *ring)
|
2010-09-19 05:21:28 -06:00
|
|
|
{
|
2010-09-22 03:31:52 -06:00
|
|
|
while (!list_empty(&ring->request_list)) {
|
|
|
|
struct drm_i915_gem_request *request;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-22 03:31:52 -06:00
|
|
|
request = list_first_entry(&ring->request_list,
|
|
|
|
struct drm_i915_gem_request,
|
|
|
|
list);
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-09-22 03:31:52 -06:00
|
|
|
list_del(&request->list);
|
2010-09-24 09:02:42 -06:00
|
|
|
i915_gem_request_remove_from_client(request);
|
2010-09-22 03:31:52 -06:00
|
|
|
kfree(request);
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-22 03:31:52 -06:00
|
|
|
while (!list_empty(&ring->active_list)) {
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-19 05:21:28 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = list_first_entry(&ring->active_list,
|
|
|
|
struct drm_i915_gem_object,
|
|
|
|
ring_list);
|
2010-09-19 05:21:28 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.write_domain = 0;
|
|
|
|
list_del_init(&obj->gpu_write_list);
|
|
|
|
i915_gem_object_move_to_inactive(obj);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-22 04:50:11 -07:00
|
|
|
static void i915_gem_reset_fences(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int i;
|
|
|
|
|
2011-10-09 13:52:02 -06:00
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++) {
|
2010-11-22 04:50:11 -07:00
|
|
|
struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
|
2010-11-27 10:38:29 -07:00
|
|
|
struct drm_i915_gem_object *obj = reg->obj;
|
|
|
|
|
|
|
|
if (!obj)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (obj->tiling_mode)
|
|
|
|
i915_gem_release_mmap(obj);
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
reg->obj->fence_reg = I915_FENCE_REG_NONE;
|
|
|
|
reg->obj->fenced_gpu_access = false;
|
|
|
|
reg->obj->last_fenced_seqno = 0;
|
|
|
|
reg->obj->last_fenced_ring = NULL;
|
|
|
|
i915_gem_clear_fence_reg(dev, reg);
|
2010-11-22 04:50:11 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-30 09:53:18 -06:00
|
|
|
void i915_gem_reset(struct drm_device *dev)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-09-19 05:31:36 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-12-04 04:30:53 -07:00
|
|
|
int i;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++)
|
|
|
|
i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
|
2010-09-22 03:31:52 -06:00
|
|
|
|
|
|
|
/* Remove anything from the flushing lists. The GPU cache is likely
|
|
|
|
* to be lost on reset along with the data, so simply move the
|
|
|
|
* lost bo to the inactive list.
|
|
|
|
*/
|
|
|
|
while (!list_empty(&dev_priv->mm.flushing_list)) {
|
2011-08-16 13:34:10 -06:00
|
|
|
obj = list_first_entry(&dev_priv->mm.flushing_list,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object,
|
|
|
|
mm_list);
|
2010-09-22 03:31:52 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.write_domain = 0;
|
|
|
|
list_del_init(&obj->gpu_write_list);
|
|
|
|
i915_gem_object_move_to_inactive(obj);
|
2010-09-22 03:31:52 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Move everything out of the GPU domains to ensure we do any
|
|
|
|
* necessary invalidation upon reuse.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
list_for_each_entry(obj,
|
2010-09-19 05:31:36 -06:00
|
|
|
&dev_priv->mm.inactive_list,
|
2010-10-19 03:36:51 -06:00
|
|
|
mm_list)
|
2010-09-19 05:31:36 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
|
2010-09-19 05:31:36 -06:00
|
|
|
}
|
2010-09-30 09:53:18 -06:00
|
|
|
|
|
|
|
/* The fence registers are invalidated so clear them out */
|
2010-11-22 04:50:11 -07:00
|
|
|
i915_gem_reset_fences(dev);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* This function clears the request list as sequence numbers are passed.
|
|
|
|
*/
|
2010-07-23 16:18:49 -06:00
|
|
|
static void
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
uint32_t seqno;
|
2010-12-04 04:30:53 -07:00
|
|
|
int i;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
if (list_empty(&ring->request_list))
|
2009-02-23 07:07:57 -07:00
|
|
|
return;
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
WARN_ON(i915_verify_lists(ring->dev));
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
seqno = ring->get_seqno(ring);
|
2010-12-04 04:30:53 -07:00
|
|
|
|
2011-01-21 03:07:18 -07:00
|
|
|
for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
|
2010-12-04 04:30:53 -07:00
|
|
|
if (seqno >= ring->sync_seqno[i])
|
|
|
|
ring->sync_seqno[i] = 0;
|
|
|
|
|
2010-05-20 19:08:56 -06:00
|
|
|
while (!list_empty(&ring->request_list)) {
|
2008-07-30 13:06:12 -06:00
|
|
|
struct drm_i915_gem_request *request;
|
|
|
|
|
2010-05-20 19:08:56 -06:00
|
|
|
request = list_first_entry(&ring->request_list,
|
2008-07-30 13:06:12 -06:00
|
|
|
struct drm_i915_gem_request,
|
|
|
|
list);
|
|
|
|
|
2010-09-22 03:31:52 -06:00
|
|
|
if (!i915_seqno_passed(seqno, request->seqno))
|
2010-09-17 18:38:04 -06:00
|
|
|
break;
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_request_retire(ring, request->seqno);
|
2010-09-17 18:38:04 -06:00
|
|
|
|
|
|
|
list_del(&request->list);
|
2010-09-24 09:02:42 -06:00
|
|
|
i915_gem_request_remove_from_client(request);
|
2010-09-17 18:38:04 -06:00
|
|
|
kfree(request);
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-17 18:38:04 -06:00
|
|
|
/* Move any buffers on the active list that are no longer referenced
|
|
|
|
* by the ringbuffer to the flushing/inactive lists as appropriate.
|
|
|
|
*/
|
|
|
|
while (!list_empty(&ring->active_list)) {
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-17 18:38:04 -06:00
|
|
|
|
2011-08-16 13:34:10 -06:00
|
|
|
obj = list_first_entry(&ring->active_list,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object,
|
|
|
|
ring_list);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
|
2008-07-30 13:06:12 -06:00
|
|
|
break;
|
2010-09-17 18:38:04 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.write_domain != 0)
|
2010-09-17 18:38:04 -06:00
|
|
|
i915_gem_object_move_to_flushing(obj);
|
|
|
|
else
|
|
|
|
i915_gem_object_move_to_inactive(obj);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
2009-09-23 22:26:06 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
if (unlikely(ring->trace_irq_seqno &&
|
|
|
|
i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
|
2010-12-04 04:30:53 -07:00
|
|
|
ring->irq_put(ring);
|
2011-02-03 04:57:46 -07:00
|
|
|
ring->trace_irq_seqno = 0;
|
2009-09-23 22:26:06 -06:00
|
|
|
}
|
2010-09-29 09:10:57 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
WARN_ON(i915_verify_lists(ring->dev));
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-07-23 16:18:49 -06:00
|
|
|
void
|
|
|
|
i915_gem_retire_requests(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-12-04 04:30:53 -07:00
|
|
|
int i;
|
2010-07-23 16:18:49 -06:00
|
|
|
|
2010-07-23 16:18:50 -06:00
|
|
|
if (!list_empty(&dev_priv->mm.deferred_free_list)) {
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj, *next;
|
2010-07-23 16:18:50 -06:00
|
|
|
|
|
|
|
/* We must be careful that during unbind() we do not
|
|
|
|
* accidentally infinitely recurse into retire requests.
|
|
|
|
* Currently:
|
|
|
|
* retire -> free -> unbind -> wait -> retire_ring
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
list_for_each_entry_safe(obj, next,
|
2010-07-23 16:18:50 -06:00
|
|
|
&dev_priv->mm.deferred_free_list,
|
2010-10-19 03:36:51 -06:00
|
|
|
mm_list)
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_free_object_tail(obj);
|
2010-07-23 16:18:50 -06:00
|
|
|
}
|
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++)
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_gem_retire_requests_ring(&dev_priv->ring[i]);
|
2010-07-23 16:18:49 -06:00
|
|
|
}
|
|
|
|
|
2010-08-20 16:25:16 -06:00
|
|
|
static void
|
2008-07-30 13:06:12 -06:00
|
|
|
i915_gem_retire_work_handler(struct work_struct *work)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv;
|
|
|
|
struct drm_device *dev;
|
2011-01-09 14:05:44 -07:00
|
|
|
bool idle;
|
|
|
|
int i;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
dev_priv = container_of(work, drm_i915_private_t,
|
|
|
|
mm.retire_work.work);
|
|
|
|
dev = dev_priv->dev;
|
|
|
|
|
2010-09-29 05:26:37 -06:00
|
|
|
/* Come back later if the device is busy... */
|
|
|
|
if (!mutex_trylock(&dev->struct_mutex)) {
|
|
|
|
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-07-23 16:18:49 -06:00
|
|
|
i915_gem_retire_requests(dev);
|
2010-05-20 19:08:57 -06:00
|
|
|
|
2011-01-09 14:05:44 -07:00
|
|
|
/* Send a periodic flush down the ring so we don't hold onto GEM
|
|
|
|
* objects indefinitely.
|
|
|
|
*/
|
|
|
|
idle = true;
|
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++) {
|
|
|
|
struct intel_ring_buffer *ring = &dev_priv->ring[i];
|
|
|
|
|
|
|
|
if (!list_empty(&ring->gpu_write_list)) {
|
|
|
|
struct drm_i915_gem_request *request;
|
|
|
|
int ret;
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_gem_flush_ring(ring,
|
|
|
|
0, I915_GEM_GPU_DOMAINS);
|
2011-01-09 14:05:44 -07:00
|
|
|
request = kzalloc(sizeof(*request), GFP_KERNEL);
|
|
|
|
if (ret || request == NULL ||
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_add_request(ring, NULL, request))
|
2011-01-09 14:05:44 -07:00
|
|
|
kfree(request);
|
|
|
|
}
|
|
|
|
|
|
|
|
idle &= list_empty(&ring->request_list);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!dev_priv->mm.suspended && !idle)
|
2009-08-03 17:09:16 -06:00
|
|
|
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
|
2011-01-09 14:05:44 -07:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
}
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
/**
|
|
|
|
* Waits for a sequence number to be signaled, and cleans up the
|
|
|
|
* request and object lists appropriately for that event.
|
|
|
|
*/
|
2009-09-15 14:57:36 -06:00
|
|
|
int
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_wait_request(struct intel_ring_buffer *ring,
|
2011-02-21 07:43:56 -07:00
|
|
|
uint32_t seqno)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2011-02-03 04:57:46 -07:00
|
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
2009-05-05 17:03:48 -06:00
|
|
|
u32 ier;
|
2008-07-30 13:06:12 -06:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
BUG_ON(seqno == 0);
|
|
|
|
|
2011-02-07 06:09:31 -07:00
|
|
|
if (atomic_read(&dev_priv->mm.wedged)) {
|
|
|
|
struct completion *x = &dev_priv->error_completion;
|
|
|
|
bool recovery_complete;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
/* Give the error handler a chance to run. */
|
|
|
|
spin_lock_irqsave(&x->wait.lock, flags);
|
|
|
|
recovery_complete = x->done > 0;
|
|
|
|
spin_unlock_irqrestore(&x->wait.lock, flags);
|
|
|
|
|
|
|
|
return recovery_complete ? -EIO : -EAGAIN;
|
|
|
|
}
|
2010-09-25 03:19:17 -06:00
|
|
|
|
2010-11-10 13:40:02 -07:00
|
|
|
if (seqno == ring->outstanding_lazy_request) {
|
2010-10-27 09:11:02 -06:00
|
|
|
struct drm_i915_gem_request *request;
|
|
|
|
|
|
|
|
request = kzalloc(sizeof(*request), GFP_KERNEL);
|
|
|
|
if (request == NULL)
|
drm/i915: allow lazy emitting of requests
Sometimes (like when flushing in preparation of batchbuffer execution)
we know that we'll emit a request but haven't yet done so. Allow this
case by simply taking the next seqno by default. Ensure that a request
is eventually emitted before waiting for an request by issuing it
in i915_wait_request iff this is not yet done.
Also replace one open-coded version of i915_gem_object_wait_rendering,
to prevent future code-diversion.
Chris Wilson asked me to explain and clarify what this patch does and why.
Here it goes:
Old way of moving objects onto the active list and associating them with a
reques:
1. i915_add_request + store the returned seqno somewhere
2. i915_gem_object_move_to_active (with the stored seqno as parameter)
For the current users, this is all fine. But I'd like to associate objects
(and fence regs) with the batchbuffer request deep down in the execbuf
call-chain. I thought about three ways of implementing this.
a) Don't care, just emit request when we need a new seqno. When heavily
pipelining fence reg changes, this would have caused tons of superflous
request (and corresponding irqs).
b) Thread all changed fences, objects, whatever through the execbuf-maze,
so that when we emit a request, we can store the new seqno at all the right
places.
c) Kill that seqno-threading-around business by simply storing the next
seqno, i.e. allow 2. to be done before 1. in the above sequence.
I've decided to implement c) (in this patch). The following patches are
just fall-out that resulted from this small conceptual change.
* We can handle the flushing list processing where we actually emit a flush
(i915_gem_flush and i915_retire_commands) instead of in i915_add_request.
The code makes IMHO more sense this way (and i915_add_request looses the
flush_domains parameter, obviously).
* We can avoid emitting unnecessary requests. IMHO there's no point in
emitting more than one request per batchbuffer (with or without an
corresponding irq).
* By enforcing 2. before 1. ordering in the above sequence the seqno
argument of i915_gem_object_move_to_active is redundant and can be
dropped.
v2: Now i915_wait_request issues request if it is not yet emitted.
Also introduce i915_gem_next_request_seqno(dev) just in case we ever
need to do some prep work before using a new seqno.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[ickle: Keep i915_gem_object_set_to_display_plane() uninterruptible.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-02-11 14:13:59 -07:00
|
|
|
return -ENOMEM;
|
2010-10-27 09:11:02 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_add_request(ring, NULL, request);
|
2010-10-27 09:11:02 -06:00
|
|
|
if (ret) {
|
|
|
|
kfree(request);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
seqno = request->seqno;
|
drm/i915: allow lazy emitting of requests
Sometimes (like when flushing in preparation of batchbuffer execution)
we know that we'll emit a request but haven't yet done so. Allow this
case by simply taking the next seqno by default. Ensure that a request
is eventually emitted before waiting for an request by issuing it
in i915_wait_request iff this is not yet done.
Also replace one open-coded version of i915_gem_object_wait_rendering,
to prevent future code-diversion.
Chris Wilson asked me to explain and clarify what this patch does and why.
Here it goes:
Old way of moving objects onto the active list and associating them with a
reques:
1. i915_add_request + store the returned seqno somewhere
2. i915_gem_object_move_to_active (with the stored seqno as parameter)
For the current users, this is all fine. But I'd like to associate objects
(and fence regs) with the batchbuffer request deep down in the execbuf
call-chain. I thought about three ways of implementing this.
a) Don't care, just emit request when we need a new seqno. When heavily
pipelining fence reg changes, this would have caused tons of superflous
request (and corresponding irqs).
b) Thread all changed fences, objects, whatever through the execbuf-maze,
so that when we emit a request, we can store the new seqno at all the right
places.
c) Kill that seqno-threading-around business by simply storing the next
seqno, i.e. allow 2. to be done before 1. in the above sequence.
I've decided to implement c) (in this patch). The following patches are
just fall-out that resulted from this small conceptual change.
* We can handle the flushing list processing where we actually emit a flush
(i915_gem_flush and i915_retire_commands) instead of in i915_add_request.
The code makes IMHO more sense this way (and i915_add_request looses the
flush_domains parameter, obviously).
* We can avoid emitting unnecessary requests. IMHO there's no point in
emitting more than one request per batchbuffer (with or without an
corresponding irq).
* By enforcing 2. before 1. ordering in the above sequence the seqno
argument of i915_gem_object_move_to_active is redundant and can be
dropped.
v2: Now i915_wait_request issues request if it is not yet emitted.
Also introduce i915_gem_next_request_seqno(dev) just in case we ever
need to do some prep work before using a new seqno.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[ickle: Keep i915_gem_object_set_to_display_plane() uninterruptible.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-02-11 14:13:59 -07:00
|
|
|
}
|
2009-09-14 15:48:41 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
|
2011-02-03 04:57:46 -07:00
|
|
|
if (HAS_PCH_SPLIT(ring->dev))
|
2009-06-08 00:40:19 -06:00
|
|
|
ier = I915_READ(DEIER) | I915_READ(GTIER);
|
|
|
|
else
|
|
|
|
ier = I915_READ(IER);
|
2009-05-05 17:03:48 -06:00
|
|
|
if (!ier) {
|
|
|
|
DRM_ERROR("something (likely vbetool) disabled "
|
|
|
|
"interrupts, re-enabling\n");
|
2011-06-28 04:48:51 -06:00
|
|
|
ring->dev->driver->irq_preinstall(ring->dev);
|
|
|
|
ring->dev->driver->irq_postinstall(ring->dev);
|
2009-05-05 17:03:48 -06:00
|
|
|
}
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_request_wait_begin(ring, seqno);
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2010-10-27 08:27:33 -06:00
|
|
|
ring->waiting_seqno = seqno;
|
2010-12-13 09:54:50 -07:00
|
|
|
if (ring->irq_get(ring)) {
|
2011-02-21 07:43:56 -07:00
|
|
|
if (dev_priv->mm.interruptible)
|
2010-12-13 09:54:50 -07:00
|
|
|
ret = wait_event_interruptible(ring->irq_queue,
|
|
|
|
i915_seqno_passed(ring->get_seqno(ring), seqno)
|
|
|
|
|| atomic_read(&dev_priv->mm.wedged));
|
|
|
|
else
|
|
|
|
wait_event(ring->irq_queue,
|
|
|
|
i915_seqno_passed(ring->get_seqno(ring), seqno)
|
|
|
|
|| atomic_read(&dev_priv->mm.wedged));
|
|
|
|
|
|
|
|
ring->irq_put(ring);
|
2010-12-14 05:17:15 -07:00
|
|
|
} else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
|
|
|
|
seqno) ||
|
|
|
|
atomic_read(&dev_priv->mm.wedged), 3000))
|
|
|
|
ret = -EBUSY;
|
2010-10-27 08:27:33 -06:00
|
|
|
ring->waiting_seqno = 0;
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_request_wait_end(ring, seqno);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
2009-09-14 15:48:47 -06:00
|
|
|
if (atomic_read(&dev_priv->mm.wedged))
|
2010-09-25 03:19:17 -06:00
|
|
|
ret = -EAGAIN;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
if (ret && ret != -ERESTARTSYS)
|
2010-02-11 14:19:40 -07:00
|
|
|
DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
|
2010-10-27 05:18:21 -06:00
|
|
|
__func__, ret, seqno, ring->get_seqno(ring),
|
2010-02-11 14:19:40 -07:00
|
|
|
dev_priv->next_seqno);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
/* Directly dispatch request retiring. While we have the work queue
|
|
|
|
* to handle this, the waiter on a request often wants an associated
|
|
|
|
* buffer to have made it to the inactive list, and we would need
|
|
|
|
* a separate wait queue to handle that.
|
|
|
|
*/
|
|
|
|
if (ret == 0)
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_gem_retire_requests_ring(ring);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Ensures that all rendering to the object has completed and the object is
|
|
|
|
* safe to unbind from the GTT or access from the CPU.
|
|
|
|
*/
|
2010-11-25 11:00:26 -07:00
|
|
|
int
|
2011-02-21 07:43:56 -07:00
|
|
|
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/* This function only exists to support waiting for existing rendering,
|
|
|
|
* not for emitting required flushes.
|
2008-07-30 13:06:12 -06:00
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
/* If there is rendering queued on the buffer being evicted, wait for
|
|
|
|
* it.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->active) {
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
|
2010-09-14 06:03:28 -06:00
|
|
|
if (ret)
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-04-13 15:06:03 -06:00
|
|
|
static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
|
|
|
|
{
|
|
|
|
u32 old_write_domain, old_read_domains;
|
|
|
|
|
|
|
|
/* Act a barrier for all accesses through the GTT */
|
|
|
|
mb();
|
|
|
|
|
|
|
|
/* Force a pagefault for domain tracking on next user access */
|
|
|
|
i915_gem_release_mmap(obj);
|
|
|
|
|
2011-06-24 22:02:59 -06:00
|
|
|
if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
|
|
|
|
return;
|
|
|
|
|
2011-04-13 15:06:03 -06:00
|
|
|
old_read_domains = obj->base.read_domains;
|
|
|
|
old_write_domain = obj->base.write_domain;
|
|
|
|
|
|
|
|
obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
|
|
|
|
obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
|
|
|
|
|
|
|
|
trace_i915_gem_object_change_domain(obj,
|
|
|
|
old_read_domains,
|
|
|
|
old_write_domain);
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/**
|
|
|
|
* Unbinds an object from the GTT aperture.
|
|
|
|
*/
|
2009-01-26 18:10:45 -07:00
|
|
|
int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_unbind(struct drm_i915_gem_object *obj)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->gtt_space == NULL)
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->pin_count != 0) {
|
2008-07-30 13:06:12 -06:00
|
|
|
DRM_ERROR("Attempting to unbind pinned buffer\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2011-04-13 15:04:09 -06:00
|
|
|
ret = i915_gem_object_finish_gpu(obj);
|
|
|
|
if (ret == -ERESTARTSYS)
|
|
|
|
return ret;
|
|
|
|
/* Continue on if we fail due to EIO, the GPU is hung so we
|
|
|
|
* should be safe and we need to cleanup or else we might
|
|
|
|
* cause memory corruption through use-after-free.
|
|
|
|
*/
|
|
|
|
|
2011-04-13 15:06:03 -06:00
|
|
|
i915_gem_object_finish_gtt(obj);
|
2009-09-09 12:50:45 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/* Move the object to the CPU domain to ensure that
|
|
|
|
* any possible CPU writes while it's not in the GTT
|
2011-04-13 15:04:09 -06:00
|
|
|
* are flushed when we go to remap it.
|
2008-07-30 13:06:12 -06:00
|
|
|
*/
|
2011-04-13 15:04:09 -06:00
|
|
|
if (ret == 0)
|
|
|
|
ret = i915_gem_object_set_to_cpu_domain(obj, 1);
|
2010-07-23 16:18:51 -06:00
|
|
|
if (ret == -ERESTARTSYS)
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
2010-09-30 08:08:57 -06:00
|
|
|
if (ret) {
|
2011-04-13 15:04:09 -06:00
|
|
|
/* In the event of a disaster, abandon all caches and
|
|
|
|
* hope for the best.
|
|
|
|
*/
|
2010-09-30 08:08:57 -06:00
|
|
|
i915_gem_clflush_object(obj);
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
|
2010-09-30 08:08:57 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2009-12-15 09:50:00 -07:00
|
|
|
/* release the fence reg _after_ flushing */
|
2010-11-10 09:40:20 -07:00
|
|
|
ret = i915_gem_object_put_fence(obj);
|
|
|
|
if (ret == -ERESTARTSYS)
|
|
|
|
return ret;
|
2009-12-15 09:50:00 -07:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_object_unbind(obj);
|
|
|
|
|
2010-11-06 03:10:47 -06:00
|
|
|
i915_gem_gtt_unbind_object(obj);
|
2010-10-28 06:45:36 -06:00
|
|
|
i915_gem_object_put_pages_gtt(obj);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-24 05:23:44 -07:00
|
|
|
list_del_init(&obj->gtt_list);
|
2010-11-08 12:18:58 -07:00
|
|
|
list_del_init(&obj->mm_list);
|
2010-11-04 10:11:09 -06:00
|
|
|
/* Avoid an unnecessary call to unbind on rebind. */
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->map_and_fenceable = true;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_mm_put_block(obj->gtt_space);
|
|
|
|
obj->gtt_space = NULL;
|
|
|
|
obj->gtt_offset = 0;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (i915_gem_object_is_purgeable(obj))
|
2009-09-20 16:03:54 -06:00
|
|
|
i915_gem_object_truncate(obj);
|
|
|
|
|
2010-07-23 16:18:51 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
int
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_gem_flush_ring(struct intel_ring_buffer *ring,
|
2010-11-25 11:00:26 -07:00
|
|
|
uint32_t invalidate_domains,
|
|
|
|
uint32_t flush_domains)
|
|
|
|
{
|
2011-01-07 10:09:48 -07:00
|
|
|
int ret;
|
|
|
|
|
2011-03-19 16:26:49 -06:00
|
|
|
if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
|
|
|
|
return 0;
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
ret = ring->flush(ring, invalidate_domains, flush_domains);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-03-19 16:26:49 -06:00
|
|
|
if (flush_domains & I915_GEM_GPU_DOMAINS)
|
|
|
|
i915_gem_process_flushing_list(ring, flush_domains);
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
return 0;
|
2010-11-25 11:00:26 -07:00
|
|
|
}
|
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
static int i915_ring_idle(struct intel_ring_buffer *ring)
|
2010-09-28 03:07:56 -06:00
|
|
|
{
|
2011-01-07 10:09:48 -07:00
|
|
|
int ret;
|
|
|
|
|
2010-10-28 14:28:46 -06:00
|
|
|
if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
|
2010-10-24 05:38:05 -06:00
|
|
|
return 0;
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
if (!list_empty(&ring->gpu_write_list)) {
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_gem_flush_ring(ring,
|
2010-12-06 07:36:02 -07:00
|
|
|
I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
|
2011-01-07 10:09:48 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
|
2010-09-28 03:07:56 -06:00
|
|
|
}
|
|
|
|
|
2010-08-07 04:01:23 -06:00
|
|
|
int
|
2010-02-19 03:52:00 -07:00
|
|
|
i915_gpu_idle(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-12-04 04:30:53 -07:00
|
|
|
int ret, i;
|
2010-02-19 03:52:00 -07:00
|
|
|
|
|
|
|
/* Flush everything onto the inactive list. */
|
2010-12-04 04:30:53 -07:00
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++) {
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_ring_idle(&dev_priv->ring[i]);
|
2010-12-04 04:30:53 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2010-02-19 03:52:00 -07:00
|
|
|
|
2010-02-11 14:29:04 -07:00
|
|
|
return 0;
|
2010-02-19 03:52:00 -07:00
|
|
|
}
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
|
|
|
|
struct intel_ring_buffer *pipelined)
|
2009-10-26 17:44:17 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2009-10-26 17:44:17 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-11-08 12:18:58 -07:00
|
|
|
u32 size = obj->gtt_space->size;
|
|
|
|
int regnum = obj->fence_reg;
|
2009-10-26 17:44:17 -06:00
|
|
|
uint64_t val;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
val = (uint64_t)((obj->gtt_offset + size - 4096) &
|
2010-11-12 06:46:18 -07:00
|
|
|
0xfffff000) << 32;
|
2010-11-08 12:18:58 -07:00
|
|
|
val |= obj->gtt_offset & 0xfffff000;
|
|
|
|
val |= (uint64_t)((obj->stride / 128) - 1) <<
|
2009-10-26 17:44:17 -06:00
|
|
|
SANDYBRIDGE_FENCE_PITCH_SHIFT;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->tiling_mode == I915_TILING_Y)
|
2009-10-26 17:44:17 -06:00
|
|
|
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
|
|
|
|
val |= I965_FENCE_REG_VALID;
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
if (pipelined) {
|
|
|
|
int ret = intel_ring_begin(pipelined, 6);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
intel_ring_emit(pipelined, MI_NOOP);
|
|
|
|
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
|
|
|
|
intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
|
|
|
|
intel_ring_emit(pipelined, (u32)val);
|
|
|
|
intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
|
|
|
|
intel_ring_emit(pipelined, (u32)(val >> 32));
|
|
|
|
intel_ring_advance(pipelined);
|
|
|
|
} else
|
|
|
|
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
|
|
|
|
|
|
|
|
return 0;
|
2009-10-26 17:44:17 -06:00
|
|
|
}
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
|
|
|
|
struct intel_ring_buffer *pipelined)
|
2008-11-12 11:03:55 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2008-11-12 11:03:55 -07:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-11-08 12:18:58 -07:00
|
|
|
u32 size = obj->gtt_space->size;
|
|
|
|
int regnum = obj->fence_reg;
|
2008-11-12 11:03:55 -07:00
|
|
|
uint64_t val;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
val = (uint64_t)((obj->gtt_offset + size - 4096) &
|
2008-11-12 11:03:55 -07:00
|
|
|
0xfffff000) << 32;
|
2010-11-08 12:18:58 -07:00
|
|
|
val |= obj->gtt_offset & 0xfffff000;
|
|
|
|
val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
|
|
|
|
if (obj->tiling_mode == I915_TILING_Y)
|
2008-11-12 11:03:55 -07:00
|
|
|
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
|
|
|
|
val |= I965_FENCE_REG_VALID;
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
if (pipelined) {
|
|
|
|
int ret = intel_ring_begin(pipelined, 6);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
intel_ring_emit(pipelined, MI_NOOP);
|
|
|
|
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
|
|
|
|
intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
|
|
|
|
intel_ring_emit(pipelined, (u32)val);
|
|
|
|
intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
|
|
|
|
intel_ring_emit(pipelined, (u32)(val >> 32));
|
|
|
|
intel_ring_advance(pipelined);
|
|
|
|
} else
|
|
|
|
I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
|
|
|
|
|
|
|
|
return 0;
|
2008-11-12 11:03:55 -07:00
|
|
|
}
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
|
|
|
|
struct intel_ring_buffer *pipelined)
|
2008-11-12 11:03:55 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2008-11-12 11:03:55 -07:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-11-08 12:18:58 -07:00
|
|
|
u32 size = obj->gtt_space->size;
|
2010-11-12 06:46:18 -07:00
|
|
|
u32 fence_reg, val, pitch_val;
|
2009-01-26 18:10:45 -07:00
|
|
|
int tile_width;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
|
|
|
|
(size & -size) != size ||
|
|
|
|
(obj->gtt_offset & (size - 1)),
|
|
|
|
"object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
|
|
|
|
obj->gtt_offset, obj->map_and_fenceable, size))
|
|
|
|
return -EINVAL;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
|
2009-01-26 18:10:45 -07:00
|
|
|
tile_width = 128;
|
2008-11-12 11:03:55 -07:00
|
|
|
else
|
2009-01-26 18:10:45 -07:00
|
|
|
tile_width = 512;
|
|
|
|
|
|
|
|
/* Note: pitch better be a power of two tile widths */
|
2010-11-08 12:18:58 -07:00
|
|
|
pitch_val = obj->stride / tile_width;
|
2009-01-26 18:10:45 -07:00
|
|
|
pitch_val = ffs(pitch_val) - 1;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
val = obj->gtt_offset;
|
|
|
|
if (obj->tiling_mode == I915_TILING_Y)
|
2008-11-12 11:03:55 -07:00
|
|
|
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
|
2010-09-24 14:15:47 -06:00
|
|
|
val |= I915_FENCE_SIZE_BITS(size);
|
2008-11-12 11:03:55 -07:00
|
|
|
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
|
|
|
|
val |= I830_FENCE_REG_VALID;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
fence_reg = obj->fence_reg;
|
2010-09-24 14:15:47 -06:00
|
|
|
if (fence_reg < 8)
|
|
|
|
fence_reg = FENCE_REG_830_0 + fence_reg * 4;
|
2009-03-10 23:34:49 -06:00
|
|
|
else
|
2010-09-24 14:15:47 -06:00
|
|
|
fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
|
2010-11-12 06:46:18 -07:00
|
|
|
|
|
|
|
if (pipelined) {
|
|
|
|
int ret = intel_ring_begin(pipelined, 4);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
intel_ring_emit(pipelined, MI_NOOP);
|
|
|
|
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
|
|
|
|
intel_ring_emit(pipelined, fence_reg);
|
|
|
|
intel_ring_emit(pipelined, val);
|
|
|
|
intel_ring_advance(pipelined);
|
|
|
|
} else
|
|
|
|
I915_WRITE(fence_reg, val);
|
|
|
|
|
|
|
|
return 0;
|
2008-11-12 11:03:55 -07:00
|
|
|
}
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
|
|
|
|
struct intel_ring_buffer *pipelined)
|
2008-11-12 11:03:55 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2008-11-12 11:03:55 -07:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-11-08 12:18:58 -07:00
|
|
|
u32 size = obj->gtt_space->size;
|
|
|
|
int regnum = obj->fence_reg;
|
2008-11-12 11:03:55 -07:00
|
|
|
uint32_t val;
|
|
|
|
uint32_t pitch_val;
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
|
|
|
|
(size & -size) != size ||
|
|
|
|
(obj->gtt_offset & (size - 1)),
|
|
|
|
"object 0x%08x not 512K or pot-size 0x%08x aligned\n",
|
|
|
|
obj->gtt_offset, size))
|
|
|
|
return -EINVAL;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
pitch_val = obj->stride / 128;
|
2009-05-26 18:44:56 -06:00
|
|
|
pitch_val = ffs(pitch_val) - 1;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
val = obj->gtt_offset;
|
|
|
|
if (obj->tiling_mode == I915_TILING_Y)
|
2008-11-12 11:03:55 -07:00
|
|
|
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
|
2010-11-12 06:46:18 -07:00
|
|
|
val |= I830_FENCE_SIZE_BITS(size);
|
2008-11-12 11:03:55 -07:00
|
|
|
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
|
|
|
|
val |= I830_FENCE_REG_VALID;
|
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
if (pipelined) {
|
|
|
|
int ret = intel_ring_begin(pipelined, 4);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
intel_ring_emit(pipelined, MI_NOOP);
|
|
|
|
intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
|
|
|
|
intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
|
|
|
|
intel_ring_emit(pipelined, val);
|
|
|
|
intel_ring_advance(pipelined);
|
|
|
|
} else
|
|
|
|
I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
|
|
|
|
|
|
|
|
return 0;
|
2008-11-12 11:03:55 -07:00
|
|
|
}
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
|
|
|
|
{
|
|
|
|
return i915_seqno_passed(ring->get_seqno(ring), seqno);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
|
2011-02-21 07:43:56 -07:00
|
|
|
struct intel_ring_buffer *pipelined)
|
2010-11-10 09:40:20 -07:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (obj->fenced_gpu_access) {
|
2011-01-07 10:09:48 -07:00
|
|
|
if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_gem_flush_ring(obj->last_fenced_ring,
|
2011-01-07 10:09:48 -07:00
|
|
|
0, obj->base.write_domain);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2010-11-10 09:40:20 -07:00
|
|
|
|
|
|
|
obj->fenced_gpu_access = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
|
|
|
|
if (!ring_passed_seqno(obj->last_fenced_ring,
|
|
|
|
obj->last_fenced_seqno)) {
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_wait_request(obj->last_fenced_ring,
|
2011-02-21 07:43:56 -07:00
|
|
|
obj->last_fenced_seqno);
|
2010-11-10 09:40:20 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
obj->last_fenced_seqno = 0;
|
|
|
|
obj->last_fenced_ring = NULL;
|
|
|
|
}
|
|
|
|
|
2011-01-04 11:42:07 -07:00
|
|
|
/* Ensure that all CPU reads are completed before installing a fence
|
|
|
|
* and all writes before removing the fence.
|
|
|
|
*/
|
|
|
|
if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
|
|
|
|
mb();
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (obj->tiling_mode)
|
|
|
|
i915_gem_release_mmap(obj);
|
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_flush_fence(obj, NULL);
|
2010-11-10 09:40:20 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (obj->fence_reg != I915_FENCE_REG_NONE) {
|
|
|
|
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
|
|
|
|
i915_gem_clear_fence_reg(obj->base.dev,
|
|
|
|
&dev_priv->fence_regs[obj->fence_reg]);
|
|
|
|
|
|
|
|
obj->fence_reg = I915_FENCE_REG_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct drm_i915_fence_reg *
|
|
|
|
i915_find_fence_reg(struct drm_device *dev,
|
|
|
|
struct intel_ring_buffer *pipelined)
|
2010-02-19 03:51:58 -07:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-11-10 09:40:20 -07:00
|
|
|
struct drm_i915_fence_reg *reg, *first, *avail;
|
|
|
|
int i;
|
2010-02-19 03:51:58 -07:00
|
|
|
|
|
|
|
/* First try to find a free reg */
|
2010-11-10 09:40:20 -07:00
|
|
|
avail = NULL;
|
2010-02-19 03:51:58 -07:00
|
|
|
for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
|
|
|
|
reg = &dev_priv->fence_regs[i];
|
|
|
|
if (!reg->obj)
|
2010-11-10 09:40:20 -07:00
|
|
|
return reg;
|
2010-02-19 03:51:58 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (!reg->obj->pin_count)
|
2010-11-10 09:40:20 -07:00
|
|
|
avail = reg;
|
2010-02-19 03:51:58 -07:00
|
|
|
}
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
if (avail == NULL)
|
|
|
|
return NULL;
|
2010-02-19 03:51:58 -07:00
|
|
|
|
|
|
|
/* None available, try to steal one or wait for a user to finish */
|
2010-11-10 09:40:20 -07:00
|
|
|
avail = first = NULL;
|
|
|
|
list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
|
|
|
|
if (reg->obj->pin_count)
|
2010-02-19 03:51:58 -07:00
|
|
|
continue;
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
if (first == NULL)
|
|
|
|
first = reg;
|
|
|
|
|
|
|
|
if (!pipelined ||
|
|
|
|
!reg->obj->last_fenced_ring ||
|
|
|
|
reg->obj->last_fenced_ring == pipelined) {
|
|
|
|
avail = reg;
|
|
|
|
break;
|
|
|
|
}
|
2010-02-19 03:51:58 -07:00
|
|
|
}
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
if (avail == NULL)
|
|
|
|
avail = first;
|
2010-02-19 03:51:58 -07:00
|
|
|
|
2010-09-24 14:15:47 -06:00
|
|
|
return avail;
|
2010-02-19 03:51:58 -07:00
|
|
|
}
|
|
|
|
|
2008-11-12 11:03:55 -07:00
|
|
|
/**
|
2010-11-10 09:40:20 -07:00
|
|
|
* i915_gem_object_get_fence - set up a fence reg for an object
|
2008-11-12 11:03:55 -07:00
|
|
|
* @obj: object to map through a fence reg
|
2010-11-10 09:40:20 -07:00
|
|
|
* @pipelined: ring on which to queue the change, or NULL for CPU access
|
|
|
|
* @interruptible: must we wait uninterruptibly for the register to retire?
|
2008-11-12 11:03:55 -07:00
|
|
|
*
|
|
|
|
* When mapping objects through the GTT, userspace wants to be able to write
|
|
|
|
* to them without having to worry about swizzling if the object is tiled.
|
|
|
|
*
|
|
|
|
* This function walks the fence regs looking for a free one for @obj,
|
|
|
|
* stealing one if it can't find any.
|
|
|
|
*
|
|
|
|
* It then sets up the reg based on the object's properties: address, pitch
|
|
|
|
* and tiling format.
|
|
|
|
*/
|
2009-06-17 15:08:52 -06:00
|
|
|
int
|
2010-11-10 09:40:20 -07:00
|
|
|
i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
|
2011-02-21 07:43:56 -07:00
|
|
|
struct intel_ring_buffer *pipelined)
|
2008-11-12 11:03:55 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-11-10 09:40:20 -07:00
|
|
|
struct drm_i915_fence_reg *reg;
|
2010-02-19 03:51:58 -07:00
|
|
|
int ret;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-12-05 14:04:18 -07:00
|
|
|
/* XXX disable pipelining. There are bugs. Shocking. */
|
|
|
|
pipelined = NULL;
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
/* Just update our place in the LRU if our fence is getting reused. */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->fence_reg != I915_FENCE_REG_NONE) {
|
|
|
|
reg = &dev_priv->fence_regs[obj->fence_reg];
|
2010-04-28 03:02:31 -06:00
|
|
|
list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
|
2010-11-10 09:40:20 -07:00
|
|
|
|
2011-03-17 09:23:22 -06:00
|
|
|
if (obj->tiling_changed) {
|
|
|
|
ret = i915_gem_object_flush_fence(obj, pipelined);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
|
|
|
|
pipelined = NULL;
|
|
|
|
|
|
|
|
if (pipelined) {
|
|
|
|
reg->setup_seqno =
|
|
|
|
i915_gem_next_request_seqno(pipelined);
|
|
|
|
obj->last_fenced_seqno = reg->setup_seqno;
|
|
|
|
obj->last_fenced_ring = pipelined;
|
|
|
|
}
|
|
|
|
|
|
|
|
goto update;
|
|
|
|
}
|
2010-11-10 09:40:20 -07:00
|
|
|
|
|
|
|
if (!pipelined) {
|
|
|
|
if (reg->setup_seqno) {
|
|
|
|
if (!ring_passed_seqno(obj->last_fenced_ring,
|
|
|
|
reg->setup_seqno)) {
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_wait_request(obj->last_fenced_ring,
|
2011-02-21 07:43:56 -07:00
|
|
|
reg->setup_seqno);
|
2010-11-10 09:40:20 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg->setup_seqno = 0;
|
|
|
|
}
|
|
|
|
} else if (obj->last_fenced_ring &&
|
|
|
|
obj->last_fenced_ring != pipelined) {
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_flush_fence(obj, pipelined);
|
2010-11-10 09:40:20 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-08-29 13:49:51 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
reg = i915_find_fence_reg(dev, pipelined);
|
|
|
|
if (reg == NULL)
|
|
|
|
return -ENOSPC;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_flush_fence(obj, pipelined);
|
2010-11-10 09:40:20 -07:00
|
|
|
if (ret)
|
2010-02-19 03:51:58 -07:00
|
|
|
return ret;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
if (reg->obj) {
|
|
|
|
struct drm_i915_gem_object *old = reg->obj;
|
|
|
|
|
|
|
|
drm_gem_object_reference(&old->base);
|
|
|
|
|
|
|
|
if (old->tiling_mode)
|
|
|
|
i915_gem_release_mmap(old);
|
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_flush_fence(old, pipelined);
|
2010-11-10 09:40:20 -07:00
|
|
|
if (ret) {
|
|
|
|
drm_gem_object_unreference(&old->base);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
|
|
|
|
pipelined = NULL;
|
|
|
|
|
|
|
|
old->fence_reg = I915_FENCE_REG_NONE;
|
|
|
|
old->last_fenced_ring = pipelined;
|
|
|
|
old->last_fenced_seqno =
|
2011-02-03 04:57:46 -07:00
|
|
|
pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
|
2010-11-10 09:40:20 -07:00
|
|
|
|
|
|
|
drm_gem_object_unreference(&old->base);
|
|
|
|
} else if (obj->last_fenced_seqno == 0)
|
|
|
|
pipelined = NULL;
|
2009-08-29 13:49:51 -06:00
|
|
|
|
2008-11-12 11:03:55 -07:00
|
|
|
reg->obj = obj;
|
2010-11-10 09:40:20 -07:00
|
|
|
list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
|
|
|
|
obj->fence_reg = reg - dev_priv->fence_regs;
|
|
|
|
obj->last_fenced_ring = pipelined;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-10 09:40:20 -07:00
|
|
|
reg->setup_seqno =
|
2011-02-03 04:57:46 -07:00
|
|
|
pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
|
2010-11-10 09:40:20 -07:00
|
|
|
obj->last_fenced_seqno = reg->setup_seqno;
|
|
|
|
|
|
|
|
update:
|
|
|
|
obj->tiling_changed = false;
|
2010-09-16 17:32:02 -06:00
|
|
|
switch (INTEL_INFO(dev)->gen) {
|
2011-05-06 14:55:53 -06:00
|
|
|
case 7:
|
2010-09-16 17:32:02 -06:00
|
|
|
case 6:
|
2010-11-12 06:46:18 -07:00
|
|
|
ret = sandybridge_write_fence_reg(obj, pipelined);
|
2010-09-16 17:32:02 -06:00
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
case 4:
|
2010-11-12 06:46:18 -07:00
|
|
|
ret = i965_write_fence_reg(obj, pipelined);
|
2010-09-16 17:32:02 -06:00
|
|
|
break;
|
|
|
|
case 3:
|
2010-11-12 06:46:18 -07:00
|
|
|
ret = i915_write_fence_reg(obj, pipelined);
|
2010-09-16 17:32:02 -06:00
|
|
|
break;
|
|
|
|
case 2:
|
2010-11-12 06:46:18 -07:00
|
|
|
ret = i830_write_fence_reg(obj, pipelined);
|
2010-09-16 17:32:02 -06:00
|
|
|
break;
|
|
|
|
}
|
2009-01-27 11:33:49 -07:00
|
|
|
|
2010-11-12 06:46:18 -07:00
|
|
|
return ret;
|
2008-11-12 11:03:55 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_gem_clear_fence_reg - clear out fence register info
|
|
|
|
* @obj: object to clear
|
|
|
|
*
|
|
|
|
* Zeroes out the fence register itself and clears out the associated
|
2010-11-08 12:18:58 -07:00
|
|
|
* data structures in dev_priv and obj.
|
2008-11-12 11:03:55 -07:00
|
|
|
*/
|
|
|
|
static void
|
2010-11-10 09:40:20 -07:00
|
|
|
i915_gem_clear_fence_reg(struct drm_device *dev,
|
|
|
|
struct drm_i915_fence_reg *reg)
|
2008-11-12 11:03:55 -07:00
|
|
|
{
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-11-10 09:40:20 -07:00
|
|
|
uint32_t fence_reg = reg - dev_priv->fence_regs;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-09-16 17:32:02 -06:00
|
|
|
switch (INTEL_INFO(dev)->gen) {
|
2011-05-06 14:55:53 -06:00
|
|
|
case 7:
|
2010-09-16 17:32:02 -06:00
|
|
|
case 6:
|
2010-11-10 09:40:20 -07:00
|
|
|
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
|
2010-09-16 17:32:02 -06:00
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
case 4:
|
2010-11-10 09:40:20 -07:00
|
|
|
I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
|
2010-09-16 17:32:02 -06:00
|
|
|
break;
|
|
|
|
case 3:
|
2010-11-10 09:40:20 -07:00
|
|
|
if (fence_reg >= 8)
|
|
|
|
fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
|
2009-03-10 23:34:49 -06:00
|
|
|
else
|
2010-09-16 17:32:02 -06:00
|
|
|
case 2:
|
2010-11-10 09:40:20 -07:00
|
|
|
fence_reg = FENCE_REG_830_0 + fence_reg * 4;
|
2009-03-10 23:34:49 -06:00
|
|
|
|
|
|
|
I915_WRITE(fence_reg, 0);
|
2010-09-16 17:32:02 -06:00
|
|
|
break;
|
2009-03-10 23:34:49 -06:00
|
|
|
}
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-04-28 03:02:31 -06:00
|
|
|
list_del_init(®->lru_list);
|
2010-11-10 09:40:20 -07:00
|
|
|
reg->obj = NULL;
|
|
|
|
reg->setup_seqno = 0;
|
2009-06-06 02:46:01 -06:00
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/**
|
|
|
|
* Finds free space in the GTT aperture and binds the object there.
|
|
|
|
*/
|
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
|
2010-09-16 09:54:23 -06:00
|
|
|
unsigned alignment,
|
2010-11-04 10:11:09 -06:00
|
|
|
bool map_and_fenceable)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2008-07-30 13:06:12 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
struct drm_mm_node *free_space;
|
2010-09-24 14:15:47 -06:00
|
|
|
gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
|
2010-11-14 14:32:36 -07:00
|
|
|
u32 size, fence_size, fence_alignment, unfenced_alignment;
|
2010-11-04 10:11:09 -06:00
|
|
|
bool mappable, fenceable;
|
2009-09-14 09:50:30 -06:00
|
|
|
int ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->madv != I915_MADV_WILLNEED) {
|
2009-09-14 09:50:29 -06:00
|
|
|
DRM_ERROR("Attempting to bind a purgeable object\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2011-07-18 14:11:49 -06:00
|
|
|
fence_size = i915_gem_get_gtt_size(dev,
|
|
|
|
obj->base.size,
|
|
|
|
obj->tiling_mode);
|
|
|
|
fence_alignment = i915_gem_get_gtt_alignment(dev,
|
|
|
|
obj->base.size,
|
|
|
|
obj->tiling_mode);
|
|
|
|
unfenced_alignment =
|
|
|
|
i915_gem_get_unfenced_gtt_alignment(dev,
|
|
|
|
obj->base.size,
|
|
|
|
obj->tiling_mode);
|
2010-09-24 14:15:47 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
if (alignment == 0)
|
2010-11-14 14:32:36 -07:00
|
|
|
alignment = map_and_fenceable ? fence_alignment :
|
|
|
|
unfenced_alignment;
|
2010-11-04 10:11:09 -06:00
|
|
|
if (map_and_fenceable && alignment & (fence_alignment - 1)) {
|
2008-07-30 13:06:12 -06:00
|
|
|
DRM_ERROR("Invalid object alignment requested %u\n", alignment);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
size = map_and_fenceable ? fence_size : obj->base.size;
|
2010-09-24 14:15:47 -06:00
|
|
|
|
2010-05-27 06:18:21 -06:00
|
|
|
/* If the object is bigger than the entire aperture, reject it early
|
|
|
|
* before evicting everything in a vain attempt to find space.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.size >
|
2010-11-04 10:11:09 -06:00
|
|
|
(map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
|
2010-05-27 06:18:21 -06:00
|
|
|
DRM_ERROR("Attempting to bind an object larger than the aperture\n");
|
|
|
|
return -E2BIG;
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
search_free:
|
2010-11-04 10:11:09 -06:00
|
|
|
if (map_and_fenceable)
|
2010-09-16 09:54:23 -06:00
|
|
|
free_space =
|
|
|
|
drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
|
2010-09-24 14:15:47 -06:00
|
|
|
size, alignment, 0,
|
2010-09-16 09:54:23 -06:00
|
|
|
dev_priv->mm.gtt_mappable_end,
|
|
|
|
0);
|
|
|
|
else
|
|
|
|
free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
|
2010-09-24 14:15:47 -06:00
|
|
|
size, alignment, 0);
|
2010-09-16 09:54:23 -06:00
|
|
|
|
|
|
|
if (free_space != NULL) {
|
2010-11-04 10:11:09 -06:00
|
|
|
if (map_and_fenceable)
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->gtt_space =
|
2010-09-16 09:54:23 -06:00
|
|
|
drm_mm_get_block_range_generic(free_space,
|
2010-09-24 14:15:47 -06:00
|
|
|
size, alignment, 0,
|
2010-09-16 09:54:23 -06:00
|
|
|
dev_priv->mm.gtt_mappable_end,
|
|
|
|
0);
|
|
|
|
else
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->gtt_space =
|
2010-09-24 14:15:47 -06:00
|
|
|
drm_mm_get_block(free_space, size, alignment);
|
2010-09-16 09:54:23 -06:00
|
|
|
}
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->gtt_space == NULL) {
|
2008-07-30 13:06:12 -06:00
|
|
|
/* If the gtt is empty and we're still having trouble
|
|
|
|
* fitting our object in, we're out of memory.
|
|
|
|
*/
|
2010-11-04 10:11:09 -06:00
|
|
|
ret = i915_gem_evict_something(dev, size, alignment,
|
|
|
|
map_and_fenceable);
|
2009-09-20 17:22:34 -06:00
|
|
|
if (ret)
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
2009-09-20 17:22:34 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
goto search_free;
|
|
|
|
}
|
|
|
|
|
2010-10-28 06:45:36 -06:00
|
|
|
ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
|
2008-07-30 13:06:12 -06:00
|
|
|
if (ret) {
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_mm_put_block(obj->gtt_space);
|
|
|
|
obj->gtt_space = NULL;
|
2009-09-14 09:50:30 -06:00
|
|
|
|
|
|
|
if (ret == -ENOMEM) {
|
2011-01-10 10:33:15 -07:00
|
|
|
/* first try to reclaim some memory by clearing the GTT */
|
|
|
|
ret = i915_gem_evict_everything(dev, false);
|
2009-09-14 09:50:30 -06:00
|
|
|
if (ret) {
|
|
|
|
/* now try to shrink everyone else */
|
2010-01-27 06:36:32 -07:00
|
|
|
if (gfpmask) {
|
|
|
|
gfpmask = 0;
|
|
|
|
goto search_free;
|
2009-09-14 09:50:30 -06:00
|
|
|
}
|
|
|
|
|
2011-01-10 10:33:15 -07:00
|
|
|
return -ENOMEM;
|
2009-09-14 09:50:30 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
goto search_free;
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-11-06 03:10:47 -06:00
|
|
|
ret = i915_gem_gtt_bind_object(obj);
|
|
|
|
if (ret) {
|
2010-10-28 06:45:36 -06:00
|
|
|
i915_gem_object_put_pages_gtt(obj);
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_mm_put_block(obj->gtt_space);
|
|
|
|
obj->gtt_space = NULL;
|
2009-09-14 09:50:30 -06:00
|
|
|
|
2011-01-10 10:33:15 -07:00
|
|
|
if (i915_gem_evict_everything(dev, false))
|
2009-09-14 09:50:30 -06:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
goto search_free;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-11-24 05:23:44 -07:00
|
|
|
list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
|
2010-11-08 12:18:58 -07:00
|
|
|
list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
|
2010-08-07 04:01:20 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/* Assert that the object is not currently in any GPU domain. As it
|
|
|
|
* wasn't in the GTT, there shouldn't be any way it could have been in
|
|
|
|
* a GPU cache
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
|
|
|
|
BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-24 05:23:44 -07:00
|
|
|
obj->gtt_offset = obj->gtt_space->start;
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2010-11-04 10:11:09 -06:00
|
|
|
fenceable =
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->gtt_space->size == fence_size &&
|
2011-08-16 13:34:10 -06:00
|
|
|
(obj->gtt_space->start & (fence_alignment - 1)) == 0;
|
2010-09-24 14:15:47 -06:00
|
|
|
|
2010-11-04 10:11:09 -06:00
|
|
|
mappable =
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
|
2010-09-24 14:15:47 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->map_and_fenceable = mappable && fenceable;
|
2010-11-04 10:11:09 -06:00
|
|
|
|
2011-02-03 04:57:46 -07:00
|
|
|
trace_i915_gem_object_bind(obj, map_and_fenceable);
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_clflush_object(struct drm_i915_gem_object *obj)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
/* If we don't have a page list set up, then we're not pinned
|
|
|
|
* to GPU, and we can ignore the cache flush because it'll happen
|
|
|
|
* again at bind time.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->pages == NULL)
|
2008-07-30 13:06:12 -06:00
|
|
|
return;
|
|
|
|
|
2011-03-29 17:59:52 -06:00
|
|
|
/* If the GPU is snooping the contents of the CPU cache,
|
|
|
|
* we do not need to manually clear the CPU cache lines. However,
|
|
|
|
* the caches are only snooped when the render cache is
|
|
|
|
* flushed/invalidated. As we always have to emit invalidations
|
|
|
|
* and flushes when moving into and out of the RENDER domain, correct
|
|
|
|
* snooping behaviour occurs naturally as the result of our domain
|
|
|
|
* tracking.
|
|
|
|
*/
|
|
|
|
if (obj->cache_level != I915_CACHE_NONE)
|
|
|
|
return;
|
|
|
|
|
2009-08-25 04:15:50 -06:00
|
|
|
trace_i915_gem_object_clflush(obj);
|
2009-05-26 19:46:16 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/** Flushes any GPU write domain for the object if it's dirty. */
|
2011-01-07 10:09:48 -07:00
|
|
|
static int
|
2010-11-28 08:37:17 -07:00
|
|
|
i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
|
2008-11-14 14:35:19 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
|
2011-01-07 10:09:48 -07:00
|
|
|
return 0;
|
2008-11-14 14:35:19 -07:00
|
|
|
|
|
|
|
/* Queue the GPU write cache flushing we need. */
|
2011-02-03 04:57:46 -07:00
|
|
|
return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
|
2008-11-14 14:35:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/** Flushes the GTT write domain for the object if it's dirty. */
|
|
|
|
static void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
|
2008-11-14 14:35:19 -07:00
|
|
|
{
|
2009-08-25 04:15:50 -06:00
|
|
|
uint32_t old_write_domain;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
|
2008-11-14 14:35:19 -07:00
|
|
|
return;
|
|
|
|
|
2011-01-04 11:42:07 -07:00
|
|
|
/* No actual flushing is required for the GTT write domain. Writes
|
2008-11-14 14:35:19 -07:00
|
|
|
* to it immediately go to main memory as far as we know, so there's
|
|
|
|
* no chipset flush. It also doesn't land in render cache.
|
2011-01-04 11:42:07 -07:00
|
|
|
*
|
|
|
|
* However, we do have to enforce the order so that all writes through
|
|
|
|
* the GTT land before any writes to the device, such as updates to
|
|
|
|
* the GATT itself.
|
2008-11-14 14:35:19 -07:00
|
|
|
*/
|
2011-01-04 11:42:07 -07:00
|
|
|
wmb();
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
old_write_domain = obj->base.write_domain;
|
|
|
|
obj->base.write_domain = 0;
|
2009-08-25 04:15:50 -06:00
|
|
|
|
|
|
|
trace_i915_gem_object_change_domain(obj,
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains,
|
2009-08-25 04:15:50 -06:00
|
|
|
old_write_domain);
|
2008-11-14 14:35:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/** Flushes the CPU write domain for the object if it's dirty. */
|
|
|
|
static void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
|
2008-11-14 14:35:19 -07:00
|
|
|
{
|
2009-08-25 04:15:50 -06:00
|
|
|
uint32_t old_write_domain;
|
2008-11-14 14:35:19 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
|
2008-11-14 14:35:19 -07:00
|
|
|
return;
|
|
|
|
|
|
|
|
i915_gem_clflush_object(obj);
|
2010-11-05 11:12:18 -06:00
|
|
|
intel_gtt_chipset_flush();
|
2010-11-08 12:18:58 -07:00
|
|
|
old_write_domain = obj->base.write_domain;
|
|
|
|
obj->base.write_domain = 0;
|
2009-08-25 04:15:50 -06:00
|
|
|
|
|
|
|
trace_i915_gem_object_change_domain(obj,
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains,
|
2009-08-25 04:15:50 -06:00
|
|
|
old_write_domain);
|
2008-11-14 14:35:19 -07:00
|
|
|
}
|
|
|
|
|
2008-11-10 11:53:25 -07:00
|
|
|
/**
|
|
|
|
* Moves a single object to the GTT read, and possibly write domain.
|
|
|
|
*
|
|
|
|
* This function returns when the move is complete, including waiting on
|
|
|
|
* flushes to occur.
|
|
|
|
*/
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
int
|
2010-11-23 08:26:33 -07:00
|
|
|
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
|
2008-11-10 11:53:25 -07:00
|
|
|
{
|
2009-08-25 04:15:50 -06:00
|
|
|
uint32_t old_write_domain, old_read_domains;
|
2008-11-14 14:35:19 -07:00
|
|
|
int ret;
|
2008-11-10 11:53:25 -07:00
|
|
|
|
2008-11-26 14:58:13 -07:00
|
|
|
/* Not valid to be called on unbound objects. */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->gtt_space == NULL)
|
2008-11-26 14:58:13 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2011-02-07 08:23:02 -07:00
|
|
|
if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
|
|
|
|
return 0;
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
ret = i915_gem_object_flush_gpu_write_domain(obj);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-12-02 02:42:56 -07:00
|
|
|
if (obj->pending_gpu_write || write) {
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_wait_rendering(obj);
|
2010-12-02 02:42:56 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2010-06-07 07:03:05 -06:00
|
|
|
|
2010-09-13 16:56:38 -06:00
|
|
|
i915_gem_object_flush_cpu_write_domain(obj);
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
old_write_domain = obj->base.write_domain;
|
|
|
|
old_read_domains = obj->base.read_domains;
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/* It should now be out of any other write domains, and we can update
|
|
|
|
* the domain values for our changes.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
|
|
|
|
obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
|
2008-11-14 14:35:19 -07:00
|
|
|
if (write) {
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains = I915_GEM_DOMAIN_GTT;
|
|
|
|
obj->base.write_domain = I915_GEM_DOMAIN_GTT;
|
|
|
|
obj->dirty = 1;
|
2008-11-10 11:53:25 -07:00
|
|
|
}
|
|
|
|
|
2009-08-25 04:15:50 -06:00
|
|
|
trace_i915_gem_object_change_domain(obj,
|
|
|
|
old_read_domains,
|
|
|
|
old_write_domain);
|
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-04-04 02:44:39 -06:00
|
|
|
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
|
|
|
|
enum i915_cache_level cache_level)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (obj->cache_level == cache_level)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (obj->pin_count) {
|
|
|
|
DRM_DEBUG("can not change the cache level of pinned objects\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (obj->gtt_space) {
|
|
|
|
ret = i915_gem_object_finish_gpu(obj);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
i915_gem_object_finish_gtt(obj);
|
|
|
|
|
|
|
|
/* Before SandyBridge, you could not use tiling or fence
|
|
|
|
* registers with snooped memory, so relinquish any fences
|
|
|
|
* currently pointing to our region in the aperture.
|
|
|
|
*/
|
|
|
|
if (INTEL_INFO(obj->base.dev)->gen < 6) {
|
|
|
|
ret = i915_gem_object_put_fence(obj);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
i915_gem_gtt_rebind_object(obj, cache_level);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cache_level == I915_CACHE_NONE) {
|
|
|
|
u32 old_read_domains, old_write_domain;
|
|
|
|
|
|
|
|
/* If we're coming from LLC cached, then we haven't
|
|
|
|
* actually been tracking whether the data is in the
|
|
|
|
* CPU cache or not, since we only allow one bit set
|
|
|
|
* in obj->write_domain and have been skipping the clflushes.
|
|
|
|
* Just set it to the CPU cache for now.
|
|
|
|
*/
|
|
|
|
WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
|
|
|
|
WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
|
|
|
|
|
|
|
|
old_read_domains = obj->base.read_domains;
|
|
|
|
old_write_domain = obj->base.write_domain;
|
|
|
|
|
|
|
|
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
|
|
|
|
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
|
|
|
|
|
|
|
|
trace_i915_gem_object_change_domain(obj,
|
|
|
|
old_read_domains,
|
|
|
|
old_write_domain);
|
|
|
|
}
|
|
|
|
|
|
|
|
obj->cache_level = cache_level;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-24 22:09:39 -07:00
|
|
|
/*
|
2011-04-14 02:41:17 -06:00
|
|
|
* Prepare buffer for display plane (scanout, cursors, etc).
|
|
|
|
* Can be called from an uninterruptible phase (modesetting) and allows
|
|
|
|
* any flushes to be pipelined (for pageflips).
|
|
|
|
*
|
|
|
|
* For the display plane, we want to be in the GTT but out of any write
|
|
|
|
* domains. So in many ways this looks like set_to_gtt_domain() apart from the
|
|
|
|
* ability to pipeline the waits, pinning and any additional subtleties
|
|
|
|
* that may differentiate the display plane from ordinary buffers.
|
2009-11-24 22:09:39 -07:00
|
|
|
*/
|
|
|
|
int
|
2011-04-14 02:41:17 -06:00
|
|
|
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
|
|
|
|
u32 alignment,
|
2010-11-12 06:42:53 -07:00
|
|
|
struct intel_ring_buffer *pipelined)
|
2009-11-24 22:09:39 -07:00
|
|
|
{
|
2011-04-14 02:41:17 -06:00
|
|
|
u32 old_read_domains, old_write_domain;
|
2009-11-24 22:09:39 -07:00
|
|
|
int ret;
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
ret = i915_gem_object_flush_gpu_write_domain(obj);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-12-06 07:36:27 -07:00
|
|
|
if (pipelined != obj->ring) {
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_wait_rendering(obj);
|
2011-07-19 17:21:40 -06:00
|
|
|
if (ret == -ERESTARTSYS)
|
2009-11-24 22:09:39 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-03-29 17:59:54 -06:00
|
|
|
/* The display engine is not coherent with the LLC cache on gen6. As
|
|
|
|
* a result, we make sure that the pinning that is about to occur is
|
|
|
|
* done with uncached PTEs. This is lowest common denominator for all
|
|
|
|
* chipsets.
|
|
|
|
*
|
|
|
|
* However for gen6+, we could do better by using the GFDT bit instead
|
|
|
|
* of uncaching, which would allow us to flush all the LLC-cached data
|
|
|
|
* with that bit in the PTE to main memory with just one PIPE_CONTROL.
|
|
|
|
*/
|
|
|
|
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-04-14 02:41:17 -06:00
|
|
|
/* As the user may map the buffer once pinned in the display plane
|
|
|
|
* (e.g. libkms for the bootup splash), we have to ensure that we
|
|
|
|
* always use map_and_fenceable for all scanout buffers.
|
|
|
|
*/
|
|
|
|
ret = i915_gem_object_pin(obj, alignment, true);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-05-27 06:18:14 -06:00
|
|
|
i915_gem_object_flush_cpu_write_domain(obj);
|
|
|
|
|
2011-04-14 02:41:17 -06:00
|
|
|
old_write_domain = obj->base.write_domain;
|
2010-11-08 12:18:58 -07:00
|
|
|
old_read_domains = obj->base.read_domains;
|
2011-04-14 02:41:17 -06:00
|
|
|
|
|
|
|
/* It should now be out of any other write domains, and we can update
|
|
|
|
* the domain values for our changes.
|
|
|
|
*/
|
|
|
|
BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
|
2009-11-24 22:09:39 -07:00
|
|
|
|
|
|
|
trace_i915_gem_object_change_domain(obj,
|
|
|
|
old_read_domains,
|
2011-04-14 02:41:17 -06:00
|
|
|
old_write_domain);
|
2009-11-24 22:09:39 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-11-13 02:49:11 -07:00
|
|
|
int
|
2011-04-13 15:04:09 -06:00
|
|
|
i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
|
2010-11-13 02:49:11 -07:00
|
|
|
{
|
2011-01-07 10:09:48 -07:00
|
|
|
int ret;
|
|
|
|
|
2011-04-13 15:04:09 -06:00
|
|
|
if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
|
2010-11-13 02:49:11 -07:00
|
|
|
return 0;
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
|
2011-01-07 10:09:48 -07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2010-11-13 02:49:11 -07:00
|
|
|
|
2011-04-13 15:04:09 -06:00
|
|
|
/* Ensure that we invalidate the GPU's caches and TLBs. */
|
|
|
|
obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
|
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
return i915_gem_object_wait_rendering(obj);
|
2010-11-13 02:49:11 -07:00
|
|
|
}
|
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/**
|
|
|
|
* Moves a single object to the CPU read, and possibly write domain.
|
|
|
|
*
|
|
|
|
* This function returns when the move is complete, including waiting on
|
|
|
|
* flushes to occur.
|
|
|
|
*/
|
|
|
|
static int
|
2010-11-12 06:42:53 -07:00
|
|
|
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
|
2008-11-14 14:35:19 -07:00
|
|
|
{
|
2009-08-25 04:15:50 -06:00
|
|
|
uint32_t old_write_domain, old_read_domains;
|
2008-11-14 14:35:19 -07:00
|
|
|
int ret;
|
|
|
|
|
2011-02-07 08:23:02 -07:00
|
|
|
if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
|
|
|
|
return 0;
|
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
ret = i915_gem_object_flush_gpu_write_domain(obj);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_wait_rendering(obj);
|
2010-11-27 14:30:41 -07:00
|
|
|
if (ret)
|
2008-11-14 14:35:19 -07:00
|
|
|
return ret;
|
2008-11-10 11:53:25 -07:00
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
i915_gem_object_flush_gtt_write_domain(obj);
|
2008-11-10 11:53:25 -07:00
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/* If we have a partially-valid cache of the object in the CPU,
|
|
|
|
* finish invalidating it and free the per-page flags.
|
2008-11-10 11:53:25 -07:00
|
|
|
*/
|
2008-11-14 14:35:19 -07:00
|
|
|
i915_gem_object_set_to_full_cpu_read_domain(obj);
|
2008-11-10 11:53:25 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
old_write_domain = obj->base.write_domain;
|
|
|
|
old_read_domains = obj->base.read_domains;
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/* Flush the CPU cache if it's still invalid. */
|
2010-11-08 12:18:58 -07:00
|
|
|
if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
|
2008-11-10 11:53:25 -07:00
|
|
|
i915_gem_clflush_object(obj);
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
|
2008-11-10 11:53:25 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* It should now be out of any other write domains, and we can update
|
|
|
|
* the domain values for our changes.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
|
2008-11-14 14:35:19 -07:00
|
|
|
|
|
|
|
/* If we're writing through the CPU, then the GPU read domains will
|
|
|
|
* need to be invalidated at next use.
|
|
|
|
*/
|
|
|
|
if (write) {
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
|
|
|
|
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
|
2008-11-14 14:35:19 -07:00
|
|
|
}
|
2008-11-10 11:53:25 -07:00
|
|
|
|
2009-08-25 04:15:50 -06:00
|
|
|
trace_i915_gem_object_change_domain(obj,
|
|
|
|
old_read_domains,
|
|
|
|
old_write_domain);
|
|
|
|
|
2008-11-10 11:53:25 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
/**
|
2008-11-14 14:35:19 -07:00
|
|
|
* Moves the object from a partially CPU read to a full one.
|
2008-07-30 13:06:12 -06:00
|
|
|
*
|
2008-11-14 14:35:19 -07:00
|
|
|
* Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
|
|
|
|
* and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
|
2008-07-30 13:06:12 -06:00
|
|
|
*/
|
2008-11-14 14:35:19 -07:00
|
|
|
static void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
if (!obj->page_cpu_valid)
|
2008-11-14 14:35:19 -07:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* If we're partially in the CPU read domain, finish moving it in.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
|
2008-11-14 14:35:19 -07:00
|
|
|
int i;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
|
|
|
|
if (obj->page_cpu_valid[i])
|
2008-11-14 14:35:19 -07:00
|
|
|
continue;
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_clflush_pages(obj->pages + i, 1);
|
2008-11-14 14:35:19 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Free the page_cpu_valid mappings which are now stale, whether
|
|
|
|
* or not we've got I915_GEM_DOMAIN_CPU.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
kfree(obj->page_cpu_valid);
|
|
|
|
obj->page_cpu_valid = NULL;
|
2008-11-14 14:35:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Set the CPU read domain on a range of the object.
|
|
|
|
*
|
|
|
|
* The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
|
|
|
|
* not entirely valid. The page_cpu_valid member of the object flags which
|
|
|
|
* pages have been flushed, and will be respected by
|
|
|
|
* i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
|
|
|
|
* of the whole object.
|
|
|
|
*
|
|
|
|
* This function returns when the move is complete, including waiting on
|
|
|
|
* flushes to occur.
|
|
|
|
*/
|
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
|
2008-11-14 14:35:19 -07:00
|
|
|
uint64_t offset, uint64_t size)
|
|
|
|
{
|
2009-08-25 04:15:50 -06:00
|
|
|
uint32_t old_read_domains;
|
2008-11-14 14:35:19 -07:00
|
|
|
int i, ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (offset == 0 && size == obj->base.size)
|
2008-11-14 14:35:19 -07:00
|
|
|
return i915_gem_object_set_to_cpu_domain(obj, 0);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-01-07 10:09:48 -07:00
|
|
|
ret = i915_gem_object_flush_gpu_write_domain(obj);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
ret = i915_gem_object_wait_rendering(obj);
|
2010-11-27 14:30:41 -07:00
|
|
|
if (ret)
|
2008-11-03 15:38:17 -07:00
|
|
|
return ret;
|
2010-11-27 14:30:41 -07:00
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
i915_gem_object_flush_gtt_write_domain(obj);
|
|
|
|
|
|
|
|
/* If we're already fully in the CPU read domain, we're done. */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->page_cpu_valid == NULL &&
|
|
|
|
(obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
|
2008-11-14 14:35:19 -07:00
|
|
|
return 0;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/* Otherwise, create/clear the per-page CPU read domain flag if we're
|
|
|
|
* newly adding I915_GEM_DOMAIN_CPU
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->page_cpu_valid == NULL) {
|
|
|
|
obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (obj->page_cpu_valid == NULL)
|
2008-11-14 14:35:19 -07:00
|
|
|
return -ENOMEM;
|
2010-11-08 12:18:58 -07:00
|
|
|
} else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
|
|
|
|
memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
|
|
|
/* Flush the cache on any pages that are still invalid from the CPU's
|
|
|
|
* perspective.
|
|
|
|
*/
|
2008-11-14 14:35:19 -07:00
|
|
|
for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
|
|
|
|
i++) {
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->page_cpu_valid[i])
|
2008-07-30 13:06:12 -06:00
|
|
|
continue;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_clflush_pages(obj->pages + i, 1);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->page_cpu_valid[i] = 1;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2008-11-14 14:35:19 -07:00
|
|
|
/* It should now be out of any other write domains, and we can update
|
|
|
|
* the domain values for our changes.
|
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
|
2008-11-14 14:35:19 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
old_read_domains = obj->base.read_domains;
|
|
|
|
obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
|
2008-11-14 14:35:19 -07:00
|
|
|
|
2009-08-25 04:15:50 -06:00
|
|
|
trace_i915_gem_object_change_domain(obj,
|
|
|
|
old_read_domains,
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.write_domain);
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Throttle our rendering by waiting until the ring has completed our requests
|
|
|
|
* emitted over 20 msec ago.
|
|
|
|
*
|
2009-06-03 01:27:35 -06:00
|
|
|
* Note that if we were to use the current jiffies each time around the loop,
|
|
|
|
* we wouldn't escape the function with any frames outstanding if the time to
|
|
|
|
* render a frame was over 20ms.
|
|
|
|
*
|
2008-07-30 13:06:12 -06:00
|
|
|
* This should get us reasonable parallelism between CPU and GPU but also
|
|
|
|
* relatively low latency when blocking on a particular request to finish.
|
|
|
|
*/
|
2009-03-12 12:23:52 -06:00
|
|
|
static int
|
2010-09-24 09:02:42 -06:00
|
|
|
i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
|
2009-03-12 12:23:52 -06:00
|
|
|
{
|
2010-09-24 09:02:42 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
2009-06-03 01:27:35 -06:00
|
|
|
unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
|
2010-09-24 09:02:42 -06:00
|
|
|
struct drm_i915_gem_request *request;
|
|
|
|
struct intel_ring_buffer *ring = NULL;
|
|
|
|
u32 seqno = 0;
|
|
|
|
int ret;
|
2010-01-31 03:40:48 -07:00
|
|
|
|
2011-01-26 08:39:14 -07:00
|
|
|
if (atomic_read(&dev_priv->mm.wedged))
|
|
|
|
return -EIO;
|
|
|
|
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_lock(&file_priv->mm.lock);
|
2010-09-24 09:02:42 -06:00
|
|
|
list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
|
2009-06-03 01:27:35 -06:00
|
|
|
if (time_after_eq(request->emitted_jiffies, recent_enough))
|
|
|
|
break;
|
2009-03-12 12:23:52 -06:00
|
|
|
|
2010-09-24 09:02:42 -06:00
|
|
|
ring = request->ring;
|
|
|
|
seqno = request->seqno;
|
2009-06-03 01:27:35 -06:00
|
|
|
}
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_unlock(&file_priv->mm.lock);
|
2009-03-12 12:23:52 -06:00
|
|
|
|
2010-09-24 09:02:42 -06:00
|
|
|
if (seqno == 0)
|
|
|
|
return 0;
|
2009-04-06 14:55:41 -06:00
|
|
|
|
2010-09-24 09:02:42 -06:00
|
|
|
ret = 0;
|
2010-10-27 05:18:21 -06:00
|
|
|
if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
|
2010-09-24 09:02:42 -06:00
|
|
|
/* And wait for the seqno passing without holding any locks and
|
|
|
|
* causing extra latency for others. This is safe as the irq
|
|
|
|
* generation is designed to be run atomically and so is
|
|
|
|
* lockless.
|
|
|
|
*/
|
2010-12-13 09:54:50 -07:00
|
|
|
if (ring->irq_get(ring)) {
|
|
|
|
ret = wait_event_interruptible(ring->irq_queue,
|
|
|
|
i915_seqno_passed(ring->get_seqno(ring), seqno)
|
|
|
|
|| atomic_read(&dev_priv->mm.wedged));
|
|
|
|
ring->irq_put(ring);
|
2009-03-12 12:23:52 -06:00
|
|
|
|
2010-12-13 09:54:50 -07:00
|
|
|
if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
|
|
|
|
ret = -EIO;
|
|
|
|
}
|
2009-03-12 12:23:52 -06:00
|
|
|
}
|
|
|
|
|
2010-09-24 09:02:42 -06:00
|
|
|
if (ret == 0)
|
|
|
|
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
|
2009-03-12 12:23:52 -06:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_pin(struct drm_i915_gem_object *obj,
|
|
|
|
uint32_t alignment,
|
2010-11-04 10:11:09 -06:00
|
|
|
bool map_and_fenceable)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2010-09-20 10:36:15 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-07-30 13:06:12 -06:00
|
|
|
int ret;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
|
2010-09-29 09:10:57 -06:00
|
|
|
WARN_ON(i915_verify_lists(dev));
|
2010-05-27 06:18:18 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->gtt_space != NULL) {
|
|
|
|
if ((alignment && obj->gtt_offset & (alignment - 1)) ||
|
|
|
|
(map_and_fenceable && !obj->map_and_fenceable)) {
|
|
|
|
WARN(obj->pin_count,
|
2010-08-04 05:37:41 -06:00
|
|
|
"bo is already pinned with incorrect alignment:"
|
2010-11-04 10:11:09 -06:00
|
|
|
" offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
|
|
|
|
" obj->map_and_fenceable=%d\n",
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->gtt_offset, alignment,
|
2010-11-04 10:11:09 -06:00
|
|
|
map_and_fenceable,
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->map_and_fenceable);
|
2010-05-27 06:18:18 -06:00
|
|
|
ret = i915_gem_object_unbind(obj);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->gtt_space == NULL) {
|
2010-09-24 14:15:47 -06:00
|
|
|
ret = i915_gem_object_bind_to_gtt(obj, alignment,
|
2010-11-04 10:11:09 -06:00
|
|
|
map_and_fenceable);
|
2009-09-20 17:22:34 -06:00
|
|
|
if (ret)
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
2009-02-11 07:26:45 -07:00
|
|
|
}
|
2009-12-17 20:05:42 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->pin_count++ == 0) {
|
|
|
|
if (!obj->active)
|
|
|
|
list_move_tail(&obj->mm_list,
|
2010-09-20 10:36:15 -06:00
|
|
|
&dev_priv->mm.pinned_list);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
2010-11-24 05:23:44 -07:00
|
|
|
obj->pin_mappable |= map_and_fenceable;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-09-29 09:10:57 -06:00
|
|
|
WARN_ON(i915_verify_lists(dev));
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_object_unpin(struct drm_i915_gem_object *obj)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2008-07-30 13:06:12 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
2010-09-29 09:10:57 -06:00
|
|
|
WARN_ON(i915_verify_lists(dev));
|
2010-11-08 12:18:58 -07:00
|
|
|
BUG_ON(obj->pin_count == 0);
|
|
|
|
BUG_ON(obj->gtt_space == NULL);
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (--obj->pin_count == 0) {
|
|
|
|
if (!obj->active)
|
|
|
|
list_move_tail(&obj->mm_list,
|
2008-07-30 13:06:12 -06:00
|
|
|
&dev_priv->mm.inactive_list);
|
2010-11-24 05:23:44 -07:00
|
|
|
obj->pin_mappable = false;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
2010-09-29 09:10:57 -06:00
|
|
|
WARN_ON(i915_verify_lists(dev));
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
i915_gem_pin_ioctl(struct drm_device *dev, void *data,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_pin *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2008-07-30 13:06:12 -06:00
|
|
|
int ret;
|
|
|
|
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->madv != I915_MADV_WILLNEED) {
|
2009-09-22 07:24:13 -06:00
|
|
|
DRM_ERROR("Attempting to pin a purgeable buffer\n");
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
2009-09-14 09:50:29 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->pin_filp != NULL && obj->pin_filp != file) {
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
|
|
|
|
args->handle);
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->user_pin_count++;
|
|
|
|
obj->pin_filp = file;
|
|
|
|
if (obj->user_pin_count == 1) {
|
2010-11-04 10:11:09 -06:00
|
|
|
ret = i915_gem_object_pin(obj, args->alignment, true);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX - flush the CPU caches for pinned objects
|
|
|
|
* as the X server doesn't manage domains yet
|
|
|
|
*/
|
2008-11-14 14:35:19 -07:00
|
|
|
i915_gem_object_flush_cpu_write_domain(obj);
|
2010-11-08 12:18:58 -07:00
|
|
|
args->offset = obj->gtt_offset;
|
2010-10-17 02:45:41 -06:00
|
|
|
out:
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2008-07-30 13:06:12 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-10-17 02:45:41 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_pin *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-25 04:22:51 -06:00
|
|
|
int ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
2010-09-25 04:22:51 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->pin_filp != file) {
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
|
|
|
|
args->handle);
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
}
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->user_pin_count--;
|
|
|
|
if (obj->user_pin_count == 0) {
|
|
|
|
obj->pin_filp = NULL;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
i915_gem_object_unpin(obj);
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-10-17 02:45:41 -06:00
|
|
|
out:
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2008-07-30 13:06:12 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-10-17 02:45:41 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
i915_gem_busy_ioctl(struct drm_device *dev, void *data,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_file *file)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_busy *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-25 03:19:17 -06:00
|
|
|
int ret;
|
|
|
|
|
2010-09-25 04:22:51 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
2010-10-17 02:45:41 -06:00
|
|
|
if (ret)
|
2010-09-25 04:22:51 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
2010-05-20 19:08:57 -06:00
|
|
|
|
2010-08-04 08:36:30 -06:00
|
|
|
/* Count all active objects as busy, even if they are currently not used
|
|
|
|
* by the gpu. Users of this interface expect objects to eventually
|
|
|
|
* become non-busy without any further actions, therefore emit any
|
|
|
|
* necessary flushes here.
|
2008-12-14 20:05:04 -07:00
|
|
|
*/
|
2010-11-08 12:18:58 -07:00
|
|
|
args->busy = obj->active;
|
2010-08-04 08:36:30 -06:00
|
|
|
if (args->busy) {
|
|
|
|
/* Unconditionally flush objects, even when the gpu still uses this
|
|
|
|
* object. Userspace calling this function indicates that it wants to
|
|
|
|
* use this buffer rather sooner than later, so issuing the required
|
|
|
|
* flush earlier is beneficial.
|
|
|
|
*/
|
2010-12-07 16:00:20 -07:00
|
|
|
if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
|
2011-02-03 04:57:46 -07:00
|
|
|
ret = i915_gem_flush_ring(obj->ring,
|
2011-01-07 10:09:48 -07:00
|
|
|
0, obj->base.write_domain);
|
2010-12-07 16:00:20 -07:00
|
|
|
} else if (obj->ring->outstanding_lazy_request ==
|
|
|
|
obj->last_rendering_seqno) {
|
|
|
|
struct drm_i915_gem_request *request;
|
|
|
|
|
2010-12-07 03:38:40 -07:00
|
|
|
/* This ring is not being cleared by active usage,
|
|
|
|
* so emit a request to do so.
|
|
|
|
*/
|
2010-12-07 16:00:20 -07:00
|
|
|
request = kzalloc(sizeof(*request), GFP_KERNEL);
|
2011-11-15 11:49:28 -07:00
|
|
|
if (request) {
|
2011-08-16 13:34:10 -06:00
|
|
|
ret = i915_add_request(obj->ring, NULL, request);
|
2011-11-15 11:49:28 -07:00
|
|
|
if (ret)
|
|
|
|
kfree(request);
|
|
|
|
} else
|
2010-12-07 03:38:40 -07:00
|
|
|
ret = -ENOMEM;
|
|
|
|
}
|
2010-08-04 08:36:30 -06:00
|
|
|
|
|
|
|
/* Update the active list for the hardware's current position.
|
|
|
|
* Otherwise this only updates on a delayed timer or when irqs
|
|
|
|
* are actually unmasked, and our working set ends up being
|
|
|
|
* larger than required.
|
|
|
|
*/
|
2011-02-03 04:57:46 -07:00
|
|
|
i915_gem_retire_requests_ring(obj->ring);
|
2010-08-04 08:36:30 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
args->busy = obj->active;
|
2010-08-04 08:36:30 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2008-07-30 13:06:12 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-10-17 02:45:41 -06:00
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
2011-08-16 13:34:10 -06:00
|
|
|
return i915_gem_ring_throttle(dev, file_priv);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2009-09-14 09:50:29 -06:00
|
|
|
int
|
|
|
|
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_madvise *args = data;
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-25 04:22:51 -06:00
|
|
|
int ret;
|
2009-09-14 09:50:29 -06:00
|
|
|
|
|
|
|
switch (args->madv) {
|
|
|
|
case I915_MADV_DONTNEED:
|
|
|
|
case I915_MADV_WILLNEED:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
|
2011-02-19 04:31:06 -07:00
|
|
|
if (&obj->base == NULL) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
2009-09-14 09:50:29 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->pin_count) {
|
2010-10-17 02:45:41 -06:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
2009-09-14 09:50:29 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->madv != __I915_MADV_PURGED)
|
|
|
|
obj->madv = args->madv;
|
2009-09-14 09:50:29 -06:00
|
|
|
|
2009-09-20 16:13:10 -06:00
|
|
|
/* if the object is no longer bound, discard its backing storage */
|
2010-11-08 12:18:58 -07:00
|
|
|
if (i915_gem_object_is_purgeable(obj) &&
|
|
|
|
obj->gtt_space == NULL)
|
2009-09-20 16:13:10 -06:00
|
|
|
i915_gem_object_truncate(obj);
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
args->retained = obj->madv != __I915_MADV_PURGED;
|
2009-09-22 07:24:13 -06:00
|
|
|
|
2010-10-17 02:45:41 -06:00
|
|
|
out:
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_unreference(&obj->base);
|
2010-10-17 02:45:41 -06:00
|
|
|
unlock:
|
2009-09-14 09:50:29 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-10-17 02:45:41 -06:00
|
|
|
return ret;
|
2009-09-14 09:50:29 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
|
|
|
|
size_t size)
|
2010-04-09 13:05:06 -06:00
|
|
|
{
|
2010-09-30 04:46:12 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-04-09 13:05:07 -06:00
|
|
|
struct drm_i915_gem_object *obj;
|
2011-06-27 17:18:18 -06:00
|
|
|
struct address_space *mapping;
|
2010-04-09 13:05:06 -06:00
|
|
|
|
2010-04-09 13:05:07 -06:00
|
|
|
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
|
|
|
|
if (obj == NULL)
|
|
|
|
return NULL;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-04-09 13:05:07 -06:00
|
|
|
if (drm_gem_object_init(dev, &obj->base, size) != 0) {
|
|
|
|
kfree(obj);
|
|
|
|
return NULL;
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-06-27 17:18:18 -06:00
|
|
|
mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
|
|
|
|
mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
|
|
|
|
|
2010-09-30 04:46:12 -06:00
|
|
|
i915_gem_info_add_obj(dev_priv, size);
|
|
|
|
|
2010-04-09 13:05:07 -06:00
|
|
|
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
|
|
|
|
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-11-03 15:15:13 -06:00
|
|
|
if (IS_GEN6(dev) || IS_GEN7(dev)) {
|
2011-03-29 17:59:55 -06:00
|
|
|
/* On Gen6, we can have the GPU use the LLC (the CPU
|
|
|
|
* cache) for about a 10% performance improvement
|
|
|
|
* compared to uncached. Graphics requests other than
|
|
|
|
* display scanout are coherent with the CPU in
|
|
|
|
* accessing this cache. This means in this mode we
|
|
|
|
* don't need to clflush on the CPU side, and on the
|
|
|
|
* GPU side we only need to flush internal caches to
|
|
|
|
* get data visible to the CPU.
|
|
|
|
*
|
|
|
|
* However, we maintain the display planes as UC, and so
|
|
|
|
* need to rebind when first used as such.
|
|
|
|
*/
|
|
|
|
obj->cache_level = I915_CACHE_LLC;
|
|
|
|
} else
|
|
|
|
obj->cache_level = I915_CACHE_NONE;
|
|
|
|
|
2010-04-09 13:05:08 -06:00
|
|
|
obj->base.driver_private = NULL;
|
2010-04-09 13:05:07 -06:00
|
|
|
obj->fence_reg = I915_FENCE_REG_NONE;
|
2010-10-19 03:36:51 -06:00
|
|
|
INIT_LIST_HEAD(&obj->mm_list);
|
2010-11-05 13:24:53 -06:00
|
|
|
INIT_LIST_HEAD(&obj->gtt_list);
|
2010-10-19 03:36:51 -06:00
|
|
|
INIT_LIST_HEAD(&obj->ring_list);
|
2010-11-25 12:32:06 -07:00
|
|
|
INIT_LIST_HEAD(&obj->exec_list);
|
2010-04-09 13:05:07 -06:00
|
|
|
INIT_LIST_HEAD(&obj->gpu_write_list);
|
|
|
|
obj->madv = I915_MADV_WILLNEED;
|
2010-11-04 10:11:09 -06:00
|
|
|
/* Avoid an unnecessary call to unbind on the first bind. */
|
|
|
|
obj->map_and_fenceable = true;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
return obj;
|
2010-04-09 13:05:07 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int i915_gem_init_object(struct drm_gem_object *obj)
|
|
|
|
{
|
|
|
|
BUG();
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
|
2008-07-30 13:06:12 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_device *dev = obj->base.dev;
|
2010-07-23 16:18:50 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-07-23 16:18:50 -06:00
|
|
|
ret = i915_gem_object_unbind(obj);
|
|
|
|
if (ret == -ERESTARTSYS) {
|
2010-11-08 12:18:58 -07:00
|
|
|
list_move(&obj->mm_list,
|
2010-07-23 16:18:50 -06:00
|
|
|
&dev_priv->mm.deferred_free_list);
|
|
|
|
return;
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2011-03-20 05:20:19 -06:00
|
|
|
trace_i915_gem_object_destroy(obj);
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->base.map_list.map)
|
2011-08-10 07:09:08 -06:00
|
|
|
drm_gem_free_mmap_offset(&obj->base);
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
drm_gem_object_release(&obj->base);
|
|
|
|
i915_gem_info_remove_obj(dev_priv, obj->base.size);
|
2010-04-09 13:05:07 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
kfree(obj->page_cpu_valid);
|
|
|
|
kfree(obj->bit_17);
|
|
|
|
kfree(obj);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
void i915_gem_free_object(struct drm_gem_object *gem_obj)
|
2010-07-23 16:18:50 -06:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
|
|
|
|
struct drm_device *dev = obj->base.dev;
|
2010-07-23 16:18:50 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
while (obj->pin_count > 0)
|
2010-07-23 16:18:50 -06:00
|
|
|
i915_gem_object_unpin(obj);
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->phys_obj)
|
2010-07-23 16:18:50 -06:00
|
|
|
i915_gem_detach_phys_object(dev, obj);
|
|
|
|
|
|
|
|
i915_gem_free_object_tail(obj);
|
|
|
|
}
|
|
|
|
|
2010-01-07 03:39:13 -07:00
|
|
|
int
|
|
|
|
i915_gem_idle(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
2008-11-13 16:00:55 -07:00
|
|
|
|
2010-01-07 03:39:13 -07:00
|
|
|
mutex_lock(&dev->struct_mutex);
|
2009-08-25 04:15:50 -06:00
|
|
|
|
2010-10-19 03:13:00 -06:00
|
|
|
if (dev_priv->mm.suspended) {
|
2010-01-07 03:39:13 -07:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return 0;
|
2008-11-13 16:00:55 -07:00
|
|
|
}
|
|
|
|
|
2010-01-07 03:39:13 -07:00
|
|
|
ret = i915_gpu_idle(dev);
|
2008-10-14 22:41:13 -06:00
|
|
|
if (ret) {
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2008-07-30 13:06:12 -06:00
|
|
|
return ret;
|
2008-10-14 22:41:13 -06:00
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
|
2010-01-07 03:39:13 -07:00
|
|
|
/* Under UMS, be paranoid and evict. */
|
|
|
|
if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
|
2010-10-31 02:49:47 -06:00
|
|
|
ret = i915_gem_evict_inactive(dev, false);
|
2010-01-07 03:39:13 -07:00
|
|
|
if (ret) {
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-22 04:50:11 -07:00
|
|
|
i915_gem_reset_fences(dev);
|
|
|
|
|
2010-01-07 03:39:13 -07:00
|
|
|
/* Hack! Don't let anybody do execbuf while we don't control the chip.
|
|
|
|
* We need to replace this with a semaphore, or something.
|
|
|
|
* And not confound mm.suspended!
|
|
|
|
*/
|
|
|
|
dev_priv->mm.suspended = 1;
|
2010-08-20 10:18:48 -06:00
|
|
|
del_timer_sync(&dev_priv->hangcheck_timer);
|
2010-01-07 03:39:13 -07:00
|
|
|
|
|
|
|
i915_kernel_lost_context(dev);
|
2008-10-14 22:41:13 -06:00
|
|
|
i915_gem_cleanup_ringbuffer(dev);
|
2010-01-07 03:39:13 -07:00
|
|
|
|
2008-10-14 22:41:13 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2010-01-07 03:39:13 -07:00
|
|
|
/* Cancel the retire work handler, which should be idle now. */
|
|
|
|
cancel_delayed_work_sync(&dev_priv->mm.retire_work);
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
int
|
|
|
|
i915_gem_init_ringbuffer(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
2010-05-27 06:18:22 -06:00
|
|
|
|
2010-09-15 20:43:11 -06:00
|
|
|
ret = intel_init_render_ring_buffer(dev);
|
2010-05-27 06:18:22 -06:00
|
|
|
if (ret)
|
2010-11-12 03:46:37 -07:00
|
|
|
return ret;
|
2010-05-27 06:18:22 -06:00
|
|
|
|
|
|
|
if (HAS_BSD(dev)) {
|
2010-09-15 20:43:11 -06:00
|
|
|
ret = intel_init_bsd_ring_buffer(dev);
|
2010-05-27 06:18:22 -06:00
|
|
|
if (ret)
|
|
|
|
goto cleanup_render_ring;
|
2010-05-20 19:08:57 -06:00
|
|
|
}
|
2010-05-27 06:18:22 -06:00
|
|
|
|
2010-10-19 04:19:32 -06:00
|
|
|
if (HAS_BLT(dev)) {
|
|
|
|
ret = intel_init_blt_ring_buffer(dev);
|
|
|
|
if (ret)
|
|
|
|
goto cleanup_bsd_ring;
|
|
|
|
}
|
|
|
|
|
2010-08-07 04:01:22 -06:00
|
|
|
dev_priv->next_seqno = 1;
|
|
|
|
|
2010-05-27 06:18:22 -06:00
|
|
|
return 0;
|
|
|
|
|
2010-10-19 04:19:32 -06:00
|
|
|
cleanup_bsd_ring:
|
2010-12-04 04:30:53 -07:00
|
|
|
intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
|
2010-05-27 06:18:22 -06:00
|
|
|
cleanup_render_ring:
|
2010-12-04 04:30:53 -07:00
|
|
|
intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
|
2010-05-20 19:08:55 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-12-04 04:30:53 -07:00
|
|
|
int i;
|
2010-05-20 19:08:55 -06:00
|
|
|
|
2010-12-04 04:30:53 -07:00
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++)
|
|
|
|
intel_cleanup_ring_buffer(&dev_priv->ring[i]);
|
2010-05-20 19:08:55 -06:00
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
int
|
|
|
|
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-12-04 04:30:53 -07:00
|
|
|
int ret, i;
|
2008-07-30 13:06:12 -06:00
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
|
|
|
return 0;
|
|
|
|
|
2009-09-14 15:48:47 -06:00
|
|
|
if (atomic_read(&dev_priv->mm.wedged)) {
|
2008-07-30 13:06:12 -06:00
|
|
|
DRM_ERROR("Reenabling wedged hardware, good luck\n");
|
2009-09-14 15:48:47 -06:00
|
|
|
atomic_set(&dev_priv->mm.wedged, 0);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
2008-12-23 19:42:32 -07:00
|
|
|
dev_priv->mm.suspended = 0;
|
|
|
|
|
|
|
|
ret = i915_gem_init_ringbuffer(dev);
|
2009-04-17 20:43:32 -06:00
|
|
|
if (ret != 0) {
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2008-12-23 19:42:32 -07:00
|
|
|
return ret;
|
2009-04-17 20:43:32 -06:00
|
|
|
}
|
2008-12-23 19:42:32 -07:00
|
|
|
|
2010-10-19 03:36:51 -06:00
|
|
|
BUG_ON(!list_empty(&dev_priv->mm.active_list));
|
2008-07-30 13:06:12 -06:00
|
|
|
BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
|
|
|
|
BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
|
2010-12-04 04:30:53 -07:00
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++) {
|
|
|
|
BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
|
|
|
|
BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
|
|
|
|
}
|
2008-07-30 13:06:12 -06:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2008-08-20 09:04:27 -06:00
|
|
|
|
2010-06-07 07:03:03 -06:00
|
|
|
ret = drm_irq_install(dev);
|
|
|
|
if (ret)
|
|
|
|
goto cleanup_ringbuffer;
|
2008-08-20 09:04:27 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
return 0;
|
2010-06-07 07:03:03 -06:00
|
|
|
|
|
|
|
cleanup_ringbuffer:
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
i915_gem_cleanup_ringbuffer(dev);
|
|
|
|
dev_priv->mm.suspended = 1;
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return ret;
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 15:24:08 -07:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
|
|
|
return 0;
|
|
|
|
|
2008-08-20 09:04:27 -06:00
|
|
|
drm_irq_uninstall(dev);
|
2009-09-08 18:09:24 -06:00
|
|
|
return i915_gem_idle(dev);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
i915_gem_lastclose(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2009-01-22 10:56:58 -07:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
|
|
|
return;
|
|
|
|
|
2008-10-14 22:41:13 -06:00
|
|
|
ret = i915_gem_idle(dev);
|
|
|
|
if (ret)
|
|
|
|
DRM_ERROR("failed to idle hardware: %d\n", ret);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
|
|
|
|
2010-10-24 05:38:05 -06:00
|
|
|
static void
|
|
|
|
init_ring_lists(struct intel_ring_buffer *ring)
|
|
|
|
{
|
|
|
|
INIT_LIST_HEAD(&ring->active_list);
|
|
|
|
INIT_LIST_HEAD(&ring->request_list);
|
|
|
|
INIT_LIST_HEAD(&ring->gpu_write_list);
|
|
|
|
}
|
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
void
|
|
|
|
i915_gem_load(struct drm_device *dev)
|
|
|
|
{
|
2009-06-23 07:41:02 -06:00
|
|
|
int i;
|
2008-07-30 13:06:12 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
2010-10-19 03:36:51 -06:00
|
|
|
INIT_LIST_HEAD(&dev_priv->mm.active_list);
|
2008-07-30 13:06:12 -06:00
|
|
|
INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
|
|
|
|
INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
|
2010-09-20 10:36:15 -06:00
|
|
|
INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
|
2009-08-29 13:49:51 -06:00
|
|
|
INIT_LIST_HEAD(&dev_priv->mm.fence_list);
|
2010-07-23 16:18:50 -06:00
|
|
|
INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
|
2010-11-05 13:24:53 -06:00
|
|
|
INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
|
2010-12-04 04:30:53 -07:00
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++)
|
|
|
|
init_ring_lists(&dev_priv->ring[i]);
|
2011-10-09 13:52:02 -06:00
|
|
|
for (i = 0; i < I915_MAX_NUM_FENCES; i++)
|
2010-04-28 03:02:31 -06:00
|
|
|
INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
|
2008-07-30 13:06:12 -06:00
|
|
|
INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
|
|
|
|
i915_gem_retire_work_handler);
|
2010-09-25 03:19:17 -06:00
|
|
|
init_completion(&dev_priv->error_completion);
|
2009-09-14 09:50:28 -06:00
|
|
|
|
2010-07-19 21:15:31 -06:00
|
|
|
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
|
|
|
|
if (IS_GEN3(dev)) {
|
|
|
|
u32 tmp = I915_READ(MI_ARB_STATE);
|
|
|
|
if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
|
|
|
|
/* arb state is a masked write, so set bit + bit in mask */
|
|
|
|
tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
|
|
|
|
I915_WRITE(MI_ARB_STATE, tmp);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-12-19 04:42:05 -07:00
|
|
|
dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
|
|
|
|
|
2008-11-12 11:03:55 -07:00
|
|
|
/* Old X drivers will take 0-2 for front, back, depth buffers */
|
2010-01-26 10:43:10 -07:00
|
|
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
|
|
|
dev_priv->fence_reg_start = 3;
|
2008-11-12 11:03:55 -07:00
|
|
|
|
2010-09-16 17:32:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
2008-11-12 11:03:55 -07:00
|
|
|
dev_priv->num_fence_regs = 16;
|
|
|
|
else
|
|
|
|
dev_priv->num_fence_regs = 8;
|
|
|
|
|
2009-06-23 07:41:02 -06:00
|
|
|
/* Initialize fence registers to zero */
|
2011-05-06 14:53:49 -06:00
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++) {
|
|
|
|
i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
|
2009-06-23 07:41:02 -06:00
|
|
|
}
|
2011-05-06 14:53:49 -06:00
|
|
|
|
2008-07-30 13:06:12 -06:00
|
|
|
i915_gem_detect_bit_6_swizzle(dev);
|
2009-11-18 09:25:18 -07:00
|
|
|
init_waitqueue_head(&dev_priv->pending_flip_queue);
|
2010-10-28 05:51:39 -06:00
|
|
|
|
2011-02-21 07:43:56 -07:00
|
|
|
dev_priv->mm.interruptible = true;
|
|
|
|
|
2010-10-28 05:51:39 -06:00
|
|
|
dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
|
|
|
|
dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
|
|
|
|
register_shrinker(&dev_priv->mm.inactive_shrinker);
|
2008-07-30 13:06:12 -06:00
|
|
|
}
|
2008-12-30 03:31:46 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Create a physically contiguous memory object for this object
|
|
|
|
* e.g. for cursor + overlay regs
|
|
|
|
*/
|
2010-08-20 06:23:26 -06:00
|
|
|
static int i915_gem_init_phys_object(struct drm_device *dev,
|
|
|
|
int id, int size, int align)
|
2008-12-30 03:31:46 -07:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_gem_phys_object *phys_obj;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (dev_priv->mm.phys_objs[id - 1] || !size)
|
|
|
|
return 0;
|
|
|
|
|
2009-03-24 13:23:04 -06:00
|
|
|
phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
|
2008-12-30 03:31:46 -07:00
|
|
|
if (!phys_obj)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
phys_obj->id = id;
|
|
|
|
|
2010-08-07 04:01:39 -06:00
|
|
|
phys_obj->handle = drm_pci_alloc(dev, size, align);
|
2008-12-30 03:31:46 -07:00
|
|
|
if (!phys_obj->handle) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto kfree_obj;
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_X86
|
|
|
|
set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
dev_priv->mm.phys_objs[id - 1] = phys_obj;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
kfree_obj:
|
2009-03-24 13:23:04 -06:00
|
|
|
kfree(phys_obj);
|
2008-12-30 03:31:46 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-08-20 06:23:26 -06:00
|
|
|
static void i915_gem_free_phys_object(struct drm_device *dev, int id)
|
2008-12-30 03:31:46 -07:00
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_gem_phys_object *phys_obj;
|
|
|
|
|
|
|
|
if (!dev_priv->mm.phys_objs[id - 1])
|
|
|
|
return;
|
|
|
|
|
|
|
|
phys_obj = dev_priv->mm.phys_objs[id - 1];
|
|
|
|
if (phys_obj->cur_obj) {
|
|
|
|
i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_X86
|
|
|
|
set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
|
|
|
|
#endif
|
|
|
|
drm_pci_free(dev, phys_obj->handle);
|
|
|
|
kfree(phys_obj);
|
|
|
|
dev_priv->mm.phys_objs[id - 1] = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_gem_free_all_phys_object(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-01-22 00:58:49 -07:00
|
|
|
for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
|
2008-12-30 03:31:46 -07:00
|
|
|
i915_gem_free_phys_object(dev, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_gem_detach_phys_object(struct drm_device *dev,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj)
|
2008-12-30 03:31:46 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
|
2010-10-28 06:45:36 -06:00
|
|
|
char *vaddr;
|
2008-12-30 03:31:46 -07:00
|
|
|
int i;
|
|
|
|
int page_count;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (!obj->phys_obj)
|
2008-12-30 03:31:46 -07:00
|
|
|
return;
|
2010-11-08 12:18:58 -07:00
|
|
|
vaddr = obj->phys_obj->handle->vaddr;
|
2008-12-30 03:31:46 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
page_count = obj->base.size / PAGE_SIZE;
|
2008-12-30 03:31:46 -07:00
|
|
|
for (i = 0; i < page_count; i++) {
|
2011-06-27 17:18:18 -06:00
|
|
|
struct page *page = shmem_read_mapping_page(mapping, i);
|
2010-10-28 06:45:36 -06:00
|
|
|
if (!IS_ERR(page)) {
|
|
|
|
char *dst = kmap_atomic(page);
|
|
|
|
memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
|
|
|
|
kunmap_atomic(dst);
|
|
|
|
|
|
|
|
drm_clflush_pages(&page, 1);
|
|
|
|
|
|
|
|
set_page_dirty(page);
|
|
|
|
mark_page_accessed(page);
|
|
|
|
page_cache_release(page);
|
|
|
|
}
|
2008-12-30 03:31:46 -07:00
|
|
|
}
|
2010-11-05 11:12:18 -06:00
|
|
|
intel_gtt_chipset_flush();
|
2009-06-17 14:52:49 -06:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->phys_obj->cur_obj = NULL;
|
|
|
|
obj->phys_obj = NULL;
|
2008-12-30 03:31:46 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
i915_gem_attach_phys_object(struct drm_device *dev,
|
2010-11-08 12:18:58 -07:00
|
|
|
struct drm_i915_gem_object *obj,
|
2010-08-07 04:01:39 -06:00
|
|
|
int id,
|
|
|
|
int align)
|
2008-12-30 03:31:46 -07:00
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
|
2008-12-30 03:31:46 -07:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
int ret = 0;
|
|
|
|
int page_count;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (id > I915_MAX_PHYS_OBJECT)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
if (obj->phys_obj) {
|
|
|
|
if (obj->phys_obj->id == id)
|
2008-12-30 03:31:46 -07:00
|
|
|
return 0;
|
|
|
|
i915_gem_detach_phys_object(dev, obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* create a new object */
|
|
|
|
if (!dev_priv->mm.phys_objs[id - 1]) {
|
|
|
|
ret = i915_gem_init_phys_object(dev, id,
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->base.size, align);
|
2008-12-30 03:31:46 -07:00
|
|
|
if (ret) {
|
2010-11-08 12:18:58 -07:00
|
|
|
DRM_ERROR("failed to init phys object %d size: %zu\n",
|
|
|
|
id, obj->base.size);
|
2010-10-28 06:45:36 -06:00
|
|
|
return ret;
|
2008-12-30 03:31:46 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* bind to the object */
|
2010-11-08 12:18:58 -07:00
|
|
|
obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
|
|
|
|
obj->phys_obj->cur_obj = obj;
|
2008-12-30 03:31:46 -07:00
|
|
|
|
2010-11-08 12:18:58 -07:00
|
|
|
page_count = obj->base.size / PAGE_SIZE;
|
2008-12-30 03:31:46 -07:00
|
|
|
|
|
|
|
for (i = 0; i < page_count; i++) {
|
2010-10-28 06:45:36 -06:00
|
|
|
struct page *page;
|
|
|
|
char *dst, *src;
|
|
|
|
|
2011-06-27 17:18:18 -06:00
|
|
|
page = shmem_read_mapping_page(mapping, i);
|
2010-10-28 06:45:36 -06:00
|
|
|
if (IS_ERR(page))
|
|
|
|
return PTR_ERR(page);
|
2008-12-30 03:31:46 -07:00
|
|
|
|
2010-10-30 15:52:31 -06:00
|
|
|
src = kmap_atomic(page);
|
2010-11-08 12:18:58 -07:00
|
|
|
dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
|
2008-12-30 03:31:46 -07:00
|
|
|
memcpy(dst, src, PAGE_SIZE);
|
2010-10-26 15:21:51 -06:00
|
|
|
kunmap_atomic(src);
|
2008-12-30 03:31:46 -07:00
|
|
|
|
2010-10-28 06:45:36 -06:00
|
|
|
mark_page_accessed(page);
|
|
|
|
page_cache_release(page);
|
|
|
|
}
|
2009-06-17 14:52:49 -06:00
|
|
|
|
2008-12-30 03:31:46 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2010-11-08 12:18:58 -07:00
|
|
|
i915_gem_phys_pwrite(struct drm_device *dev,
|
|
|
|
struct drm_i915_gem_object *obj,
|
2008-12-30 03:31:46 -07:00
|
|
|
struct drm_i915_gem_pwrite *args,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
2010-11-08 12:18:58 -07:00
|
|
|
void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
|
2010-11-07 18:12:29 -07:00
|
|
|
char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
|
2008-12-30 03:31:46 -07:00
|
|
|
|
2010-11-07 18:12:29 -07:00
|
|
|
if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
|
|
|
|
unsigned long unwritten;
|
|
|
|
|
|
|
|
/* The physical object once assigned is fixed for the lifetime
|
|
|
|
* of the obj, so we can safely drop the lock and continue
|
|
|
|
* to access vaddr.
|
|
|
|
*/
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
unwritten = copy_from_user(vaddr, user_data, args->size);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
if (unwritten)
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
2008-12-30 03:31:46 -07:00
|
|
|
|
2010-11-05 11:12:18 -06:00
|
|
|
intel_gtt_chipset_flush();
|
2008-12-30 03:31:46 -07:00
|
|
|
return 0;
|
|
|
|
}
|
2009-06-03 01:27:35 -06:00
|
|
|
|
2010-09-24 09:02:42 -06:00
|
|
|
void i915_gem_release(struct drm_device *dev, struct drm_file *file)
|
2009-06-03 01:27:35 -06:00
|
|
|
{
|
2010-09-24 09:02:42 -06:00
|
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
2009-06-03 01:27:35 -06:00
|
|
|
|
|
|
|
/* Clean up our request list when the client is going away, so that
|
|
|
|
* later retire_requests won't dereference our soon-to-be-gone
|
|
|
|
* file_priv.
|
|
|
|
*/
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_lock(&file_priv->mm.lock);
|
2010-09-24 09:02:42 -06:00
|
|
|
while (!list_empty(&file_priv->mm.request_list)) {
|
|
|
|
struct drm_i915_gem_request *request;
|
|
|
|
|
|
|
|
request = list_first_entry(&file_priv->mm.request_list,
|
|
|
|
struct drm_i915_gem_request,
|
|
|
|
client_list);
|
|
|
|
list_del(&request->client_list);
|
|
|
|
request->file_priv = NULL;
|
|
|
|
}
|
2010-09-26 04:03:27 -06:00
|
|
|
spin_unlock(&file_priv->mm.lock);
|
2009-06-03 01:27:35 -06:00
|
|
|
}
|
2009-09-14 09:50:28 -06:00
|
|
|
|
2010-04-20 10:10:35 -06:00
|
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static int
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i915_gpu_is_active(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int lists_empty;
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lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
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2010-10-28 05:51:39 -06:00
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list_empty(&dev_priv->mm.active_list);
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2010-04-20 10:10:35 -06:00
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return !lists_empty;
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}
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2009-09-14 09:50:28 -06:00
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static int
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2011-05-24 18:12:27 -06:00
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i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
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2009-09-14 09:50:28 -06:00
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{
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2010-10-28 05:51:39 -06:00
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struct drm_i915_private *dev_priv =
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container_of(shrinker,
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struct drm_i915_private,
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mm.inactive_shrinker);
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struct drm_device *dev = dev_priv->dev;
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struct drm_i915_gem_object *obj, *next;
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2011-05-24 18:12:27 -06:00
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int nr_to_scan = sc->nr_to_scan;
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2010-10-28 05:51:39 -06:00
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int cnt;
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if (!mutex_trylock(&dev->struct_mutex))
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2010-10-28 15:35:07 -06:00
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return 0;
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2009-09-14 09:50:28 -06:00
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/* "fast-path" to count number of available objects */
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if (nr_to_scan == 0) {
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2010-10-28 05:51:39 -06:00
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cnt = 0;
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list_for_each_entry(obj,
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&dev_priv->mm.inactive_list,
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mm_list)
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cnt++;
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mutex_unlock(&dev->struct_mutex);
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return cnt / 100 * sysctl_vfs_cache_pressure;
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2009-09-14 09:50:28 -06:00
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}
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2010-04-20 10:10:35 -06:00
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rescan:
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2009-09-14 09:50:28 -06:00
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/* first scan for clean buffers */
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2010-10-28 05:51:39 -06:00
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i915_gem_retire_requests(dev);
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2009-09-14 09:50:28 -06:00
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2010-10-28 05:51:39 -06:00
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list_for_each_entry_safe(obj, next,
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&dev_priv->mm.inactive_list,
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mm_list) {
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if (i915_gem_object_is_purgeable(obj)) {
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2010-11-23 08:26:33 -07:00
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if (i915_gem_object_unbind(obj) == 0 &&
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--nr_to_scan == 0)
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2010-10-28 05:51:39 -06:00
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break;
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2009-09-14 09:50:28 -06:00
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}
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}
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/* second pass, evict/count anything still on the inactive list */
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2010-10-28 05:51:39 -06:00
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cnt = 0;
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list_for_each_entry_safe(obj, next,
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&dev_priv->mm.inactive_list,
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mm_list) {
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2010-11-23 08:26:33 -07:00
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if (nr_to_scan &&
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i915_gem_object_unbind(obj) == 0)
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2010-10-28 05:51:39 -06:00
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nr_to_scan--;
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2010-11-23 08:26:33 -07:00
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else
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2010-10-28 05:51:39 -06:00
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cnt++;
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}
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if (nr_to_scan && i915_gpu_is_active(dev)) {
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2010-04-20 10:10:35 -06:00
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/*
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* We are desperate for pages, so as a last resort, wait
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* for the GPU to finish and discard whatever we can.
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* This has a dramatic impact to reduce the number of
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* OOM-killer events whilst running the GPU aggressively.
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*/
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2010-10-28 05:51:39 -06:00
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if (i915_gpu_idle(dev) == 0)
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2010-04-20 10:10:35 -06:00
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goto rescan;
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}
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2010-10-28 05:51:39 -06:00
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mutex_unlock(&dev->struct_mutex);
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return cnt / 100 * sysctl_vfs_cache_pressure;
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2009-09-14 09:50:28 -06:00
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}
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