2009-12-14 15:20:22 -07:00
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/*
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2011-06-06 01:16:30 -06:00
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* Designware SPI core controller driver (refer pxa2xx_spi.c)
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2009-12-14 15:20:22 -07:00
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*
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* Copyright (c) 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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2011-07-03 13:44:29 -06:00
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#include <linux/module.h>
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2009-12-14 15:20:22 -07:00
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#include <linux/highmem.h>
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#include <linux/delay.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2009-12-14 15:20:22 -07:00
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#include <linux/spi/spi.h>
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2011-06-06 01:16:30 -06:00
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#include "spi-dw.h"
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2011-02-28 12:47:12 -07:00
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2009-12-14 15:20:22 -07:00
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#endif
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#define START_STATE ((void *)0)
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#define RUNNING_STATE ((void *)1)
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#define DONE_STATE ((void *)2)
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#define ERROR_STATE ((void *)-1)
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#define QUEUE_RUNNING 0
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#define QUEUE_STOPPED 1
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#define MRST_SPI_DEASSERT 0
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#define MRST_SPI_ASSERT 1
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/* Slave spi_dev related */
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struct chip_data {
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u16 cr0;
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u8 cs; /* chip select pin */
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u8 n_bytes; /* current is a 1/2/4 byte op */
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u8 tmode; /* TR/TO/RO/EEPROM */
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u8 type; /* SPI/SSP/MicroWire */
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u8 poll_mode; /* 1 means use poll mode */
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u32 dma_width;
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u32 rx_threshold;
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u32 tx_threshold;
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u8 enable_dma;
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u8 bits_per_word;
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u16 clk_div; /* baud rate divider */
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u32 speed_hz; /* baud rate */
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void (*cs_control)(u32 command);
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};
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#ifdef CONFIG_DEBUG_FS
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#define SPI_REGS_BUFSIZE 1024
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static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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struct dw_spi *dws;
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char *buf;
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u32 len = 0;
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ssize_t ret;
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dws = file->private_data;
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buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
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if (!buf)
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return 0;
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"MRST SPI0 registers:\n");
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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2011-09-20 12:06:17 -06:00
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"DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
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2009-12-14 15:20:22 -07:00
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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kfree(buf);
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return ret;
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}
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static const struct file_operations mrst_spi_regs_ops = {
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.owner = THIS_MODULE,
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2012-04-05 15:25:11 -06:00
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.open = simple_open,
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2009-12-14 15:20:22 -07:00
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.read = spi_show_regs,
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llseek: automatically add .llseek fop
All file_operations should get a .llseek operation so we can make
nonseekable_open the default for future file operations without a
.llseek pointer.
The three cases that we can automatically detect are no_llseek, seq_lseek
and default_llseek. For cases where we can we can automatically prove that
the file offset is always ignored, we use noop_llseek, which maintains
the current behavior of not returning an error from a seek.
New drivers should normally not use noop_llseek but instead use no_llseek
and call nonseekable_open at open time. Existing drivers can be converted
to do the same when the maintainer knows for certain that no user code
relies on calling seek on the device file.
The generated code is often incorrectly indented and right now contains
comments that clarify for each added line why a specific variant was
chosen. In the version that gets submitted upstream, the comments will
be gone and I will manually fix the indentation, because there does not
seem to be a way to do that using coccinelle.
Some amount of new code is currently sitting in linux-next that should get
the same modifications, which I will do at the end of the merge window.
Many thanks to Julia Lawall for helping me learn to write a semantic
patch that does all this.
===== begin semantic patch =====
// This adds an llseek= method to all file operations,
// as a preparation for making no_llseek the default.
//
// The rules are
// - use no_llseek explicitly if we do nonseekable_open
// - use seq_lseek for sequential files
// - use default_llseek if we know we access f_pos
// - use noop_llseek if we know we don't access f_pos,
// but we still want to allow users to call lseek
//
@ open1 exists @
identifier nested_open;
@@
nested_open(...)
{
<+...
nonseekable_open(...)
...+>
}
@ open exists@
identifier open_f;
identifier i, f;
identifier open1.nested_open;
@@
int open_f(struct inode *i, struct file *f)
{
<+...
(
nonseekable_open(...)
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nested_open(...)
)
...+>
}
@ read disable optional_qualifier exists @
identifier read_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
expression E;
identifier func;
@@
ssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)
{
<+...
(
*off = E
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*off += E
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func(..., off, ...)
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E = *off
)
...+>
}
@ read_no_fpos disable optional_qualifier exists @
identifier read_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
@@
ssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)
{
... when != off
}
@ write @
identifier write_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
expression E;
identifier func;
@@
ssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)
{
<+...
(
*off = E
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*off += E
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func(..., off, ...)
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E = *off
)
...+>
}
@ write_no_fpos @
identifier write_f;
identifier f, p, s, off;
type ssize_t, size_t, loff_t;
@@
ssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)
{
... when != off
}
@ fops0 @
identifier fops;
@@
struct file_operations fops = {
...
};
@ has_llseek depends on fops0 @
identifier fops0.fops;
identifier llseek_f;
@@
struct file_operations fops = {
...
.llseek = llseek_f,
...
};
@ has_read depends on fops0 @
identifier fops0.fops;
identifier read_f;
@@
struct file_operations fops = {
...
.read = read_f,
...
};
@ has_write depends on fops0 @
identifier fops0.fops;
identifier write_f;
@@
struct file_operations fops = {
...
.write = write_f,
...
};
@ has_open depends on fops0 @
identifier fops0.fops;
identifier open_f;
@@
struct file_operations fops = {
...
.open = open_f,
...
};
// use no_llseek if we call nonseekable_open
////////////////////////////////////////////
@ nonseekable1 depends on !has_llseek && has_open @
identifier fops0.fops;
identifier nso ~= "nonseekable_open";
@@
struct file_operations fops = {
... .open = nso, ...
+.llseek = no_llseek, /* nonseekable */
};
@ nonseekable2 depends on !has_llseek @
identifier fops0.fops;
identifier open.open_f;
@@
struct file_operations fops = {
... .open = open_f, ...
+.llseek = no_llseek, /* open uses nonseekable */
};
// use seq_lseek for sequential files
/////////////////////////////////////
@ seq depends on !has_llseek @
identifier fops0.fops;
identifier sr ~= "seq_read";
@@
struct file_operations fops = {
... .read = sr, ...
+.llseek = seq_lseek, /* we have seq_read */
};
// use default_llseek if there is a readdir
///////////////////////////////////////////
@ fops1 depends on !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier readdir_e;
@@
// any other fop is used that changes pos
struct file_operations fops = {
... .readdir = readdir_e, ...
+.llseek = default_llseek, /* readdir is present */
};
// use default_llseek if at least one of read/write touches f_pos
/////////////////////////////////////////////////////////////////
@ fops2 depends on !fops1 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier read.read_f;
@@
// read fops use offset
struct file_operations fops = {
... .read = read_f, ...
+.llseek = default_llseek, /* read accesses f_pos */
};
@ fops3 depends on !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier write.write_f;
@@
// write fops use offset
struct file_operations fops = {
... .write = write_f, ...
+ .llseek = default_llseek, /* write accesses f_pos */
};
// Use noop_llseek if neither read nor write accesses f_pos
///////////////////////////////////////////////////////////
@ fops4 depends on !fops1 && !fops2 && !fops3 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier read_no_fpos.read_f;
identifier write_no_fpos.write_f;
@@
// write fops use offset
struct file_operations fops = {
...
.write = write_f,
.read = read_f,
...
+.llseek = noop_llseek, /* read and write both use no f_pos */
};
@ depends on has_write && !has_read && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier write_no_fpos.write_f;
@@
struct file_operations fops = {
... .write = write_f, ...
+.llseek = noop_llseek, /* write uses no f_pos */
};
@ depends on has_read && !has_write && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
identifier read_no_fpos.read_f;
@@
struct file_operations fops = {
... .read = read_f, ...
+.llseek = noop_llseek, /* read uses no f_pos */
};
@ depends on !has_read && !has_write && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @
identifier fops0.fops;
@@
struct file_operations fops = {
...
+.llseek = noop_llseek, /* no read or write fn */
};
===== End semantic patch =====
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Julia Lawall <julia@diku.dk>
Cc: Christoph Hellwig <hch@infradead.org>
2010-08-15 10:52:59 -06:00
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.llseek = default_llseek,
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2009-12-14 15:20:22 -07:00
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};
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static int mrst_spi_debugfs_init(struct dw_spi *dws)
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{
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dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
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if (!dws->debugfs)
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return -ENOMEM;
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debugfs_create_file("registers", S_IFREG | S_IRUGO,
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dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
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return 0;
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}
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static void mrst_spi_debugfs_remove(struct dw_spi *dws)
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{
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if (dws->debugfs)
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debugfs_remove_recursive(dws->debugfs);
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}
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#else
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static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
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{
|
2010-01-21 04:40:49 -07:00
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return 0;
|
2009-12-14 15:20:22 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
|
|
|
2011-03-30 09:09:54 -06:00
|
|
|
/* Return the max entries we can fill into tx fifo */
|
|
|
|
static inline u32 tx_max(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
u32 tx_left, tx_room, rxtx_gap;
|
|
|
|
|
|
|
|
tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
|
2011-09-20 12:06:17 -06:00
|
|
|
tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
|
2011-03-30 09:09:54 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Another concern is about the tx/rx mismatch, we
|
|
|
|
* though to use (dws->fifo_len - rxflr - txflr) as
|
|
|
|
* one maximum value for tx, but it doesn't cover the
|
|
|
|
* data which is out of tx/rx fifo and inside the
|
|
|
|
* shift registers. So a control from sw point of
|
|
|
|
* view is taken.
|
|
|
|
*/
|
|
|
|
rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
|
|
|
|
/ dws->n_bytes;
|
|
|
|
|
|
|
|
return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return the max entries we should read out of rx fifo */
|
|
|
|
static inline u32 rx_max(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
|
|
|
|
|
2011-09-20 12:06:17 -06:00
|
|
|
return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
|
2011-03-30 09:09:54 -06:00
|
|
|
}
|
|
|
|
|
2011-03-30 09:09:55 -06:00
|
|
|
static void dw_writer(struct dw_spi *dws)
|
2009-12-14 15:20:22 -07:00
|
|
|
{
|
2011-03-30 09:09:54 -06:00
|
|
|
u32 max = tx_max(dws);
|
2011-03-30 09:09:52 -06:00
|
|
|
u16 txw = 0;
|
2009-12-14 15:20:22 -07:00
|
|
|
|
2011-03-30 09:09:54 -06:00
|
|
|
while (max--) {
|
|
|
|
/* Set the tx word if the transfer's original "tx" is not null */
|
|
|
|
if (dws->tx_end - dws->len) {
|
|
|
|
if (dws->n_bytes == 1)
|
|
|
|
txw = *(u8 *)(dws->tx);
|
|
|
|
else
|
|
|
|
txw = *(u16 *)(dws->tx);
|
|
|
|
}
|
2011-09-20 12:06:17 -06:00
|
|
|
dw_writew(dws, DW_SPI_DR, txw);
|
2011-03-30 09:09:54 -06:00
|
|
|
dws->tx += dws->n_bytes;
|
2009-12-14 15:20:22 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-30 09:09:55 -06:00
|
|
|
static void dw_reader(struct dw_spi *dws)
|
2009-12-14 15:20:22 -07:00
|
|
|
{
|
2011-03-30 09:09:54 -06:00
|
|
|
u32 max = rx_max(dws);
|
2011-03-30 09:09:52 -06:00
|
|
|
u16 rxw;
|
2009-12-14 15:20:22 -07:00
|
|
|
|
2011-03-30 09:09:54 -06:00
|
|
|
while (max--) {
|
2011-09-20 12:06:17 -06:00
|
|
|
rxw = dw_readw(dws, DW_SPI_DR);
|
2011-03-30 09:09:52 -06:00
|
|
|
/* Care rx only if the transfer's original "rx" is not null */
|
|
|
|
if (dws->rx_end - dws->len) {
|
|
|
|
if (dws->n_bytes == 1)
|
|
|
|
*(u8 *)(dws->rx) = rxw;
|
|
|
|
else
|
|
|
|
*(u16 *)(dws->rx) = rxw;
|
|
|
|
}
|
|
|
|
dws->rx += dws->n_bytes;
|
2009-12-14 15:20:22 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *next_transfer(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
struct spi_message *msg = dws->cur_msg;
|
|
|
|
struct spi_transfer *trans = dws->cur_transfer;
|
|
|
|
|
|
|
|
/* Move to next transfer */
|
|
|
|
if (trans->transfer_list.next != &msg->transfers) {
|
|
|
|
dws->cur_transfer =
|
|
|
|
list_entry(trans->transfer_list.next,
|
|
|
|
struct spi_transfer,
|
|
|
|
transfer_list);
|
|
|
|
return RUNNING_STATE;
|
|
|
|
} else
|
|
|
|
return DONE_STATE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note: first step is the protocol driver prepares
|
|
|
|
* a dma-capable memory, and this func just need translate
|
|
|
|
* the virt addr to physical
|
|
|
|
*/
|
|
|
|
static int map_dma_buffers(struct dw_spi *dws)
|
|
|
|
{
|
2010-12-23 22:59:11 -07:00
|
|
|
if (!dws->cur_msg->is_dma_mapped
|
|
|
|
|| !dws->dma_inited
|
|
|
|
|| !dws->cur_chip->enable_dma
|
|
|
|
|| !dws->dma_ops)
|
2009-12-14 15:20:22 -07:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (dws->cur_transfer->tx_dma)
|
|
|
|
dws->tx_dma = dws->cur_transfer->tx_dma;
|
|
|
|
|
|
|
|
if (dws->cur_transfer->rx_dma)
|
|
|
|
dws->rx_dma = dws->cur_transfer->rx_dma;
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Caller already set message->status; dma and pio irqs are blocked */
|
|
|
|
static void giveback(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
struct spi_transfer *last_transfer;
|
|
|
|
unsigned long flags;
|
|
|
|
struct spi_message *msg;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dws->lock, flags);
|
|
|
|
msg = dws->cur_msg;
|
|
|
|
dws->cur_msg = NULL;
|
|
|
|
dws->cur_transfer = NULL;
|
|
|
|
dws->prev_chip = dws->cur_chip;
|
|
|
|
dws->cur_chip = NULL;
|
|
|
|
dws->dma_mapped = 0;
|
|
|
|
queue_work(dws->workqueue, &dws->pump_messages);
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
|
|
|
|
last_transfer = list_entry(msg->transfers.prev,
|
|
|
|
struct spi_transfer,
|
|
|
|
transfer_list);
|
|
|
|
|
2010-09-07 01:52:06 -06:00
|
|
|
if (!last_transfer->cs_change && dws->cs_control)
|
2009-12-14 15:20:22 -07:00
|
|
|
dws->cs_control(MRST_SPI_DEASSERT);
|
|
|
|
|
|
|
|
msg->state = NULL;
|
|
|
|
if (msg->complete)
|
|
|
|
msg->complete(msg->context);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void int_error_stop(struct dw_spi *dws, const char *msg)
|
|
|
|
{
|
2011-03-30 09:09:53 -06:00
|
|
|
/* Stop the hw */
|
2009-12-14 15:20:22 -07:00
|
|
|
spi_enable_chip(dws, 0);
|
|
|
|
|
|
|
|
dev_err(&dws->master->dev, "%s\n", msg);
|
|
|
|
dws->cur_msg->state = ERROR_STATE;
|
|
|
|
tasklet_schedule(&dws->pump_transfers);
|
|
|
|
}
|
|
|
|
|
2010-12-23 22:59:11 -07:00
|
|
|
void dw_spi_xfer_done(struct dw_spi *dws)
|
2009-12-14 15:20:22 -07:00
|
|
|
{
|
2011-03-30 19:57:33 -06:00
|
|
|
/* Update total byte transferred return count actual bytes read */
|
2009-12-14 15:20:22 -07:00
|
|
|
dws->cur_msg->actual_length += dws->len;
|
|
|
|
|
|
|
|
/* Move to next transfer */
|
|
|
|
dws->cur_msg->state = next_transfer(dws);
|
|
|
|
|
|
|
|
/* Handle end of message */
|
|
|
|
if (dws->cur_msg->state == DONE_STATE) {
|
|
|
|
dws->cur_msg->status = 0;
|
|
|
|
giveback(dws);
|
|
|
|
} else
|
|
|
|
tasklet_schedule(&dws->pump_transfers);
|
|
|
|
}
|
2010-12-23 22:59:11 -07:00
|
|
|
EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
static irqreturn_t interrupt_transfer(struct dw_spi *dws)
|
|
|
|
{
|
2011-09-20 12:06:17 -06:00
|
|
|
u16 irq_status = dw_readw(dws, DW_SPI_ISR);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
/* Error handling */
|
|
|
|
if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
|
2011-09-20 12:06:17 -06:00
|
|
|
dw_readw(dws, DW_SPI_TXOICR);
|
|
|
|
dw_readw(dws, DW_SPI_RXOICR);
|
|
|
|
dw_readw(dws, DW_SPI_RXUICR);
|
2011-03-30 09:09:55 -06:00
|
|
|
int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
|
2009-12-14 15:20:22 -07:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2011-03-30 09:09:55 -06:00
|
|
|
dw_reader(dws);
|
|
|
|
if (dws->rx_end == dws->rx) {
|
|
|
|
spi_mask_intr(dws, SPI_INT_TXEI);
|
|
|
|
dw_spi_xfer_done(dws);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2010-01-20 13:49:45 -07:00
|
|
|
if (irq_status & SPI_INT_TXEI) {
|
|
|
|
spi_mask_intr(dws, SPI_INT_TXEI);
|
2011-03-30 09:09:55 -06:00
|
|
|
dw_writer(dws);
|
|
|
|
/* Enable TX irq always, it will be disabled when RX finished */
|
|
|
|
spi_umask_intr(dws, SPI_INT_TXEI);
|
2009-12-14 15:20:22 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t dw_spi_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct dw_spi *dws = dev_id;
|
2011-09-20 12:06:17 -06:00
|
|
|
u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
|
2010-09-07 01:27:27 -06:00
|
|
|
|
|
|
|
if (!irq_status)
|
|
|
|
return IRQ_NONE;
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
if (!dws->cur_msg) {
|
|
|
|
spi_mask_intr(dws, SPI_INT_TXEI);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dws->transfer_handler(dws);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Must be called inside pump_transfers() */
|
|
|
|
static void poll_transfer(struct dw_spi *dws)
|
|
|
|
{
|
2011-03-30 09:09:54 -06:00
|
|
|
do {
|
|
|
|
dw_writer(dws);
|
2011-03-30 09:09:52 -06:00
|
|
|
dw_reader(dws);
|
2011-03-30 09:09:54 -06:00
|
|
|
cpu_relax();
|
|
|
|
} while (dws->rx_end > dws->rx);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
2010-12-23 22:59:11 -07:00
|
|
|
dw_spi_xfer_done(dws);
|
2009-12-14 15:20:22 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pump_transfers(unsigned long data)
|
|
|
|
{
|
|
|
|
struct dw_spi *dws = (struct dw_spi *)data;
|
|
|
|
struct spi_message *message = NULL;
|
|
|
|
struct spi_transfer *transfer = NULL;
|
|
|
|
struct spi_transfer *previous = NULL;
|
|
|
|
struct spi_device *spi = NULL;
|
|
|
|
struct chip_data *chip = NULL;
|
|
|
|
u8 bits = 0;
|
|
|
|
u8 imask = 0;
|
|
|
|
u8 cs_change = 0;
|
2010-01-20 13:49:45 -07:00
|
|
|
u16 txint_level = 0;
|
2009-12-14 15:20:22 -07:00
|
|
|
u16 clk_div = 0;
|
|
|
|
u32 speed = 0;
|
|
|
|
u32 cr0 = 0;
|
|
|
|
|
|
|
|
/* Get current state information */
|
|
|
|
message = dws->cur_msg;
|
|
|
|
transfer = dws->cur_transfer;
|
|
|
|
chip = dws->cur_chip;
|
|
|
|
spi = message->spi;
|
|
|
|
|
2010-01-20 13:49:45 -07:00
|
|
|
if (unlikely(!chip->clk_div))
|
|
|
|
chip->clk_div = dws->max_freq / chip->speed_hz;
|
|
|
|
|
2009-12-14 15:20:22 -07:00
|
|
|
if (message->state == ERROR_STATE) {
|
|
|
|
message->status = -EIO;
|
|
|
|
goto early_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle end of message */
|
|
|
|
if (message->state == DONE_STATE) {
|
|
|
|
message->status = 0;
|
|
|
|
goto early_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Delay if requested at end of transfer*/
|
|
|
|
if (message->state == RUNNING_STATE) {
|
|
|
|
previous = list_entry(transfer->transfer_list.prev,
|
|
|
|
struct spi_transfer,
|
|
|
|
transfer_list);
|
|
|
|
if (previous->delay_usecs)
|
|
|
|
udelay(previous->delay_usecs);
|
|
|
|
}
|
|
|
|
|
|
|
|
dws->n_bytes = chip->n_bytes;
|
|
|
|
dws->dma_width = chip->dma_width;
|
|
|
|
dws->cs_control = chip->cs_control;
|
|
|
|
|
|
|
|
dws->rx_dma = transfer->rx_dma;
|
|
|
|
dws->tx_dma = transfer->tx_dma;
|
|
|
|
dws->tx = (void *)transfer->tx_buf;
|
|
|
|
dws->tx_end = dws->tx + transfer->len;
|
|
|
|
dws->rx = transfer->rx_buf;
|
|
|
|
dws->rx_end = dws->rx + transfer->len;
|
|
|
|
dws->cs_change = transfer->cs_change;
|
|
|
|
dws->len = dws->cur_transfer->len;
|
|
|
|
if (chip != dws->prev_chip)
|
|
|
|
cs_change = 1;
|
|
|
|
|
|
|
|
cr0 = chip->cr0;
|
|
|
|
|
|
|
|
/* Handle per transfer options for bpw and speed */
|
|
|
|
if (transfer->speed_hz) {
|
|
|
|
speed = chip->speed_hz;
|
|
|
|
|
|
|
|
if (transfer->speed_hz != speed) {
|
|
|
|
speed = transfer->speed_hz;
|
|
|
|
if (speed > dws->max_freq) {
|
|
|
|
printk(KERN_ERR "MRST SPI0: unsupported"
|
|
|
|
"freq: %dHz\n", speed);
|
|
|
|
message->status = -EIO;
|
|
|
|
goto early_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clk_div doesn't support odd number */
|
|
|
|
clk_div = dws->max_freq / speed;
|
2010-01-20 13:49:45 -07:00
|
|
|
clk_div = (clk_div + 1) & 0xfffe;
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
chip->speed_hz = speed;
|
|
|
|
chip->clk_div = clk_div;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (transfer->bits_per_word) {
|
|
|
|
bits = transfer->bits_per_word;
|
|
|
|
|
|
|
|
switch (bits) {
|
|
|
|
case 8:
|
|
|
|
case 16:
|
2011-03-30 09:09:55 -06:00
|
|
|
dws->n_bytes = dws->dma_width = bits >> 3;
|
2009-12-14 15:20:22 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk(KERN_ERR "MRST SPI0: unsupported bits:"
|
|
|
|
"%db\n", bits);
|
|
|
|
message->status = -EIO;
|
|
|
|
goto early_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
cr0 = (bits - 1)
|
|
|
|
| (chip->type << SPI_FRF_OFFSET)
|
|
|
|
| (spi->mode << SPI_MODE_OFFSET)
|
|
|
|
| (chip->tmode << SPI_TMOD_OFFSET);
|
|
|
|
}
|
|
|
|
message->state = RUNNING_STATE;
|
|
|
|
|
2010-01-21 04:40:52 -07:00
|
|
|
/*
|
|
|
|
* Adjust transfer mode if necessary. Requires platform dependent
|
|
|
|
* chipselect mechanism.
|
|
|
|
*/
|
|
|
|
if (dws->cs_control) {
|
|
|
|
if (dws->rx && dws->tx)
|
2010-09-07 01:52:06 -06:00
|
|
|
chip->tmode = SPI_TMOD_TR;
|
2010-01-21 04:40:52 -07:00
|
|
|
else if (dws->rx)
|
2010-09-07 01:52:06 -06:00
|
|
|
chip->tmode = SPI_TMOD_RO;
|
2010-01-21 04:40:52 -07:00
|
|
|
else
|
2010-09-07 01:52:06 -06:00
|
|
|
chip->tmode = SPI_TMOD_TO;
|
2010-01-21 04:40:52 -07:00
|
|
|
|
2010-09-07 01:52:06 -06:00
|
|
|
cr0 &= ~SPI_TMOD_MASK;
|
2010-01-21 04:40:52 -07:00
|
|
|
cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
|
|
|
|
}
|
|
|
|
|
2009-12-14 15:20:22 -07:00
|
|
|
/* Check if current transfer is a DMA transaction */
|
|
|
|
dws->dma_mapped = map_dma_buffers(dws);
|
|
|
|
|
2010-01-20 13:49:45 -07:00
|
|
|
/*
|
|
|
|
* Interrupt mode
|
|
|
|
* we only need set the TXEI IRQ, as TX/RX always happen syncronizely
|
|
|
|
*/
|
2009-12-14 15:20:22 -07:00
|
|
|
if (!dws->dma_mapped && !chip->poll_mode) {
|
2010-01-20 13:49:45 -07:00
|
|
|
int templen = dws->len / dws->n_bytes;
|
|
|
|
txint_level = dws->fifo_len / 2;
|
|
|
|
txint_level = (templen > txint_level) ? txint_level : templen;
|
|
|
|
|
2011-03-30 09:09:55 -06:00
|
|
|
imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
|
2009-12-14 15:20:22 -07:00
|
|
|
dws->transfer_handler = interrupt_transfer;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reprogram registers only if
|
|
|
|
* 1. chip select changes
|
|
|
|
* 2. clk_div is changed
|
|
|
|
* 3. control value changes
|
|
|
|
*/
|
2011-09-20 12:06:17 -06:00
|
|
|
if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
|
2009-12-14 15:20:22 -07:00
|
|
|
spi_enable_chip(dws, 0);
|
|
|
|
|
2011-09-20 12:06:17 -06:00
|
|
|
if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
|
|
|
|
dw_writew(dws, DW_SPI_CTRL0, cr0);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
2010-01-20 13:49:45 -07:00
|
|
|
spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
|
|
|
|
spi_chip_sel(dws, spi->chip_select);
|
|
|
|
|
2010-12-30 16:07:51 -07:00
|
|
|
/* Set the interrupt mask, for poll mode just disable all int */
|
2009-12-14 15:20:22 -07:00
|
|
|
spi_mask_intr(dws, 0xff);
|
2010-01-20 13:49:45 -07:00
|
|
|
if (imask)
|
2009-12-14 15:20:22 -07:00
|
|
|
spi_umask_intr(dws, imask);
|
2010-01-20 13:49:45 -07:00
|
|
|
if (txint_level)
|
2011-09-20 12:06:17 -06:00
|
|
|
dw_writew(dws, DW_SPI_TXFLTR, txint_level);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
spi_enable_chip(dws, 1);
|
|
|
|
if (cs_change)
|
|
|
|
dws->prev_chip = chip;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dws->dma_mapped)
|
2010-12-23 22:59:11 -07:00
|
|
|
dws->dma_ops->dma_transfer(dws, cs_change);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
if (chip->poll_mode)
|
|
|
|
poll_transfer(dws);
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
early_exit:
|
|
|
|
giveback(dws);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pump_messages(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct dw_spi *dws =
|
|
|
|
container_of(work, struct dw_spi, pump_messages);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
/* Lock queue and check for queue work */
|
|
|
|
spin_lock_irqsave(&dws->lock, flags);
|
|
|
|
if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
|
|
|
|
dws->busy = 0;
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure we are not already running a message */
|
|
|
|
if (dws->cur_msg) {
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Extract head of queue */
|
|
|
|
dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
|
|
|
|
list_del_init(&dws->cur_msg->queue);
|
|
|
|
|
|
|
|
/* Initial message state*/
|
|
|
|
dws->cur_msg->state = START_STATE;
|
|
|
|
dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
|
|
|
|
struct spi_transfer,
|
|
|
|
transfer_list);
|
|
|
|
dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
|
|
|
|
|
|
|
|
/* Mark as busy and launch transfers */
|
|
|
|
tasklet_schedule(&dws->pump_transfers);
|
|
|
|
|
|
|
|
dws->busy = 1;
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* spi_device use this to queue in their spi_msg */
|
|
|
|
static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
|
|
|
|
{
|
|
|
|
struct dw_spi *dws = spi_master_get_devdata(spi->master);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dws->lock, flags);
|
|
|
|
|
|
|
|
if (dws->run == QUEUE_STOPPED) {
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
return -ESHUTDOWN;
|
|
|
|
}
|
|
|
|
|
|
|
|
msg->actual_length = 0;
|
|
|
|
msg->status = -EINPROGRESS;
|
|
|
|
msg->state = START_STATE;
|
|
|
|
|
|
|
|
list_add_tail(&msg->queue, &dws->queue);
|
|
|
|
|
|
|
|
if (dws->run == QUEUE_RUNNING && !dws->busy) {
|
|
|
|
|
|
|
|
if (dws->cur_transfer || dws->cur_msg)
|
|
|
|
queue_work(dws->workqueue,
|
|
|
|
&dws->pump_messages);
|
|
|
|
else {
|
|
|
|
/* If no other data transaction in air, just go */
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
pump_messages(&dws->pump_messages);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* This may be called twice for each spi dev */
|
|
|
|
static int dw_spi_setup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct dw_spi_chip *chip_info = NULL;
|
|
|
|
struct chip_data *chip;
|
|
|
|
|
|
|
|
if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Only alloc on first setup */
|
|
|
|
chip = spi_get_ctldata(spi);
|
|
|
|
if (!chip) {
|
|
|
|
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
|
|
|
if (!chip)
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Protocol drivers may change the chip settings, so...
|
|
|
|
* if chip_info exists, use it
|
|
|
|
*/
|
|
|
|
chip_info = spi->controller_data;
|
|
|
|
|
|
|
|
/* chip_info doesn't always exist */
|
|
|
|
if (chip_info) {
|
|
|
|
if (chip_info->cs_control)
|
|
|
|
chip->cs_control = chip_info->cs_control;
|
|
|
|
|
|
|
|
chip->poll_mode = chip_info->poll_mode;
|
|
|
|
chip->type = chip_info->type;
|
|
|
|
|
|
|
|
chip->rx_threshold = 0;
|
|
|
|
chip->tx_threshold = 0;
|
|
|
|
|
|
|
|
chip->enable_dma = chip_info->enable_dma;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (spi->bits_per_word <= 8) {
|
|
|
|
chip->n_bytes = 1;
|
|
|
|
chip->dma_width = 1;
|
|
|
|
} else if (spi->bits_per_word <= 16) {
|
|
|
|
chip->n_bytes = 2;
|
|
|
|
chip->dma_width = 2;
|
|
|
|
} else {
|
|
|
|
/* Never take >16b case for MRST SPIC */
|
|
|
|
dev_err(&spi->dev, "invalid wordsize\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
chip->bits_per_word = spi->bits_per_word;
|
|
|
|
|
2010-01-20 13:49:45 -07:00
|
|
|
if (!spi->max_speed_hz) {
|
|
|
|
dev_err(&spi->dev, "No max speed HZ parameter\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-12-14 15:20:22 -07:00
|
|
|
chip->speed_hz = spi->max_speed_hz;
|
|
|
|
|
|
|
|
chip->tmode = 0; /* Tx & Rx */
|
|
|
|
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
|
|
|
|
chip->cr0 = (chip->bits_per_word - 1)
|
|
|
|
| (chip->type << SPI_FRF_OFFSET)
|
|
|
|
| (spi->mode << SPI_MODE_OFFSET)
|
|
|
|
| (chip->tmode << SPI_TMOD_OFFSET);
|
|
|
|
|
|
|
|
spi_set_ctldata(spi, chip);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dw_spi_cleanup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct chip_data *chip = spi_get_ctldata(spi);
|
|
|
|
kfree(chip);
|
|
|
|
}
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
static int init_queue(struct dw_spi *dws)
|
2009-12-14 15:20:22 -07:00
|
|
|
{
|
|
|
|
INIT_LIST_HEAD(&dws->queue);
|
|
|
|
spin_lock_init(&dws->lock);
|
|
|
|
|
|
|
|
dws->run = QUEUE_STOPPED;
|
|
|
|
dws->busy = 0;
|
|
|
|
|
|
|
|
tasklet_init(&dws->pump_transfers,
|
|
|
|
pump_transfers, (unsigned long)dws);
|
|
|
|
|
|
|
|
INIT_WORK(&dws->pump_messages, pump_messages);
|
|
|
|
dws->workqueue = create_singlethread_workqueue(
|
|
|
|
dev_name(dws->master->dev.parent));
|
|
|
|
if (dws->workqueue == NULL)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int start_queue(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dws->lock, flags);
|
|
|
|
|
|
|
|
if (dws->run == QUEUE_RUNNING || dws->busy) {
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
dws->run = QUEUE_RUNNING;
|
|
|
|
dws->cur_msg = NULL;
|
|
|
|
dws->cur_transfer = NULL;
|
|
|
|
dws->cur_chip = NULL;
|
|
|
|
dws->prev_chip = NULL;
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
|
|
|
|
queue_work(dws->workqueue, &dws->pump_messages);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stop_queue(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
unsigned limit = 50;
|
|
|
|
int status = 0;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dws->lock, flags);
|
|
|
|
dws->run = QUEUE_STOPPED;
|
2011-04-06 08:49:15 -06:00
|
|
|
while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
|
2009-12-14 15:20:22 -07:00
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
msleep(10);
|
|
|
|
spin_lock_irqsave(&dws->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!list_empty(&dws->queue) || dws->busy)
|
|
|
|
status = -EBUSY;
|
|
|
|
spin_unlock_irqrestore(&dws->lock, flags);
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int destroy_queue(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
int status;
|
|
|
|
|
|
|
|
status = stop_queue(dws);
|
|
|
|
if (status != 0)
|
|
|
|
return status;
|
|
|
|
destroy_workqueue(dws->workqueue);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Restart the controller, disable all interrupts, clean rx fifo */
|
|
|
|
static void spi_hw_init(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
spi_enable_chip(dws, 0);
|
|
|
|
spi_mask_intr(dws, 0xff);
|
|
|
|
spi_enable_chip(dws, 1);
|
2010-01-20 19:41:10 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Try to detect the FIFO depth if not set by interface driver,
|
|
|
|
* the depth could be from 2 to 256 from HW spec
|
|
|
|
*/
|
|
|
|
if (!dws->fifo_len) {
|
|
|
|
u32 fifo;
|
|
|
|
for (fifo = 2; fifo <= 257; fifo++) {
|
2011-09-20 12:06:17 -06:00
|
|
|
dw_writew(dws, DW_SPI_TXFLTR, fifo);
|
|
|
|
if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
|
2010-01-20 19:41:10 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
dws->fifo_len = (fifo == 257) ? 0 : fifo;
|
2011-09-20 12:06:17 -06:00
|
|
|
dw_writew(dws, DW_SPI_TXFLTR, 0);
|
2010-01-20 19:41:10 -07:00
|
|
|
}
|
2009-12-14 15:20:22 -07:00
|
|
|
}
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
int dw_spi_add_host(struct dw_spi *dws)
|
2009-12-14 15:20:22 -07:00
|
|
|
{
|
|
|
|
struct spi_master *master;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
BUG_ON(dws == NULL);
|
|
|
|
|
|
|
|
master = spi_alloc_master(dws->parent_dev, 0);
|
|
|
|
if (!master) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
dws->master = master;
|
|
|
|
dws->type = SSI_MOTO_SPI;
|
|
|
|
dws->prev_chip = NULL;
|
|
|
|
dws->dma_inited = 0;
|
|
|
|
dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
|
2011-07-08 00:24:31 -06:00
|
|
|
snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
|
|
|
|
dws->bus_num);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
2010-09-07 01:27:27 -06:00
|
|
|
ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
|
2011-07-08 00:24:31 -06:00
|
|
|
dws->name, dws);
|
2009-12-14 15:20:22 -07:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&master->dev, "can not get IRQ\n");
|
|
|
|
goto err_free_master;
|
|
|
|
}
|
|
|
|
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
|
|
|
master->bus_num = dws->bus_num;
|
|
|
|
master->num_chipselect = dws->num_cs;
|
|
|
|
master->cleanup = dw_spi_cleanup;
|
|
|
|
master->setup = dw_spi_setup;
|
|
|
|
master->transfer = dw_spi_transfer;
|
|
|
|
|
|
|
|
/* Basic HW init */
|
|
|
|
spi_hw_init(dws);
|
|
|
|
|
2010-12-23 22:59:11 -07:00
|
|
|
if (dws->dma_ops && dws->dma_ops->dma_init) {
|
|
|
|
ret = dws->dma_ops->dma_init(dws);
|
|
|
|
if (ret) {
|
|
|
|
dev_warn(&master->dev, "DMA init failed\n");
|
|
|
|
dws->dma_inited = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-12-14 15:20:22 -07:00
|
|
|
/* Initial and start queue */
|
|
|
|
ret = init_queue(dws);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&master->dev, "problem initializing queue\n");
|
|
|
|
goto err_diable_hw;
|
|
|
|
}
|
|
|
|
ret = start_queue(dws);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&master->dev, "problem starting queue\n");
|
|
|
|
goto err_diable_hw;
|
|
|
|
}
|
|
|
|
|
|
|
|
spi_master_set_devdata(master, dws);
|
|
|
|
ret = spi_register_master(master);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&master->dev, "problem registering spi master\n");
|
|
|
|
goto err_queue_alloc;
|
|
|
|
}
|
|
|
|
|
|
|
|
mrst_spi_debugfs_init(dws);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_queue_alloc:
|
|
|
|
destroy_queue(dws);
|
2010-12-23 22:59:11 -07:00
|
|
|
if (dws->dma_ops && dws->dma_ops->dma_exit)
|
|
|
|
dws->dma_ops->dma_exit(dws);
|
2009-12-14 15:20:22 -07:00
|
|
|
err_diable_hw:
|
|
|
|
spi_enable_chip(dws, 0);
|
|
|
|
free_irq(dws->irq, dws);
|
|
|
|
err_free_master:
|
|
|
|
spi_master_put(master);
|
|
|
|
exit:
|
|
|
|
return ret;
|
|
|
|
}
|
2010-12-23 22:59:10 -07:00
|
|
|
EXPORT_SYMBOL_GPL(dw_spi_add_host);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
void dw_spi_remove_host(struct dw_spi *dws)
|
2009-12-14 15:20:22 -07:00
|
|
|
{
|
|
|
|
int status = 0;
|
|
|
|
|
|
|
|
if (!dws)
|
|
|
|
return;
|
|
|
|
mrst_spi_debugfs_remove(dws);
|
|
|
|
|
|
|
|
/* Remove the queue */
|
|
|
|
status = destroy_queue(dws);
|
|
|
|
if (status != 0)
|
|
|
|
dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
|
|
|
|
"complete, message memory not freed\n");
|
|
|
|
|
2010-12-23 22:59:11 -07:00
|
|
|
if (dws->dma_ops && dws->dma_ops->dma_exit)
|
|
|
|
dws->dma_ops->dma_exit(dws);
|
2009-12-14 15:20:22 -07:00
|
|
|
spi_enable_chip(dws, 0);
|
|
|
|
/* Disable clk */
|
|
|
|
spi_set_clk(dws, 0);
|
|
|
|
free_irq(dws->irq, dws);
|
|
|
|
|
|
|
|
/* Disconnect from the SPI framework */
|
|
|
|
spi_unregister_master(dws->master);
|
|
|
|
}
|
2010-12-23 22:59:10 -07:00
|
|
|
EXPORT_SYMBOL_GPL(dw_spi_remove_host);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
int dw_spi_suspend_host(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = stop_queue(dws);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
spi_enable_chip(dws, 0);
|
|
|
|
spi_set_clk(dws, 0);
|
|
|
|
return ret;
|
|
|
|
}
|
2010-12-23 22:59:10 -07:00
|
|
|
EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
int dw_spi_resume_host(struct dw_spi *dws)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
spi_hw_init(dws);
|
|
|
|
ret = start_queue(dws);
|
|
|
|
if (ret)
|
|
|
|
dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
2010-12-23 22:59:10 -07:00
|
|
|
EXPORT_SYMBOL_GPL(dw_spi_resume_host);
|
2009-12-14 15:20:22 -07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
|
|
|
|
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
|
|
|
|
MODULE_LICENSE("GPL v2");
|