2011-02-21 03:35:28 -07:00
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/*
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* Portions copyright (C) 2003 Russell King, PXA MMCI Driver
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* Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
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*
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* Copyright 2008 Embedded Alley Solutions, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/highmem.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/completion.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sdio.h>
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#include <linux/gpio.h>
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#include <linux/regulator/consumer.h>
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2011-07-03 13:15:51 -06:00
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#include <linux/module.h>
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2012-02-15 23:17:32 -07:00
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#include <linux/fsl/mxs-dma.h>
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2012-05-06 08:56:16 -06:00
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#include <linux/pinctrl/consumer.h>
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2012-05-05 05:40:09 -06:00
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#include <linux/stmp_device.h>
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2012-05-05 20:04:23 -06:00
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#include <linux/mmc/mxs-mmc.h>
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2011-02-21 03:35:28 -07:00
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#define DRIVER_NAME "mxs-mmc"
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/* card detect polling timeout */
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#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
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2012-05-05 06:24:01 -06:00
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#define ssp_is_old(host) ((host)->devid == IMX23_MMC)
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2011-02-21 03:35:28 -07:00
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/* SSP registers */
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#define HW_SSP_CTRL0 0x000
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#define BM_SSP_CTRL0_RUN (1 << 29)
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#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
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#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
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#define BM_SSP_CTRL0_READ (1 << 25)
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#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
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#define BP_SSP_CTRL0_BUS_WIDTH (22)
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#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
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#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
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#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
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#define BM_SSP_CTRL0_GET_RESP (1 << 17)
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#define BM_SSP_CTRL0_ENABLE (1 << 16)
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#define BP_SSP_CTRL0_XFER_COUNT (0)
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#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
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#define HW_SSP_CMD0 0x010
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#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
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#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
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#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
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#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
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#define BP_SSP_CMD0_BLOCK_SIZE (16)
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#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
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#define BP_SSP_CMD0_BLOCK_COUNT (8)
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#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
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#define BP_SSP_CMD0_CMD (0)
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#define BM_SSP_CMD0_CMD (0xff)
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#define HW_SSP_CMD1 0x020
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#define HW_SSP_XFER_SIZE 0x030
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#define HW_SSP_BLOCK_SIZE 0x040
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#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
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#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
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#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
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#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
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2012-05-05 19:36:39 -06:00
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#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
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2011-02-21 03:35:28 -07:00
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#define BP_SSP_TIMING_TIMEOUT (16)
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#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
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#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
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#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
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#define BP_SSP_TIMING_CLOCK_RATE (0)
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#define BM_SSP_TIMING_CLOCK_RATE (0xff)
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2012-05-05 19:36:39 -06:00
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#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
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2011-02-21 03:35:28 -07:00
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#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
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#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
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#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
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#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
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#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
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#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
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#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
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#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
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#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
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#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
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#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
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#define BM_SSP_CTRL1_POLARITY (1 << 9)
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#define BP_SSP_CTRL1_WORD_LENGTH (4)
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#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
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#define BP_SSP_CTRL1_SSP_MODE (0)
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#define BM_SSP_CTRL1_SSP_MODE (0xf)
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2012-05-05 19:36:39 -06:00
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#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
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#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
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#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
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#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
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#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
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2011-02-21 03:35:28 -07:00
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#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
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#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
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#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
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#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
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BM_SSP_CTRL1_RESP_ERR_IRQ | \
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BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
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BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
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BM_SSP_CTRL1_DATA_CRC_IRQ | \
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BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
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BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
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BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
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#define SSP_PIO_NUM 3
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2012-05-05 06:24:01 -06:00
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enum mxs_mmc_id {
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IMX23_MMC,
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IMX28_MMC,
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};
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2011-02-21 03:35:28 -07:00
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struct mxs_mmc_host {
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struct mmc_host *mmc;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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void __iomem *base;
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struct resource *dma_res;
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struct clk *clk;
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unsigned int clk_rate;
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struct dma_chan *dmach;
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struct mxs_dma_data dma_data;
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unsigned int dma_dir;
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2011-10-13 23:15:11 -06:00
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enum dma_transfer_direction slave_dirn;
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2011-02-21 03:35:28 -07:00
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u32 ssp_pio_words[SSP_PIO_NUM];
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2012-05-05 06:24:01 -06:00
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enum mxs_mmc_id devid;
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2011-02-21 03:35:28 -07:00
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unsigned char bus_width;
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spinlock_t lock;
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int sdio_irq_en;
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};
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static int mxs_mmc_get_ro(struct mmc_host *mmc)
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{
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struct mxs_mmc_host *host = mmc_priv(mmc);
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struct mxs_mmc_platform_data *pdata =
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mmc_dev(host->mmc)->platform_data;
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if (!pdata)
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return -EFAULT;
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if (!gpio_is_valid(pdata->wp_gpio))
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return -EINVAL;
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return gpio_get_value(pdata->wp_gpio);
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}
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static int mxs_mmc_get_cd(struct mmc_host *mmc)
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{
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struct mxs_mmc_host *host = mmc_priv(mmc);
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2012-05-05 19:36:39 -06:00
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return !(readl(host->base + HW_SSP_STATUS(host)) &
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2011-02-21 03:35:28 -07:00
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BM_SSP_STATUS_CARD_DETECT);
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}
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static void mxs_mmc_reset(struct mxs_mmc_host *host)
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{
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u32 ctrl0, ctrl1;
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2012-05-05 05:40:09 -06:00
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stmp_reset_block(host->base);
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2011-02-21 03:35:28 -07:00
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ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
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ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
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BF_SSP(0x7, CTRL1_WORD_LENGTH) |
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BM_SSP_CTRL1_DMA_ENABLE |
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BM_SSP_CTRL1_POLARITY |
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BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
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BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
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BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
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BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
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BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
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writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
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BF_SSP(2, TIMING_CLOCK_DIVIDE) |
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BF_SSP(0, TIMING_CLOCK_RATE),
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2012-05-05 19:36:39 -06:00
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host->base + HW_SSP_TIMING(host));
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2011-02-21 03:35:28 -07:00
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if (host->sdio_irq_en) {
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ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
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ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
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}
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writel(ctrl0, host->base + HW_SSP_CTRL0);
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2012-05-05 19:36:39 -06:00
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writel(ctrl1, host->base + HW_SSP_CTRL1(host));
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2011-02-21 03:35:28 -07:00
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}
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static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
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struct mmc_command *cmd);
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static void mxs_mmc_request_done(struct mxs_mmc_host *host)
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{
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struct mmc_command *cmd = host->cmd;
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struct mmc_data *data = host->data;
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struct mmc_request *mrq = host->mrq;
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if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
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if (mmc_resp_type(cmd) & MMC_RSP_136) {
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2012-05-05 19:36:39 -06:00
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cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
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cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
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cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
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cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
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2011-02-21 03:35:28 -07:00
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} else {
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cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
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2011-02-21 03:35:28 -07:00
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}
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}
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if (data) {
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dma_unmap_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, host->dma_dir);
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/*
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* If there was an error on any block, we mark all
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* data blocks as being in error.
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*/
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if (!data->error)
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data->bytes_xfered = data->blocks * data->blksz;
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else
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data->bytes_xfered = 0;
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host->data = NULL;
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if (mrq->stop) {
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mxs_mmc_start_cmd(host, mrq->stop);
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return;
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}
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}
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host->mrq = NULL;
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mmc_request_done(host->mmc, mrq);
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}
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static void mxs_mmc_dma_irq_callback(void *param)
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{
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struct mxs_mmc_host *host = param;
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mxs_mmc_request_done(host);
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}
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static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
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{
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struct mxs_mmc_host *host = dev_id;
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struct mmc_command *cmd = host->cmd;
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struct mmc_data *data = host->data;
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u32 stat;
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spin_lock(&host->lock);
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2012-05-05 19:36:39 -06:00
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stat = readl(host->base + HW_SSP_CTRL1(host));
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2011-02-21 03:35:28 -07:00
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writel(stat & MXS_MMC_IRQ_BITS,
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2012-05-05 19:36:39 -06:00
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host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
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2011-02-21 03:35:28 -07:00
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if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
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mmc_signal_sdio_irq(host->mmc);
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spin_unlock(&host->lock);
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if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
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cmd->error = -ETIMEDOUT;
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else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
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cmd->error = -EIO;
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if (data) {
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if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
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BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
|
|
|
|
data->error = -ETIMEDOUT;
|
|
|
|
else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
|
|
|
|
data->error = -EILSEQ;
|
|
|
|
else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
|
|
|
|
BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
|
|
|
|
data->error = -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
|
mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^
|
|
set WAIT4END here
This chain works fine in the mx23/mx28.
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
<1> For mxs-mmc driver, just use the new flags, do not change any logic.
<2> For gpmi-nand driver, and use the new flags to set the DMA
chain, especially for ecc read page.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-02-15 23:17:33 -07:00
|
|
|
struct mxs_mmc_host *host, unsigned long flags)
|
2011-02-21 03:35:28 -07:00
|
|
|
{
|
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
struct scatterlist * sgl;
|
|
|
|
unsigned int sg_len;
|
|
|
|
|
|
|
|
if (data) {
|
|
|
|
/* data */
|
|
|
|
dma_map_sg(mmc_dev(host->mmc), data->sg,
|
|
|
|
data->sg_len, host->dma_dir);
|
|
|
|
sgl = data->sg;
|
|
|
|
sg_len = data->sg_len;
|
|
|
|
} else {
|
|
|
|
/* pio */
|
|
|
|
sgl = (struct scatterlist *) host->ssp_pio_words;
|
|
|
|
sg_len = SSP_PIO_NUM;
|
|
|
|
}
|
|
|
|
|
2012-03-08 14:11:18 -07:00
|
|
|
desc = dmaengine_prep_slave_sg(host->dmach,
|
mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^
|
|
set WAIT4END here
This chain works fine in the mx23/mx28.
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
<1> For mxs-mmc driver, just use the new flags, do not change any logic.
<2> For gpmi-nand driver, and use the new flags to set the DMA
chain, especially for ecc read page.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-02-15 23:17:33 -07:00
|
|
|
sgl, sg_len, host->slave_dirn, flags);
|
2011-02-21 03:35:28 -07:00
|
|
|
if (desc) {
|
|
|
|
desc->callback = mxs_mmc_dma_irq_callback;
|
|
|
|
desc->callback_param = host;
|
|
|
|
} else {
|
|
|
|
if (data)
|
|
|
|
dma_unmap_sg(mmc_dev(host->mmc), data->sg,
|
|
|
|
data->sg_len, host->dma_dir);
|
|
|
|
}
|
|
|
|
|
|
|
|
return desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_bc(struct mxs_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_command *cmd = host->cmd;
|
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
u32 ctrl0, cmd0, cmd1;
|
|
|
|
|
|
|
|
ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
|
|
|
|
cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
|
|
|
|
cmd1 = cmd->arg;
|
|
|
|
|
|
|
|
if (host->sdio_irq_en) {
|
|
|
|
ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
|
|
|
|
cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
|
|
|
|
}
|
|
|
|
|
|
|
|
host->ssp_pio_words[0] = ctrl0;
|
|
|
|
host->ssp_pio_words[1] = cmd0;
|
|
|
|
host->ssp_pio_words[2] = cmd1;
|
|
|
|
host->dma_dir = DMA_NONE;
|
2011-12-13 08:48:04 -07:00
|
|
|
host->slave_dirn = DMA_TRANS_NONE;
|
mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^
|
|
set WAIT4END here
This chain works fine in the mx23/mx28.
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
<1> For mxs-mmc driver, just use the new flags, do not change any logic.
<2> For gpmi-nand driver, and use the new flags to set the DMA
chain, especially for ecc read page.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-02-15 23:17:33 -07:00
|
|
|
desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
|
2011-02-21 03:35:28 -07:00
|
|
|
if (!desc)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
dmaengine_submit(desc);
|
2012-04-10 23:29:31 -06:00
|
|
|
dma_async_issue_pending(host->dmach);
|
2011-02-21 03:35:28 -07:00
|
|
|
return;
|
|
|
|
|
|
|
|
out:
|
|
|
|
dev_warn(mmc_dev(host->mmc),
|
|
|
|
"%s: failed to prep dma\n", __func__);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_ac(struct mxs_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_command *cmd = host->cmd;
|
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
u32 ignore_crc, get_resp, long_resp;
|
|
|
|
u32 ctrl0, cmd0, cmd1;
|
|
|
|
|
|
|
|
ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
|
|
|
|
0 : BM_SSP_CTRL0_IGNORE_CRC;
|
|
|
|
get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
|
|
|
|
BM_SSP_CTRL0_GET_RESP : 0;
|
|
|
|
long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
|
|
|
|
BM_SSP_CTRL0_LONG_RESP : 0;
|
|
|
|
|
|
|
|
ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
|
|
|
|
cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
|
|
|
|
cmd1 = cmd->arg;
|
|
|
|
|
|
|
|
if (host->sdio_irq_en) {
|
|
|
|
ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
|
|
|
|
cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
|
|
|
|
}
|
|
|
|
|
|
|
|
host->ssp_pio_words[0] = ctrl0;
|
|
|
|
host->ssp_pio_words[1] = cmd0;
|
|
|
|
host->ssp_pio_words[2] = cmd1;
|
|
|
|
host->dma_dir = DMA_NONE;
|
2011-12-13 08:48:04 -07:00
|
|
|
host->slave_dirn = DMA_TRANS_NONE;
|
mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^
|
|
set WAIT4END here
This chain works fine in the mx23/mx28.
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
<1> For mxs-mmc driver, just use the new flags, do not change any logic.
<2> For gpmi-nand driver, and use the new flags to set the DMA
chain, especially for ecc read page.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-02-15 23:17:33 -07:00
|
|
|
desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
|
2011-02-21 03:35:28 -07:00
|
|
|
if (!desc)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
dmaengine_submit(desc);
|
2012-04-10 23:29:31 -06:00
|
|
|
dma_async_issue_pending(host->dmach);
|
2011-02-21 03:35:28 -07:00
|
|
|
return;
|
|
|
|
|
|
|
|
out:
|
|
|
|
dev_warn(mmc_dev(host->mmc),
|
|
|
|
"%s: failed to prep dma\n", __func__);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
|
|
|
|
{
|
|
|
|
const unsigned int ssp_timeout_mul = 4096;
|
|
|
|
/*
|
|
|
|
* Calculate ticks in ms since ns are large numbers
|
|
|
|
* and might overflow
|
|
|
|
*/
|
|
|
|
const unsigned int clock_per_ms = clock_rate / 1000;
|
|
|
|
const unsigned int ms = ns / 1000;
|
|
|
|
const unsigned int ticks = ms * clock_per_ms;
|
|
|
|
const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
|
|
|
|
|
|
|
|
WARN_ON(ssp_ticks == 0);
|
|
|
|
return ssp_ticks;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_adtc(struct mxs_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_command *cmd = host->cmd;
|
|
|
|
struct mmc_data *data = cmd->data;
|
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
struct scatterlist *sgl = data->sg, *sg;
|
|
|
|
unsigned int sg_len = data->sg_len;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
unsigned short dma_data_dir, timeout;
|
2011-10-13 23:15:11 -06:00
|
|
|
enum dma_transfer_direction slave_dirn;
|
2011-02-21 03:35:28 -07:00
|
|
|
unsigned int data_size = 0, log2_blksz;
|
|
|
|
unsigned int blocks = data->blocks;
|
|
|
|
|
|
|
|
u32 ignore_crc, get_resp, long_resp, read;
|
|
|
|
u32 ctrl0, cmd0, cmd1, val;
|
|
|
|
|
|
|
|
ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
|
|
|
|
0 : BM_SSP_CTRL0_IGNORE_CRC;
|
|
|
|
get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
|
|
|
|
BM_SSP_CTRL0_GET_RESP : 0;
|
|
|
|
long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
|
|
|
|
BM_SSP_CTRL0_LONG_RESP : 0;
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_WRITE) {
|
|
|
|
dma_data_dir = DMA_TO_DEVICE;
|
2011-10-13 23:15:11 -06:00
|
|
|
slave_dirn = DMA_MEM_TO_DEV;
|
2011-02-21 03:35:28 -07:00
|
|
|
read = 0;
|
|
|
|
} else {
|
|
|
|
dma_data_dir = DMA_FROM_DEVICE;
|
2011-10-13 23:15:11 -06:00
|
|
|
slave_dirn = DMA_DEV_TO_MEM;
|
2011-02-21 03:35:28 -07:00
|
|
|
read = BM_SSP_CTRL0_READ;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
|
|
|
|
ignore_crc | get_resp | long_resp |
|
|
|
|
BM_SSP_CTRL0_DATA_XFER | read |
|
|
|
|
BM_SSP_CTRL0_WAIT_FOR_IRQ |
|
|
|
|
BM_SSP_CTRL0_ENABLE;
|
|
|
|
|
|
|
|
cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
|
|
|
|
|
|
|
|
/* get logarithm to base 2 of block size for setting register */
|
|
|
|
log2_blksz = ilog2(data->blksz);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* take special care of the case that data size from data->sg
|
|
|
|
* is not equal to blocks x blksz
|
|
|
|
*/
|
|
|
|
for_each_sg(sgl, sg, sg_len, i)
|
|
|
|
data_size += sg->length;
|
|
|
|
|
|
|
|
if (data_size != data->blocks * data->blksz)
|
|
|
|
blocks = 1;
|
|
|
|
|
|
|
|
/* xfer count, block size and count need to be set differently */
|
2012-05-05 19:36:39 -06:00
|
|
|
if (ssp_is_old(host)) {
|
2011-02-21 03:35:28 -07:00
|
|
|
ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
|
|
|
|
cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
|
|
|
|
BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
|
|
|
|
} else {
|
|
|
|
writel(data_size, host->base + HW_SSP_XFER_SIZE);
|
|
|
|
writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
|
|
|
|
BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
|
|
|
|
host->base + HW_SSP_BLOCK_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
|
|
|
|
(cmd->opcode == SD_IO_RW_EXTENDED))
|
|
|
|
cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
|
|
|
|
|
|
|
|
cmd1 = cmd->arg;
|
|
|
|
|
|
|
|
if (host->sdio_irq_en) {
|
|
|
|
ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
|
|
|
|
cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set the timeout count */
|
|
|
|
timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
|
2012-05-05 19:36:39 -06:00
|
|
|
val = readl(host->base + HW_SSP_TIMING(host));
|
2011-02-21 03:35:28 -07:00
|
|
|
val &= ~(BM_SSP_TIMING_TIMEOUT);
|
|
|
|
val |= BF_SSP(timeout, TIMING_TIMEOUT);
|
2012-05-05 19:36:39 -06:00
|
|
|
writel(val, host->base + HW_SSP_TIMING(host));
|
2011-02-21 03:35:28 -07:00
|
|
|
|
|
|
|
/* pio */
|
|
|
|
host->ssp_pio_words[0] = ctrl0;
|
|
|
|
host->ssp_pio_words[1] = cmd0;
|
|
|
|
host->ssp_pio_words[2] = cmd1;
|
|
|
|
host->dma_dir = DMA_NONE;
|
2011-12-13 08:48:04 -07:00
|
|
|
host->slave_dirn = DMA_TRANS_NONE;
|
2011-02-21 03:35:28 -07:00
|
|
|
desc = mxs_mmc_prep_dma(host, 0);
|
|
|
|
if (!desc)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* append data sg */
|
|
|
|
WARN_ON(host->data != NULL);
|
|
|
|
host->data = data;
|
|
|
|
host->dma_dir = dma_data_dir;
|
2011-10-13 23:15:11 -06:00
|
|
|
host->slave_dirn = slave_dirn;
|
mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()
[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^
|
|
set WAIT4END here
This chain works fine in the mx23/mx28.
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
| |
| |
set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
<1> For mxs-mmc driver, just use the new flags, do not change any logic.
<2> For gpmi-nand driver, and use the new flags to set the DMA
chain, especially for ecc read page.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-02-15 23:17:33 -07:00
|
|
|
desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
2011-02-21 03:35:28 -07:00
|
|
|
if (!desc)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
dmaengine_submit(desc);
|
2012-04-10 23:29:31 -06:00
|
|
|
dma_async_issue_pending(host->dmach);
|
2011-02-21 03:35:28 -07:00
|
|
|
return;
|
|
|
|
out:
|
|
|
|
dev_warn(mmc_dev(host->mmc),
|
|
|
|
"%s: failed to prep dma\n", __func__);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
host->cmd = cmd;
|
|
|
|
|
|
|
|
switch (mmc_cmd_type(cmd)) {
|
|
|
|
case MMC_CMD_BC:
|
|
|
|
mxs_mmc_bc(host);
|
|
|
|
break;
|
|
|
|
case MMC_CMD_BCR:
|
|
|
|
mxs_mmc_ac(host);
|
|
|
|
break;
|
|
|
|
case MMC_CMD_AC:
|
|
|
|
mxs_mmc_ac(host);
|
|
|
|
break;
|
|
|
|
case MMC_CMD_ADTC:
|
|
|
|
mxs_mmc_adtc(host);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn(mmc_dev(host->mmc),
|
|
|
|
"%s: unknown MMC command\n", __func__);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
WARN_ON(host->mrq != NULL);
|
|
|
|
host->mrq = mrq;
|
|
|
|
mxs_mmc_start_cmd(host, mrq->cmd);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
|
|
|
|
{
|
2011-07-15 15:39:00 -06:00
|
|
|
unsigned int ssp_clk, ssp_sck;
|
|
|
|
u32 clock_divide, clock_rate;
|
2011-02-21 03:35:28 -07:00
|
|
|
u32 val;
|
|
|
|
|
2011-07-15 15:39:00 -06:00
|
|
|
ssp_clk = clk_get_rate(host->clk);
|
2011-02-21 03:35:28 -07:00
|
|
|
|
2011-07-15 15:39:00 -06:00
|
|
|
for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
|
|
|
|
clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
|
|
|
|
clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
|
|
|
|
if (clock_rate <= 255)
|
2011-02-21 03:35:28 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-07-15 15:39:00 -06:00
|
|
|
if (clock_divide > 254) {
|
2011-02-21 03:35:28 -07:00
|
|
|
dev_err(mmc_dev(host->mmc),
|
|
|
|
"%s: cannot set clock to %d\n", __func__, rate);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-07-15 15:39:00 -06:00
|
|
|
ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
|
2011-02-21 03:35:28 -07:00
|
|
|
|
2012-05-05 19:36:39 -06:00
|
|
|
val = readl(host->base + HW_SSP_TIMING(host));
|
2011-02-21 03:35:28 -07:00
|
|
|
val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
|
2011-07-15 15:39:00 -06:00
|
|
|
val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
|
|
|
|
val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
|
2012-05-05 19:36:39 -06:00
|
|
|
writel(val, host->base + HW_SSP_TIMING(host));
|
2011-02-21 03:35:28 -07:00
|
|
|
|
2011-07-15 15:39:00 -06:00
|
|
|
host->clk_rate = ssp_sck;
|
2011-02-21 03:35:28 -07:00
|
|
|
|
|
|
|
dev_dbg(mmc_dev(host->mmc),
|
2011-07-15 15:39:00 -06:00
|
|
|
"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
|
|
|
|
__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
|
2011-02-21 03:35:28 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
|
{
|
|
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_8)
|
|
|
|
host->bus_width = 2;
|
|
|
|
else if (ios->bus_width == MMC_BUS_WIDTH_4)
|
|
|
|
host->bus_width = 1;
|
|
|
|
else
|
|
|
|
host->bus_width = 0;
|
|
|
|
|
|
|
|
if (ios->clock)
|
|
|
|
mxs_mmc_set_clk_rate(host, ios->clock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
|
|
|
{
|
|
|
|
struct mxs_mmc_host *host = mmc_priv(mmc);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
host->sdio_irq_en = enable;
|
|
|
|
|
|
|
|
if (enable) {
|
|
|
|
writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
|
2012-05-05 05:40:09 -06:00
|
|
|
host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
2011-02-21 03:35:28 -07:00
|
|
|
writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
|
2012-05-05 19:36:39 -06:00
|
|
|
host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
|
2011-02-21 03:35:28 -07:00
|
|
|
|
2012-05-05 19:36:39 -06:00
|
|
|
if (readl(host->base + HW_SSP_STATUS(host)) &
|
|
|
|
BM_SSP_STATUS_SDIO_IRQ)
|
2011-02-21 03:35:28 -07:00
|
|
|
mmc_signal_sdio_irq(host->mmc);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
|
2012-05-05 05:40:09 -06:00
|
|
|
host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
2011-02-21 03:35:28 -07:00
|
|
|
writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
|
2012-05-05 19:36:39 -06:00
|
|
|
host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
|
2011-02-21 03:35:28 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct mmc_host_ops mxs_mmc_ops = {
|
|
|
|
.request = mxs_mmc_request,
|
|
|
|
.get_ro = mxs_mmc_get_ro,
|
|
|
|
.get_cd = mxs_mmc_get_cd,
|
|
|
|
.set_ios = mxs_mmc_set_ios,
|
|
|
|
.enable_sdio_irq = mxs_mmc_enable_sdio_irq,
|
|
|
|
};
|
|
|
|
|
|
|
|
static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
|
|
|
|
{
|
|
|
|
struct mxs_mmc_host *host = param;
|
|
|
|
|
|
|
|
if (!mxs_dma_is_apbh(chan))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (chan->chan_id != host->dma_res->start)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
chan->private = &host->dma_data;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-05-05 06:24:01 -06:00
|
|
|
static struct platform_device_id mxs_mmc_ids[] = {
|
|
|
|
{
|
|
|
|
.name = "imx23-mmc",
|
|
|
|
.driver_data = IMX23_MMC,
|
|
|
|
}, {
|
|
|
|
.name = "imx28-mmc",
|
|
|
|
.driver_data = IMX28_MMC,
|
|
|
|
}, {
|
|
|
|
/* sentinel */
|
|
|
|
}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
|
|
|
|
|
2011-02-21 03:35:28 -07:00
|
|
|
static int mxs_mmc_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct mxs_mmc_host *host;
|
|
|
|
struct mmc_host *mmc;
|
2012-05-05 21:20:40 -06:00
|
|
|
struct resource *iores, *dmares;
|
2011-02-21 03:35:28 -07:00
|
|
|
struct mxs_mmc_platform_data *pdata;
|
2012-05-06 08:56:16 -06:00
|
|
|
struct pinctrl *pinctrl;
|
2011-02-21 03:35:28 -07:00
|
|
|
int ret = 0, irq_err, irq_dma;
|
|
|
|
dma_cap_mask_t mask;
|
|
|
|
|
|
|
|
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
|
|
irq_err = platform_get_irq(pdev, 0);
|
|
|
|
irq_dma = platform_get_irq(pdev, 1);
|
|
|
|
if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
|
2012-05-05 21:20:40 -06:00
|
|
|
if (!mmc)
|
|
|
|
return -ENOMEM;
|
2011-02-21 03:35:28 -07:00
|
|
|
|
|
|
|
host = mmc_priv(mmc);
|
2012-05-05 21:20:40 -06:00
|
|
|
host->base = devm_request_and_ioremap(&pdev->dev, iores);
|
2011-02-21 03:35:28 -07:00
|
|
|
if (!host->base) {
|
2012-05-05 21:20:40 -06:00
|
|
|
ret = -EADDRNOTAVAIL;
|
2011-02-21 03:35:28 -07:00
|
|
|
goto out_mmc_free;
|
|
|
|
}
|
|
|
|
|
2012-05-05 06:24:01 -06:00
|
|
|
host->devid = pdev->id_entry->driver_data;
|
2011-02-21 03:35:28 -07:00
|
|
|
host->mmc = mmc;
|
|
|
|
host->dma_res = dmares;
|
|
|
|
host->sdio_irq_en = 0;
|
|
|
|
|
2012-05-06 08:56:16 -06:00
|
|
|
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
|
|
|
if (IS_ERR(pinctrl)) {
|
|
|
|
ret = PTR_ERR(pinctrl);
|
|
|
|
goto out_iounmap;
|
|
|
|
}
|
|
|
|
|
2011-02-21 03:35:28 -07:00
|
|
|
host->clk = clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(host->clk)) {
|
|
|
|
ret = PTR_ERR(host->clk);
|
2012-05-05 21:20:40 -06:00
|
|
|
goto out_mmc_free;
|
2011-02-21 03:35:28 -07:00
|
|
|
}
|
2011-12-19 22:57:41 -07:00
|
|
|
clk_prepare_enable(host->clk);
|
2011-02-21 03:35:28 -07:00
|
|
|
|
|
|
|
mxs_mmc_reset(host);
|
|
|
|
|
|
|
|
dma_cap_zero(mask);
|
|
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
host->dma_data.chan_irq = irq_dma;
|
|
|
|
host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
|
|
|
|
if (!host->dmach) {
|
|
|
|
dev_err(mmc_dev(host->mmc),
|
|
|
|
"%s: failed to request dma\n", __func__);
|
|
|
|
goto out_clk_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set mmc core parameters */
|
|
|
|
mmc->ops = &mxs_mmc_ops;
|
|
|
|
mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
|
|
|
|
MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
|
|
|
|
|
|
|
|
pdata = mmc_dev(host->mmc)->platform_data;
|
|
|
|
if (pdata) {
|
|
|
|
if (pdata->flags & SLOTF_8_BIT_CAPABLE)
|
|
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
|
|
|
|
if (pdata->flags & SLOTF_4_BIT_CAPABLE)
|
|
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
|
|
}
|
|
|
|
|
|
|
|
mmc->f_min = 400000;
|
|
|
|
mmc->f_max = 288000000;
|
|
|
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
|
|
|
|
mmc->max_segs = 52;
|
|
|
|
mmc->max_blk_size = 1 << 0xf;
|
2012-05-05 19:36:39 -06:00
|
|
|
mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
|
|
|
|
mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
|
2011-02-21 03:35:28 -07:00
|
|
|
mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, mmc);
|
|
|
|
|
2012-05-05 21:20:40 -06:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
|
|
|
|
DRIVER_NAME, host);
|
2011-02-21 03:35:28 -07:00
|
|
|
if (ret)
|
|
|
|
goto out_free_dma;
|
|
|
|
|
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
|
|
|
|
ret = mmc_add_host(mmc);
|
|
|
|
if (ret)
|
2012-05-05 21:20:40 -06:00
|
|
|
goto out_free_dma;
|
2011-02-21 03:35:28 -07:00
|
|
|
|
|
|
|
dev_info(mmc_dev(host->mmc), "initialized\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_free_dma:
|
|
|
|
if (host->dmach)
|
|
|
|
dma_release_channel(host->dmach);
|
|
|
|
out_clk_put:
|
2011-12-19 22:57:41 -07:00
|
|
|
clk_disable_unprepare(host->clk);
|
2011-02-21 03:35:28 -07:00
|
|
|
clk_put(host->clk);
|
|
|
|
out_mmc_free:
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxs_mmc_remove(struct platform_device *pdev)
|
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{
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struct mmc_host *mmc = platform_get_drvdata(pdev);
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struct mxs_mmc_host *host = mmc_priv(mmc);
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mmc_remove_host(mmc);
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platform_set_drvdata(pdev, NULL);
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if (host->dmach)
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dma_release_channel(host->dmach);
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2011-12-19 22:57:41 -07:00
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clk_disable_unprepare(host->clk);
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2011-02-21 03:35:28 -07:00
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clk_put(host->clk);
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mmc_free_host(mmc);
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return 0;
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}
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#ifdef CONFIG_PM
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static int mxs_mmc_suspend(struct device *dev)
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{
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struct mmc_host *mmc = dev_get_drvdata(dev);
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struct mxs_mmc_host *host = mmc_priv(mmc);
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int ret = 0;
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ret = mmc_suspend_host(mmc);
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2011-12-19 22:57:41 -07:00
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clk_disable_unprepare(host->clk);
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2011-02-21 03:35:28 -07:00
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return ret;
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}
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static int mxs_mmc_resume(struct device *dev)
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{
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struct mmc_host *mmc = dev_get_drvdata(dev);
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struct mxs_mmc_host *host = mmc_priv(mmc);
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int ret = 0;
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2011-12-19 22:57:41 -07:00
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clk_prepare_enable(host->clk);
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2011-02-21 03:35:28 -07:00
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ret = mmc_resume_host(mmc);
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return ret;
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}
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static const struct dev_pm_ops mxs_mmc_pm_ops = {
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.suspend = mxs_mmc_suspend,
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.resume = mxs_mmc_resume,
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};
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#endif
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static struct platform_driver mxs_mmc_driver = {
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.probe = mxs_mmc_probe,
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.remove = mxs_mmc_remove,
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2012-05-05 06:24:01 -06:00
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.id_table = mxs_mmc_ids,
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2011-02-21 03:35:28 -07:00
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.driver = {
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
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#ifdef CONFIG_PM
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.pm = &mxs_mmc_pm_ops,
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#endif
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},
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};
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2011-11-25 21:55:43 -07:00
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module_platform_driver(mxs_mmc_driver);
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2011-02-21 03:35:28 -07:00
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MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
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MODULE_AUTHOR("Freescale Semiconductor");
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MODULE_LICENSE("GPL");
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