2019-10-16 06:48:26 -06:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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2015-06-04 03:03:42 -06:00
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* Copyright 2016-2017,2019 NXP
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2019-10-16 06:48:26 -06:00
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*/
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/dts-v1/;
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#include "s32v234.dtsi"
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/ {
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model = "NXP S32V234-EVB2 Board";
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compatible = "fsl,s32v234-evb", "fsl,s32v234";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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2015-11-03 08:25:46 -07:00
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&can0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0>;
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "okay";
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};
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2015-08-21 02:14:11 -06:00
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&siul2 {
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status = "okay";
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2015-09-17 09:52:09 -06:00
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s32v234-evb {
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/* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the
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* IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference
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* Manual states.
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*/
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2015-11-03 08:25:46 -07:00
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pinctrl_can0: can0grp {
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fsl,pins = <
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S32V234_PAD_PA2__CAN_FD0_TXD
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S32V234_PAD_PA3__CAN_FD0_RXD_OUT
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S32V234_PAD_PA3__CAN_FD0_RXD_IN
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>;
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};
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pinctrl_can1: can1grp {
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fsl,pins = <
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S32V234_PAD_PA4__CAN_FD1_TXD
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S32V234_PAD_PA5__CAN_FD1_RXD_OUT
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S32V234_PAD_PA5__CAN_FD1_RXD_IN
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>;
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};
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2015-09-17 09:52:09 -06:00
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pinctrl_uart0: uart0grp {
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fsl,pins = <
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2015-09-17 09:52:09 -06:00
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S32V234_PAD_PA12__UART0_TXD
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S32V234_PAD_PA11__UART0_RXD_OUT
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S32V234_PAD_PA11__UART0_RXD_IN
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2015-09-17 09:52:09 -06:00
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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2015-09-17 09:52:09 -06:00
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S32V234_PAD_PA14__UART1_TXD
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S32V234_PAD_PA13__UART1_RXD_OUT
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S32V234_PAD_PA13__UART1_RXD_IN
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2015-09-17 09:52:09 -06:00
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>;
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};
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2015-09-17 09:52:09 -06:00
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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S32V234_PAD_PK6__USDHC_CLK_OUT
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S32V234_PAD_PK6__USDHC_CLK_IN
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S32V234_PAD_PK7__USDHC_CMD_OUT
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S32V234_PAD_PK7__USDHC_CMD_IN
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S32V234_PAD_PK8__USDHC_DAT0_OUT
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S32V234_PAD_PK8__USDHC_DAT0_IN
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S32V234_PAD_PK9__USDHC_DAT1_OUT
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S32V234_PAD_PK9__USDHC_DAT1_IN
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S32V234_PAD_PK10__USDHC_DAT2_OUT
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S32V234_PAD_PK10__USDHC_DAT2_IN
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S32V234_PAD_PK11__USDHC_DAT3_OUT
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S32V234_PAD_PK11__USDHC_DAT3_IN
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S32V234_PAD_PK15__USDHC_DAT4_OUT
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S32V234_PAD_PK15__USDHC_DAT4_IN
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S32V234_PAD_PL0__USDHC_DAT5_OUT
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S32V234_PAD_PL0__USDHC_DAT5_IN
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S32V234_PAD_PL1__USDHC_DAT6_OUT
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S32V234_PAD_PL1__USDHC_DAT6_IN
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S32V234_PAD_PL2__USDHC_DAT7_OUT
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S32V234_PAD_PL2__USDHC_DAT7_IN
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2015-09-17 09:52:09 -06:00
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>;
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};
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2015-09-17 09:52:09 -06:00
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};
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2015-08-21 02:14:11 -06:00
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};
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2019-10-16 06:48:26 -06:00
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&uart0 {
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2015-09-17 09:52:09 -06:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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2019-10-16 06:48:26 -06:00
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status = "okay";
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};
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&uart1 {
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2015-09-17 09:52:09 -06:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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2019-10-16 06:48:26 -06:00
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status = "okay";
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};
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2015-06-04 03:03:42 -06:00
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&usdhc0 {
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no-1-8-v;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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status = "okay";
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};
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