2005-09-26 00:04:21 -06:00
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/*
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* FPU support code, moved here from head.S so that it can be used
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* by chips which use other head-whatever.S files.
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*
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2006-08-29 22:45:35 -06:00
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Copyright (C) 1996 Paul Mackerras.
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* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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2005-09-26 00:04:21 -06:00
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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2005-10-10 06:20:10 -06:00
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#include <asm/reg.h>
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2005-09-26 00:04:21 -06:00
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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2010-11-18 08:06:17 -07:00
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#include <asm/ptrace.h>
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2016-01-13 21:33:46 -07:00
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#include <asm/export.h>
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2018-07-05 10:24:57 -06:00
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#include <asm/asm-compat.h>
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2018-07-05 10:25:01 -06:00
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#include <asm/feature-fixups.h>
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2005-09-26 00:04:21 -06:00
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2008-06-24 22:07:18 -06:00
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#ifdef CONFIG_VSX
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2012-06-25 07:33:23 -06:00
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#define __REST_32FPVSRS(n,c,base) \
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2008-06-24 22:07:18 -06:00
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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2012-06-25 07:33:23 -06:00
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#define __SAVE_32FPVSRS(n,c,base) \
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2008-06-24 22:07:18 -06:00
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS(n,base); \
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b 3f; \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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2012-06-25 07:33:23 -06:00
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#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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2008-06-24 22:07:18 -06:00
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#endif
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2012-06-25 07:33:23 -06:00
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#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
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#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
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2008-06-24 22:07:18 -06:00
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2013-09-10 04:21:10 -06:00
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/*
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* Load state from memory into FP registers including FPSCR.
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(load_fp_state)
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lfd fr0,FPSTATE_FPSCR(r3)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R3)
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blr
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2016-01-13 21:33:46 -07:00
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EXPORT_SYMBOL(load_fp_state)
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powerpc/64: Don't trace code that runs with the soft irq mask unreconciled
"Reconciling" in terms of interrupt handling, is to bring the soft irq
mask state in to synch with the hardware, after an interrupt causes
MSR[EE] to be cleared (while the soft mask may be enabled, and hard
irqs not marked disabled).
General kernel code should not be called while unreconciled, because
local_irq_disable, etc. manipulations can cause surprising irq traces,
and it's fragile because the soft irq code does not really expect to
be called in this situation.
When exiting from an interrupt, MSR[EE] is cleared to prevent races,
but soft irq state is enabled for the returned-to context, so this is
now an unreconciled state. restore_math is called in this state, and
that can be ftraced, and the ftrace subsystem disables local irqs.
Mark restore_math and its callees as notrace. Restore a sanity check
in the soft irq code that had to be disabled for this case, by commit
4da1f79227ad4 ("powerpc/64: Disable irq restore warning for now").
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-05-01 23:21:07 -06:00
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_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */
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2013-09-10 04:21:10 -06:00
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/*
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* Store FP state into memory, including FPSCR
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(store_fp_state)
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SAVE_32FPVSRS(0, R4, R3)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r3)
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blr
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2016-01-13 21:33:46 -07:00
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EXPORT_SYMBOL(store_fp_state)
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2013-09-10 04:21:10 -06:00
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2005-09-26 00:04:21 -06:00
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Load up this task's FP registers from its thread_struct,
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* enable the FPU for the current task and return to the task.
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2013-10-23 02:40:02 -06:00
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* Note that on 32-bit this can only use registers that will be
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* restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
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2005-09-26 00:04:21 -06:00
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*/
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2005-10-05 18:59:19 -06:00
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_GLOBAL(load_up_fpu)
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2005-09-26 00:04:21 -06:00
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mfmsr r5
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ori r5,r5,MSR_FP
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2008-06-24 22:07:18 -06:00
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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2005-09-26 00:04:21 -06:00
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SYNC
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MTMSRD(r5) /* enable use of fpu now */
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isync
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/* enable use of FP after return */
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2005-10-05 18:59:19 -06:00
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#ifdef CONFIG_PPC32
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2013-09-10 04:20:42 -06:00
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mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
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2005-09-26 00:04:21 -06:00
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r9,r9,MSR_FP /* enable FP for current */
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or r9,r9,r4
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2005-10-05 18:59:19 -06:00
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#else
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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2006-02-06 19:55:30 -07:00
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lwz r4,THREAD_FPEXC_MODE(r5)
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2005-10-05 18:59:19 -06:00
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ori r12,r12,MSR_FP
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or r12,r12,r4
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std r12,_MSR(r1)
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#endif
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2016-02-28 23:53:47 -07:00
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/* Don't care if r4 overflows, this is desired behaviour */
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lbz r4,THREAD_LOAD_FP(r5)
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addi r4,r4,1
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stb r4,THREAD_LOAD_FP(r5)
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2013-10-23 02:40:02 -06:00
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addi r10,r5,THREAD_FPSTATE
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lfd fr0,FPSTATE_FPSCR(r10)
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2006-06-10 04:18:39 -06:00
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MTFSF_L(fr0)
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2013-10-23 02:40:02 -06:00
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REST_32FPVSRS(0, R4, R10)
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2005-09-26 00:04:21 -06:00
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/* restore registers and return */
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/* we haven't used ctr or xer or lr */
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2008-06-24 22:07:18 -06:00
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blr
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2005-09-26 00:04:21 -06:00
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/*
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2016-02-28 23:53:49 -07:00
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* save_fpu(tsk)
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* Save the floating-point registers in its thread_struct.
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2005-09-26 00:04:21 -06:00
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* Enables the FPU for use in the kernel on return.
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*/
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2016-02-28 23:53:49 -07:00
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_GLOBAL(save_fpu)
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2005-09-26 00:04:21 -06:00
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addi r3,r3,THREAD /* want THREAD of task */
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2013-09-10 04:21:10 -06:00
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PPC_LL r6,THREAD_FPSAVEAREA(r3)
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[PATCH] powerpc: Consolidate asm compatibility macros
This patch consolidates macros used to generate assembly for
compatibility across different CPUs or configs. A new header,
asm-powerpc/asm-compat.h contains the main compatibility macros. It
uses some preprocessor magic to make the macros suitable both for use
in .S files, and in inline asm in .c files. Headers (bitops.h,
uaccess.h, atomic.h, bug.h) which had their own such compatibility
macros are changed to use asm-compat.h.
ppc_asm.h is now for use in .S files *only*, and a #error enforces
that. As such, we're a lot more careless about namespace pollution
here than in asm-compat.h.
While we're at it, this patch adds a call to the PPC405_ERR77 macro in
futex.h which should have had it already, but didn't.
Built and booted on pSeries, Maple and iSeries (ARCH=powerpc). Built
for 32-bit powermac (ARCH=powerpc) and Walnut (ARCH=ppc).
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-09 18:56:55 -07:00
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PPC_LL r5,PT_REGS(r3)
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2013-09-10 04:21:10 -06:00
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PPC_LCMPI 0,r6,0
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bne 2f
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2013-09-10 04:20:42 -06:00
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addi r6,r3,THREAD_FPSTATE
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2016-02-28 23:53:49 -07:00
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2: SAVE_32FPVSRS(0, R4, R6)
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2005-09-26 00:04:21 -06:00
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mffs fr0
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2013-09-10 04:20:42 -06:00
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stfd fr0,FPSTATE_FPSCR(r6)
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2005-09-26 00:04:21 -06:00
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blr
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[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 00:27:25 -06:00
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/*
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* These are used in the alignment trap handler when emulating
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* single-precision loads and stores.
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*/
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_GLOBAL(cvt_fd)
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lfs 0,0(r3)
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stfd 0,0(r4)
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blr
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_GLOBAL(cvt_df)
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lfd 0,0(r3)
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stfs 0,0(r4)
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blr
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