2005-04-16 16:20:36 -06:00
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/*
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* linux/arch/m32r/kernel/sys_m32r.c
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*
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* This file contains various random system calls that
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* have a non-standard calling sequence on the Linux/M32R platform.
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*
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* Taken from i386 version.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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2007-07-30 07:00:47 -06:00
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#include <linux/fs.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/smp.h>
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#include <linux/sem.h>
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#include <linux/msg.h>
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#include <linux/shm.h>
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#include <linux/stat.h>
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#include <linux/syscalls.h>
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#include <linux/mman.h>
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#include <linux/file.h>
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#include <linux/utsname.h>
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2007-10-17 00:29:24 -06:00
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#include <linux/ipc.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/uaccess.h>
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#include <asm/cachectl.h>
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#include <asm/cacheflush.h>
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2006-10-02 03:18:34 -06:00
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#include <asm/syscall.h>
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#include <asm/unistd.h>
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2005-04-16 16:20:36 -06:00
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/*
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* sys_tas() - test-and-set
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*/
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2006-10-11 10:24:55 -06:00
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asmlinkage int sys_tas(int __user *addr)
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2005-04-16 16:20:36 -06:00
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{
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int oldval;
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if (!access_ok(VERIFY_WRITE, addr, sizeof (int)))
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return -EFAULT;
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[PATCH] m32r: update sys_tas() routine
This patch updates and fixes sys_tas() routine for m32r.
In the previous implementation, a lockup rarely caused at sys_tas()
routine in SMP environment.
> > The problem is that touching *addr will generate an oops if that page isn't
> > paged in. If we convert it to use get_user() then that's an improvement,
> > but we must not run get_user() under spinlock or local_irq_disable().
I rewrote sys_tas() routine by using "lock -> unlock" instructions, and
utilizing the m32r's interrupt handling characteristics; the m32r processor
can accept interrupts only at the 32-bit instruction boundary. So, the
"unlock" instruction can be executed continuously after the "lock"
instruction execution without any interruptions.
In addition, to solve such a page_fault problem, I use a fixup code like
get_user().
And, as for the kernel lockup problem, we found that a calling
do_page_fault() routine with disabling interrupts might cause a lockup at
flush_tlb_others(), because we checked a completion of IPI handler's
operations in a spin-locked critical section.
Therefore, by using "lock -> unlock" code, we can implement the sys_tas()
rouitine without disabling interrupts explicitly, then no lockups would
happen at flush_tlb_others(), I hope.
Compile check and some working test in SMP environment have done.
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-20 19:28:17 -07:00
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/* atomic operation:
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* oldval = *addr; *addr = 1;
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*/
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r4", "%1")
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" .fillinsn\n"
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"1:\n"
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" lock %0, @%1 -> unlock %2, @%1\n"
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"2:\n"
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/* NOTE:
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* The m32r processor can accept interrupts only
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* at the 32-bit instruction boundary.
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* So, in the above code, the "unlock" instruction
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* can be executed continuously after the "lock"
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* instruction execution without any interruptions.
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*/
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".section .fixup,\"ax\"\n"
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" .balign 4\n"
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"3: ldi %0, #%3\n"
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" seth r14, #high(2b)\n"
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" or3 r14, r14, #low(2b)\n"
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" jmp r14\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .balign 4\n"
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" .long 1b,3b\n"
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".previous\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (1), "i"(-EFAULT)
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: "r14", "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r4"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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2005-04-16 16:20:36 -06:00
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return oldval;
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}
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asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
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{
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2007-10-19 17:14:39 -06:00
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/* This should flush more selectively ... */
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2005-04-16 16:20:36 -06:00
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_flush_cache_all();
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return 0;
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}
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asmlinkage int sys_cachectl(char *addr, int nbytes, int op)
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{
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/* Not implemented yet. */
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return -ENOSYS;
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}
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