[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
/*
|
2008-03-27 12:51:41 -06:00
|
|
|
* arch/arm/mach-orion5x/common.c
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
*
|
2008-03-27 12:51:41 -06:00
|
|
|
* Core functions for Marvell Orion 5x SoCs
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
*
|
|
|
|
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
|
|
|
|
*
|
2008-03-27 12:51:41 -06:00
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
2007-10-23 13:14:42 -06:00
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/serial_8250.h>
|
2008-03-27 12:51:39 -06:00
|
|
|
#include <linux/mbus.h>
|
2007-10-31 04:42:41 -06:00
|
|
|
#include <linux/mv643xx_eth.h>
|
2007-11-12 00:51:36 -07:00
|
|
|
#include <linux/mv643xx_i2c.h>
|
2008-03-27 12:51:39 -06:00
|
|
|
#include <linux/ata_platform.h>
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-28 22:55:06 -06:00
|
|
|
#include <linux/spi/orion_spi.h>
|
2008-09-25 08:23:48 -06:00
|
|
|
#include <net/dsa.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
#include <asm/page.h>
|
2008-02-29 13:12:57 -07:00
|
|
|
#include <asm/setup.h>
|
2007-10-23 13:14:42 -06:00
|
|
|
#include <asm/timex.h>
|
2008-02-29 13:12:57 -07:00
|
|
|
#include <asm/mach/arch.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
#include <asm/mach/map.h>
|
2008-03-27 12:51:40 -06:00
|
|
|
#include <asm/mach/time.h>
|
2008-08-05 09:14:15 -06:00
|
|
|
#include <mach/hardware.h>
|
|
|
|
#include <mach/orion5x.h>
|
2008-08-09 05:44:58 -06:00
|
|
|
#include <plat/ehci-orion.h>
|
2008-06-17 04:25:12 -06:00
|
|
|
#include <plat/mv_xor.h>
|
2008-08-09 05:44:58 -06:00
|
|
|
#include <plat/orion_nand.h>
|
2009-06-01 11:56:02 -06:00
|
|
|
#include <plat/orion_wdt.h>
|
2008-08-09 05:44:58 -06:00
|
|
|
#include <plat/time.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
#include "common.h"
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* I/O Address Mapping
|
|
|
|
****************************************************************************/
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct map_desc orion5x_io_desc[] __initdata = {
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
{
|
2008-03-27 12:51:41 -06:00
|
|
|
.virtual = ORION5X_REGS_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
|
|
|
|
.length = ORION5X_REGS_SIZE,
|
2008-05-10 08:30:01 -06:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 12:51:41 -06:00
|
|
|
.virtual = ORION5X_PCIE_IO_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCIE_IO_SIZE,
|
2008-05-10 08:30:01 -06:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 12:51:41 -06:00
|
|
|
.virtual = ORION5X_PCI_IO_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCI_IO_SIZE,
|
2008-05-10 08:30:01 -06:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 12:51:41 -06:00
|
|
|
.virtual = ORION5X_PCIE_WA_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCIE_WA_SIZE,
|
2008-05-10 08:30:01 -06:00
|
|
|
.type = MT_DEVICE,
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
void __init orion5x_map_io(void)
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
{
|
2008-03-27 12:51:41 -06:00
|
|
|
iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 13:14:41 -06:00
|
|
|
}
|
2007-10-23 13:14:42 -06:00
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
|
2007-10-23 13:14:42 -06:00
|
|
|
/*****************************************************************************
|
2008-04-21 21:37:12 -06:00
|
|
|
* EHCI
|
2007-10-23 13:14:42 -06:00
|
|
|
****************************************************************************/
|
2008-04-21 21:37:12 -06:00
|
|
|
static struct orion_ehci_data orion5x_ehci_data = {
|
|
|
|
.dram = &orion5x_mbus_dram_info,
|
2008-09-17 01:08:05 -06:00
|
|
|
.phy_version = EHCI_PHY_ORION,
|
2007-10-23 13:14:42 -06:00
|
|
|
};
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
static u64 ehci_dmamask = 0xffffffffUL;
|
2007-10-23 13:14:42 -06:00
|
|
|
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI0
|
|
|
|
****************************************************************************/
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct resource orion5x_ehci0_resources[] = {
|
2007-10-23 13:14:42 -06:00
|
|
|
{
|
2008-03-27 12:51:41 -06:00
|
|
|
.start = ORION5X_USB0_PHYS_BASE,
|
2008-04-25 14:30:21 -06:00
|
|
|
.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
|
2007-10-23 13:14:42 -06:00
|
|
|
.flags = IORESOURCE_MEM,
|
2008-05-10 08:30:01 -06:00
|
|
|
}, {
|
2008-03-27 12:51:41 -06:00
|
|
|
.start = IRQ_ORION5X_USB0_CTRL,
|
|
|
|
.end = IRQ_ORION5X_USB0_CTRL,
|
2007-10-23 13:14:42 -06:00
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct platform_device orion5x_ehci0 = {
|
2007-10-23 13:14:42 -06:00
|
|
|
.name = "orion-ehci",
|
|
|
|
.id = 0,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &ehci_dmamask,
|
|
|
|
.coherent_dma_mask = 0xffffffff,
|
2008-03-27 12:51:41 -06:00
|
|
|
.platform_data = &orion5x_ehci_data,
|
2007-10-23 13:14:42 -06:00
|
|
|
},
|
2008-03-27 12:51:41 -06:00
|
|
|
.resource = orion5x_ehci0_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
|
2007-10-23 13:14:42 -06:00
|
|
|
};
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
void __init orion5x_ehci0_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_ehci0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI1
|
|
|
|
****************************************************************************/
|
|
|
|
static struct resource orion5x_ehci1_resources[] = {
|
|
|
|
{
|
|
|
|
.start = ORION5X_USB1_PHYS_BASE,
|
|
|
|
.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_USB1_CTRL,
|
|
|
|
.end = IRQ_ORION5X_USB1_CTRL,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct platform_device orion5x_ehci1 = {
|
2007-10-23 13:14:42 -06:00
|
|
|
.name = "orion-ehci",
|
|
|
|
.id = 1,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &ehci_dmamask,
|
|
|
|
.coherent_dma_mask = 0xffffffff,
|
2008-03-27 12:51:41 -06:00
|
|
|
.platform_data = &orion5x_ehci_data,
|
2007-10-23 13:14:42 -06:00
|
|
|
},
|
2008-03-27 12:51:41 -06:00
|
|
|
.resource = orion5x_ehci1_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
|
2007-10-23 13:14:42 -06:00
|
|
|
};
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
void __init orion5x_ehci1_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_ehci1);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-10-31 04:42:41 -06:00
|
|
|
/*****************************************************************************
|
2008-04-21 21:37:12 -06:00
|
|
|
* GigE
|
2007-10-31 04:42:41 -06:00
|
|
|
****************************************************************************/
|
2008-04-26 12:48:11 -06:00
|
|
|
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
|
|
|
|
.dram = &orion5x_mbus_dram_info,
|
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct resource orion5x_eth_shared_resources[] = {
|
2007-10-31 04:42:41 -06:00
|
|
|
{
|
2008-03-27 12:51:41 -06:00
|
|
|
.start = ORION5X_ETH_PHYS_BASE + 0x2000,
|
|
|
|
.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
|
2007-10-31 04:42:41 -06:00
|
|
|
.flags = IORESOURCE_MEM,
|
2008-08-26 08:01:21 -06:00
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_ETH_ERR,
|
|
|
|
.end = IRQ_ORION5X_ETH_ERR,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
2007-10-31 04:42:41 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct platform_device orion5x_eth_shared = {
|
2007-10-31 04:42:41 -06:00
|
|
|
.name = MV643XX_ETH_SHARED_NAME,
|
|
|
|
.id = 0,
|
2008-04-26 12:48:11 -06:00
|
|
|
.dev = {
|
|
|
|
.platform_data = &orion5x_eth_shared_data,
|
|
|
|
},
|
2008-08-26 08:01:21 -06:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
|
2008-03-27 12:51:41 -06:00
|
|
|
.resource = orion5x_eth_shared_resources,
|
2007-10-31 04:42:41 -06:00
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct resource orion5x_eth_resources[] = {
|
2007-10-31 04:42:41 -06:00
|
|
|
{
|
|
|
|
.name = "eth irq",
|
2008-03-27 12:51:41 -06:00
|
|
|
.start = IRQ_ORION5X_ETH_SUM,
|
|
|
|
.end = IRQ_ORION5X_ETH_SUM,
|
2007-10-31 04:42:41 -06:00
|
|
|
.flags = IORESOURCE_IRQ,
|
2008-05-10 08:30:01 -06:00
|
|
|
},
|
2007-10-31 04:42:41 -06:00
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct platform_device orion5x_eth = {
|
2007-10-31 04:42:41 -06:00
|
|
|
.name = MV643XX_ETH_NAME,
|
|
|
|
.id = 0,
|
|
|
|
.num_resources = 1,
|
2008-03-27 12:51:41 -06:00
|
|
|
.resource = orion5x_eth_resources,
|
2009-05-22 14:53:40 -06:00
|
|
|
.dev = {
|
|
|
|
.coherent_dma_mask = 0xffffffff,
|
|
|
|
},
|
2007-10-31 04:42:41 -06:00
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
|
2007-10-31 04:42:41 -06:00
|
|
|
{
|
2008-04-23 17:27:02 -06:00
|
|
|
eth_data->shared = &orion5x_eth_shared;
|
2008-03-27 12:51:41 -06:00
|
|
|
orion5x_eth.dev.platform_data = eth_data;
|
2008-04-23 17:27:02 -06:00
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
platform_device_register(&orion5x_eth_shared);
|
|
|
|
platform_device_register(&orion5x_eth);
|
2007-10-31 04:42:41 -06:00
|
|
|
}
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
|
2008-09-25 08:23:48 -06:00
|
|
|
/*****************************************************************************
|
|
|
|
* Ethernet switch
|
|
|
|
****************************************************************************/
|
|
|
|
static struct resource orion5x_switch_resources[] = {
|
|
|
|
{
|
|
|
|
.start = 0,
|
|
|
|
.end = 0,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_switch_device = {
|
|
|
|
.name = "dsa",
|
|
|
|
.id = 0,
|
|
|
|
.num_resources = 0,
|
|
|
|
.resource = orion5x_switch_resources,
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
|
|
|
|
{
|
dsa: add switch chip cascading support
The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips. This patch adds support
for multiple switch chips on a network interface.
An example topology for a 16-port device with an embedded CPU is as
follows:
+-----+ +--------+ +--------+
| |eth0 10| switch |9 10| switch |
| CPU +----------+ +-------+ |
| | | chip 0 | | chip 1 |
+-----+ +---++---+ +---++---+
|| ||
|| ||
||1000baseT ||1000baseT
||ports 1-8 ||ports 9-16
This requires a couple of interdependent changes in the DSA layer:
- The dsa platform driver data needs to be extended: there is still
only one netdevice per DSA driver instance (eth0 in the example
above), but each of the switch chips in the tree needs its own
mii_bus device pointer, MII management bus address, and port name
array. (include/net/dsa.h) The existing in-tree dsa users need
some small changes to deal with this. (arch/arm)
- The DSA and Ethertype DSA tagging modules need to be extended to
use the DSA device ID field on receive and demultiplex the packet
accordingly, and fill in the DSA device ID field on transmit
according to which switch chip the packet is heading to.
(net/dsa/tag_{dsa,edsa}.c)
- The concept of "CPU port", which is the switch chip port that the
CPU is connected to (port 10 on switch chip 0 in the example), needs
to be extended with the concept of "upstream port", which is the
port on the switch chip that will bring us one hop closer to the CPU
(port 10 for both switch chips in the example above).
- The dsa platform data needs to specify which ports on which switch
chips are links to other switch chips, so that we can enable DSA
tagging mode on them. (For inter-switch links, we always use
non-EtherType DSA tagging, since it has lower overhead. The CPU
link uses dsa or edsa tagging depending on what the 'root' switch
chip supports.) This is done by specifying "dsa" for the given
port in the port array.
- The dsa platform data needs to be extended with information on via
which port to reach any given switch chip from any given switch chip.
This info is specified via the per-switch chip data struct ->rtable[]
array, which gives the nexthop ports for each of the other switches
in the tree.
For the example topology above, the dsa platform data would look
something like this:
static struct dsa_chip_data sw[2] = {
{
.mii_bus = &foo,
.sw_addr = 1,
.port_names[0] = "p1",
.port_names[1] = "p2",
.port_names[2] = "p3",
.port_names[3] = "p4",
.port_names[4] = "p5",
.port_names[5] = "p6",
.port_names[6] = "p7",
.port_names[7] = "p8",
.port_names[9] = "dsa",
.port_names[10] = "cpu",
.rtable = (s8 []){ -1, 9, },
}, {
.mii_bus = &foo,
.sw_addr = 2,
.port_names[0] = "p9",
.port_names[1] = "p10",
.port_names[2] = "p11",
.port_names[3] = "p12",
.port_names[4] = "p13",
.port_names[5] = "p14",
.port_names[6] = "p15",
.port_names[7] = "p16",
.port_names[10] = "dsa",
.rtable = (s8 []){ 10, -1, },
},
},
static struct dsa_platform_data pd = {
.netdev = &foo,
.nr_switches = 2,
.sw = sw,
};
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 03:52:09 -06:00
|
|
|
int i;
|
|
|
|
|
2008-09-25 08:23:48 -06:00
|
|
|
if (irq != NO_IRQ) {
|
|
|
|
orion5x_switch_resources[0].start = irq;
|
|
|
|
orion5x_switch_resources[0].end = irq;
|
|
|
|
orion5x_switch_device.num_resources = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
d->netdev = &orion5x_eth.dev;
|
dsa: add switch chip cascading support
The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips. This patch adds support
for multiple switch chips on a network interface.
An example topology for a 16-port device with an embedded CPU is as
follows:
+-----+ +--------+ +--------+
| |eth0 10| switch |9 10| switch |
| CPU +----------+ +-------+ |
| | | chip 0 | | chip 1 |
+-----+ +---++---+ +---++---+
|| ||
|| ||
||1000baseT ||1000baseT
||ports 1-8 ||ports 9-16
This requires a couple of interdependent changes in the DSA layer:
- The dsa platform driver data needs to be extended: there is still
only one netdevice per DSA driver instance (eth0 in the example
above), but each of the switch chips in the tree needs its own
mii_bus device pointer, MII management bus address, and port name
array. (include/net/dsa.h) The existing in-tree dsa users need
some small changes to deal with this. (arch/arm)
- The DSA and Ethertype DSA tagging modules need to be extended to
use the DSA device ID field on receive and demultiplex the packet
accordingly, and fill in the DSA device ID field on transmit
according to which switch chip the packet is heading to.
(net/dsa/tag_{dsa,edsa}.c)
- The concept of "CPU port", which is the switch chip port that the
CPU is connected to (port 10 on switch chip 0 in the example), needs
to be extended with the concept of "upstream port", which is the
port on the switch chip that will bring us one hop closer to the CPU
(port 10 for both switch chips in the example above).
- The dsa platform data needs to specify which ports on which switch
chips are links to other switch chips, so that we can enable DSA
tagging mode on them. (For inter-switch links, we always use
non-EtherType DSA tagging, since it has lower overhead. The CPU
link uses dsa or edsa tagging depending on what the 'root' switch
chip supports.) This is done by specifying "dsa" for the given
port in the port array.
- The dsa platform data needs to be extended with information on via
which port to reach any given switch chip from any given switch chip.
This info is specified via the per-switch chip data struct ->rtable[]
array, which gives the nexthop ports for each of the other switches
in the tree.
For the example topology above, the dsa platform data would look
something like this:
static struct dsa_chip_data sw[2] = {
{
.mii_bus = &foo,
.sw_addr = 1,
.port_names[0] = "p1",
.port_names[1] = "p2",
.port_names[2] = "p3",
.port_names[3] = "p4",
.port_names[4] = "p5",
.port_names[5] = "p6",
.port_names[6] = "p7",
.port_names[7] = "p8",
.port_names[9] = "dsa",
.port_names[10] = "cpu",
.rtable = (s8 []){ -1, 9, },
}, {
.mii_bus = &foo,
.sw_addr = 2,
.port_names[0] = "p9",
.port_names[1] = "p10",
.port_names[2] = "p11",
.port_names[3] = "p12",
.port_names[4] = "p13",
.port_names[5] = "p14",
.port_names[6] = "p15",
.port_names[7] = "p16",
.port_names[10] = "dsa",
.rtable = (s8 []){ 10, -1, },
},
},
static struct dsa_platform_data pd = {
.netdev = &foo,
.nr_switches = 2,
.sw = sw,
};
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 03:52:09 -06:00
|
|
|
for (i = 0; i < d->nr_chips; i++)
|
|
|
|
d->chip[i].mii_bus = &orion5x_eth_shared.dev;
|
2008-09-25 08:23:48 -06:00
|
|
|
orion5x_switch_device.dev.platform_data = d;
|
|
|
|
|
|
|
|
platform_device_register(&orion5x_switch_device);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-11-12 00:51:36 -07:00
|
|
|
/*****************************************************************************
|
2008-04-21 21:37:12 -06:00
|
|
|
* I2C
|
2007-11-12 00:51:36 -07:00
|
|
|
****************************************************************************/
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
|
2007-11-12 00:51:36 -07:00
|
|
|
.freq_m = 8, /* assumes 166 MHz TCLK */
|
|
|
|
.freq_n = 3,
|
|
|
|
.timeout = 1000, /* Default timeout of 1 second */
|
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct resource orion5x_i2c_resources[] = {
|
2007-11-12 00:51:36 -07:00
|
|
|
{
|
2008-05-10 08:30:01 -06:00
|
|
|
.start = I2C_PHYS_BASE,
|
2008-04-21 21:37:12 -06:00
|
|
|
.end = I2C_PHYS_BASE + 0x1f,
|
2008-05-10 08:30:01 -06:00
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_I2C,
|
|
|
|
.end = IRQ_ORION5X_I2C,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
2007-11-12 00:51:36 -07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct platform_device orion5x_i2c = {
|
2007-11-12 00:51:36 -07:00
|
|
|
.name = MV64XXX_I2C_CTLR_NAME,
|
|
|
|
.id = 0,
|
2008-03-27 12:51:41 -06:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
|
|
|
|
.resource = orion5x_i2c_resources,
|
2007-11-12 00:51:36 -07:00
|
|
|
.dev = {
|
2008-05-10 08:30:01 -06:00
|
|
|
.platform_data = &orion5x_i2c_pdata,
|
2007-11-12 00:51:36 -07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
void __init orion5x_i2c_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_i2c);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-01-29 15:33:32 -07:00
|
|
|
/*****************************************************************************
|
2008-04-21 21:37:12 -06:00
|
|
|
* SATA
|
2008-01-29 15:33:32 -07:00
|
|
|
****************************************************************************/
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct resource orion5x_sata_resources[] = {
|
2008-01-29 15:33:32 -07:00
|
|
|
{
|
2008-05-10 08:30:01 -06:00
|
|
|
.name = "sata base",
|
|
|
|
.start = ORION5X_SATA_PHYS_BASE,
|
|
|
|
.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "sata irq",
|
|
|
|
.start = IRQ_ORION5X_SATA,
|
|
|
|
.end = IRQ_ORION5X_SATA,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
2008-01-29 15:33:32 -07:00
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static struct platform_device orion5x_sata = {
|
2008-05-10 08:30:01 -06:00
|
|
|
.name = "sata_mv",
|
|
|
|
.id = 0,
|
2008-01-29 15:33:32 -07:00
|
|
|
.dev = {
|
|
|
|
.coherent_dma_mask = 0xffffffff,
|
|
|
|
},
|
2008-05-10 08:30:01 -06:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_sata_resources),
|
|
|
|
.resource = orion5x_sata_resources,
|
2008-01-29 15:33:32 -07:00
|
|
|
};
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
|
2008-01-29 15:33:32 -07:00
|
|
|
{
|
2008-03-27 12:51:41 -06:00
|
|
|
sata_data->dram = &orion5x_mbus_dram_info;
|
|
|
|
orion5x_sata.dev.platform_data = sata_data;
|
|
|
|
platform_device_register(&orion5x_sata);
|
2008-01-29 15:33:32 -07:00
|
|
|
}
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-28 22:55:06 -06:00
|
|
|
/*****************************************************************************
|
|
|
|
* SPI
|
|
|
|
****************************************************************************/
|
|
|
|
static struct orion_spi_info orion5x_spi_plat_data = {
|
2008-10-19 12:18:25 -06:00
|
|
|
.tclk = 0,
|
|
|
|
.enable_clock_fix = 1,
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-28 22:55:06 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource orion5x_spi_resources[] = {
|
|
|
|
{
|
|
|
|
.name = "spi base",
|
|
|
|
.start = SPI_PHYS_BASE,
|
|
|
|
.end = SPI_PHYS_BASE + 0x1f,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_spi = {
|
|
|
|
.name = "orion_spi",
|
|
|
|
.id = 0,
|
|
|
|
.dev = {
|
|
|
|
.platform_data = &orion5x_spi_plat_data,
|
|
|
|
},
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_spi_resources),
|
|
|
|
.resource = orion5x_spi_resources,
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_spi_init()
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_spi);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-03-27 12:51:40 -06:00
|
|
|
/*****************************************************************************
|
2008-04-21 21:37:12 -06:00
|
|
|
* UART0
|
|
|
|
****************************************************************************/
|
|
|
|
static struct plat_serial8250_port orion5x_uart0_data[] = {
|
|
|
|
{
|
|
|
|
.mapbase = UART0_PHYS_BASE,
|
|
|
|
.membase = (char *)UART0_VIRT_BASE,
|
|
|
|
.irq = IRQ_ORION5X_UART0,
|
|
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
|
|
.iotype = UPIO_MEM,
|
|
|
|
.regshift = 2,
|
2008-08-28 21:55:51 -06:00
|
|
|
.uartclk = 0,
|
2008-04-21 21:37:12 -06:00
|
|
|
}, {
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource orion5x_uart0_resources[] = {
|
|
|
|
{
|
|
|
|
.start = UART0_PHYS_BASE,
|
|
|
|
.end = UART0_PHYS_BASE + 0xff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_UART0,
|
|
|
|
.end = IRQ_ORION5X_UART0,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_uart0 = {
|
|
|
|
.name = "serial8250",
|
|
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
|
|
.dev = {
|
|
|
|
.platform_data = orion5x_uart0_data,
|
|
|
|
},
|
|
|
|
.resource = orion5x_uart0_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_uart0_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_uart0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART1
|
2008-03-27 12:51:40 -06:00
|
|
|
****************************************************************************/
|
2008-04-21 21:37:12 -06:00
|
|
|
static struct plat_serial8250_port orion5x_uart1_data[] = {
|
|
|
|
{
|
|
|
|
.mapbase = UART1_PHYS_BASE,
|
|
|
|
.membase = (char *)UART1_VIRT_BASE,
|
|
|
|
.irq = IRQ_ORION5X_UART1,
|
|
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
|
|
.iotype = UPIO_MEM,
|
|
|
|
.regshift = 2,
|
2008-08-28 21:55:51 -06:00
|
|
|
.uartclk = 0,
|
2008-04-21 21:37:12 -06:00
|
|
|
}, {
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource orion5x_uart1_resources[] = {
|
|
|
|
{
|
|
|
|
.start = UART1_PHYS_BASE,
|
|
|
|
.end = UART1_PHYS_BASE + 0xff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_UART1,
|
|
|
|
.end = IRQ_ORION5X_UART1,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_uart1 = {
|
|
|
|
.name = "serial8250",
|
|
|
|
.id = PLAT8250_DEV_PLATFORM1,
|
|
|
|
.dev = {
|
|
|
|
.platform_data = orion5x_uart1_data,
|
|
|
|
},
|
|
|
|
.resource = orion5x_uart1_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_uart1_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_uart1);
|
|
|
|
}
|
2008-03-27 12:51:40 -06:00
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
|
2008-06-17 04:25:12 -06:00
|
|
|
/*****************************************************************************
|
|
|
|
* XOR engine
|
|
|
|
****************************************************************************/
|
2009-03-02 08:30:36 -07:00
|
|
|
struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
|
|
|
|
.dram = &orion5x_mbus_dram_info,
|
|
|
|
};
|
|
|
|
|
2008-06-17 04:25:12 -06:00
|
|
|
static struct resource orion5x_xor_shared_resources[] = {
|
|
|
|
{
|
|
|
|
.name = "xor low",
|
|
|
|
.start = ORION5X_XOR_PHYS_BASE,
|
|
|
|
.end = ORION5X_XOR_PHYS_BASE + 0xff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "xor high",
|
|
|
|
.start = ORION5X_XOR_PHYS_BASE + 0x200,
|
|
|
|
.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_xor_shared = {
|
|
|
|
.name = MV_XOR_SHARED_NAME,
|
|
|
|
.id = 0,
|
2009-03-02 08:30:36 -07:00
|
|
|
.dev = {
|
|
|
|
.platform_data = &orion5x_xor_shared_data,
|
|
|
|
},
|
2008-06-17 04:25:12 -06:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
|
|
|
|
.resource = orion5x_xor_shared_resources,
|
|
|
|
};
|
|
|
|
|
2009-04-06 20:01:15 -06:00
|
|
|
static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
|
2008-06-17 04:25:12 -06:00
|
|
|
|
|
|
|
static struct resource orion5x_xor0_resources[] = {
|
|
|
|
[0] = {
|
|
|
|
.start = IRQ_ORION5X_XOR0,
|
|
|
|
.end = IRQ_ORION5X_XOR0,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct mv_xor_platform_data orion5x_xor0_data = {
|
|
|
|
.shared = &orion5x_xor_shared,
|
|
|
|
.hw_id = 0,
|
|
|
|
.pool_size = PAGE_SIZE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_xor0_channel = {
|
|
|
|
.name = MV_XOR_NAME,
|
|
|
|
.id = 0,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
|
|
|
|
.resource = orion5x_xor0_resources,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &orion5x_xor_dmamask,
|
2009-04-06 20:01:13 -06:00
|
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
2008-06-17 04:25:12 -06:00
|
|
|
.platform_data = (void *)&orion5x_xor0_data,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource orion5x_xor1_resources[] = {
|
|
|
|
[0] = {
|
|
|
|
.start = IRQ_ORION5X_XOR1,
|
|
|
|
.end = IRQ_ORION5X_XOR1,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct mv_xor_platform_data orion5x_xor1_data = {
|
|
|
|
.shared = &orion5x_xor_shared,
|
|
|
|
.hw_id = 1,
|
|
|
|
.pool_size = PAGE_SIZE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_xor1_channel = {
|
|
|
|
.name = MV_XOR_NAME,
|
|
|
|
.id = 1,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
|
|
|
|
.resource = orion5x_xor1_resources,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &orion5x_xor_dmamask,
|
2009-04-06 20:01:13 -06:00
|
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
2008-06-17 04:25:12 -06:00
|
|
|
.platform_data = (void *)&orion5x_xor1_data,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_xor_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_xor_shared);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* two engines can't do memset simultaneously, this limitation
|
|
|
|
* satisfied by removing memset support from one of the engines.
|
|
|
|
*/
|
|
|
|
dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
|
|
|
|
dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
|
|
|
|
platform_device_register(&orion5x_xor0_channel);
|
|
|
|
|
|
|
|
dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
|
|
|
|
dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
|
|
|
|
dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
|
|
|
|
platform_device_register(&orion5x_xor1_channel);
|
|
|
|
}
|
|
|
|
|
2009-05-07 14:59:24 -06:00
|
|
|
static struct resource orion5x_crypto_res[] = {
|
|
|
|
{
|
|
|
|
.name = "regs",
|
|
|
|
.start = ORION5X_CRYPTO_PHYS_BASE,
|
|
|
|
.end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "sram",
|
|
|
|
.start = ORION5X_SRAM_PHYS_BASE,
|
|
|
|
.end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "crypto interrupt",
|
|
|
|
.start = IRQ_ORION5X_CESA,
|
|
|
|
.end = IRQ_ORION5X_CESA,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_crypto_device = {
|
|
|
|
.name = "mv_crypto",
|
|
|
|
.id = -1,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_crypto_res),
|
|
|
|
.resource = orion5x_crypto_res,
|
|
|
|
};
|
|
|
|
|
2009-06-11 14:27:20 -06:00
|
|
|
static int __init orion5x_crypto_init(void)
|
2009-05-07 14:59:24 -06:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = orion5x_setup_sram_win();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return platform_device_register(&orion5x_crypto_device);
|
|
|
|
}
|
2008-06-17 04:25:12 -06:00
|
|
|
|
2009-02-24 15:59:22 -07:00
|
|
|
/*****************************************************************************
|
|
|
|
* Watchdog
|
|
|
|
****************************************************************************/
|
2009-06-01 11:56:02 -06:00
|
|
|
static struct orion_wdt_platform_data orion5x_wdt_data = {
|
2009-02-24 15:59:22 -07:00
|
|
|
.tclk = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_wdt_device = {
|
2009-06-01 11:56:02 -06:00
|
|
|
.name = "orion_wdt",
|
2009-02-24 15:59:22 -07:00
|
|
|
.id = -1,
|
|
|
|
.dev = {
|
|
|
|
.platform_data = &orion5x_wdt_data,
|
|
|
|
},
|
|
|
|
.num_resources = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_wdt_init(void)
|
|
|
|
{
|
|
|
|
orion5x_wdt_data.tclk = orion5x_tclk;
|
|
|
|
platform_device_register(&orion5x_wdt_device);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
/*****************************************************************************
|
|
|
|
* Time handling
|
|
|
|
****************************************************************************/
|
2008-08-28 21:55:51 -06:00
|
|
|
int orion5x_tclk;
|
|
|
|
|
|
|
|
int __init orion5x_find_tclk(void)
|
|
|
|
{
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-28 22:55:06 -06:00
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
orion5x_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV88F6183_DEV_ID &&
|
|
|
|
(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
|
|
|
|
return 133333333;
|
|
|
|
|
2008-08-28 21:55:51 -06:00
|
|
|
return 166666667;
|
|
|
|
}
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
static void orion5x_timer_init(void)
|
2008-03-27 12:51:40 -06:00
|
|
|
{
|
2008-08-28 21:55:51 -06:00
|
|
|
orion5x_tclk = orion5x_find_tclk();
|
|
|
|
orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
|
2008-03-27 12:51:40 -06:00
|
|
|
}
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
struct sys_timer orion5x_timer = {
|
2008-05-10 08:30:01 -06:00
|
|
|
.init = orion5x_timer_init,
|
2008-03-27 12:51:40 -06:00
|
|
|
};
|
|
|
|
|
2008-04-21 21:37:12 -06:00
|
|
|
|
2007-10-23 13:14:42 -06:00
|
|
|
/*****************************************************************************
|
|
|
|
* General
|
|
|
|
****************************************************************************/
|
|
|
|
/*
|
2008-04-25 14:31:32 -06:00
|
|
|
* Identify device ID and rev from PCIe configuration header space '0'.
|
2007-10-23 13:14:42 -06:00
|
|
|
*/
|
2008-03-27 12:51:41 -06:00
|
|
|
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
|
2007-10-23 13:14:42 -06:00
|
|
|
{
|
2008-03-27 12:51:41 -06:00
|
|
|
orion5x_pcie_id(dev, rev);
|
2007-10-23 13:14:42 -06:00
|
|
|
|
|
|
|
if (*dev == MV88F5281_DEV_ID) {
|
|
|
|
if (*rev == MV88F5281_REV_D2) {
|
|
|
|
*dev_name = "MV88F5281-D2";
|
|
|
|
} else if (*rev == MV88F5281_REV_D1) {
|
|
|
|
*dev_name = "MV88F5281-D1";
|
2008-08-09 07:17:27 -06:00
|
|
|
} else if (*rev == MV88F5281_REV_D0) {
|
|
|
|
*dev_name = "MV88F5281-D0";
|
2007-10-23 13:14:42 -06:00
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5281-Rev-Unsupported";
|
|
|
|
}
|
|
|
|
} else if (*dev == MV88F5182_DEV_ID) {
|
|
|
|
if (*rev == MV88F5182_REV_A2) {
|
|
|
|
*dev_name = "MV88F5182-A2";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5182-Rev-Unsupported";
|
|
|
|
}
|
2007-11-11 04:05:11 -07:00
|
|
|
} else if (*dev == MV88F5181_DEV_ID) {
|
|
|
|
if (*rev == MV88F5181_REV_B1) {
|
|
|
|
*dev_name = "MV88F5181-Rev-B1";
|
2008-05-31 00:30:40 -06:00
|
|
|
} else if (*rev == MV88F5181L_REV_A1) {
|
|
|
|
*dev_name = "MV88F5181L-Rev-A1";
|
2007-11-11 04:05:11 -07:00
|
|
|
} else {
|
2008-05-31 00:30:40 -06:00
|
|
|
*dev_name = "MV88F5181(L)-Rev-Unsupported";
|
2007-11-11 04:05:11 -07:00
|
|
|
}
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-28 22:55:06 -06:00
|
|
|
} else if (*dev == MV88F6183_DEV_ID) {
|
|
|
|
if (*rev == MV88F6183_REV_B0) {
|
|
|
|
*dev_name = "MV88F6183-Rev-B0";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F6183-Rev-Unsupported";
|
|
|
|
}
|
2007-10-23 13:14:42 -06:00
|
|
|
} else {
|
|
|
|
*dev_name = "Device-Unknown";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
void __init orion5x_init(void)
|
2007-10-23 13:14:42 -06:00
|
|
|
{
|
|
|
|
char *dev_name;
|
|
|
|
u32 dev, rev;
|
|
|
|
|
2008-03-27 12:51:41 -06:00
|
|
|
orion5x_id(&dev, &rev, &dev_name);
|
2008-08-28 21:55:51 -06:00
|
|
|
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
|
|
|
|
|
|
|
|
orion5x_eth_shared_data.t_clk = orion5x_tclk;
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-28 22:55:06 -06:00
|
|
|
orion5x_spi_plat_data.tclk = orion5x_tclk;
|
2008-08-28 21:55:51 -06:00
|
|
|
orion5x_uart0_data[0].uartclk = orion5x_tclk;
|
|
|
|
orion5x_uart1_data[0].uartclk = orion5x_tclk;
|
2007-10-23 13:14:42 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup Orion address map
|
|
|
|
*/
|
2008-03-27 12:51:41 -06:00
|
|
|
orion5x_setup_cpu_mbus_bridge();
|
2008-08-09 07:17:27 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Don't issue "Wait for Interrupt" instruction if we are
|
|
|
|
* running on D0 5281 silicon.
|
|
|
|
*/
|
|
|
|
if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
|
|
|
|
printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
|
|
|
|
disable_hlt();
|
|
|
|
}
|
2009-02-24 15:59:22 -07:00
|
|
|
|
2009-06-11 14:27:20 -06:00
|
|
|
/*
|
|
|
|
* The 5082/5181l/5182/6082/6082l/6183 have crypto
|
|
|
|
* while 5180n/5181/5281 don't have crypto.
|
|
|
|
*/
|
|
|
|
if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
|
|
|
|
dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
|
|
|
|
orion5x_crypto_init();
|
|
|
|
|
2009-02-24 15:59:22 -07:00
|
|
|
/*
|
|
|
|
* Register watchdog driver
|
|
|
|
*/
|
|
|
|
orion5x_wdt_init();
|
2007-10-23 13:14:42 -06:00
|
|
|
}
|
2008-02-29 13:12:57 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Many orion-based systems have buggy bootloader implementations.
|
|
|
|
* This is a common fixup for bogus memory tags.
|
|
|
|
*/
|
|
|
|
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
|
|
|
|
char **from, struct meminfo *meminfo)
|
|
|
|
{
|
|
|
|
for (; t->hdr.size; t = tag_next(t))
|
|
|
|
if (t->hdr.tag == ATAG_MEM &&
|
|
|
|
(!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
|
|
|
|
t->u.mem.start & ~PAGE_MASK)) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"Clearing invalid memory bank %dKB@0x%08x\n",
|
|
|
|
t->u.mem.size / 1024, t->u.mem.start);
|
|
|
|
t->hdr.tag = 0;
|
|
|
|
}
|
|
|
|
}
|