2008-04-10 06:31:47 -06:00
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/*
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* linux/arch/arm/mach-sa1100/gpio.c
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*
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* Generic SA-1100 GPIO handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2011-07-26 03:53:52 -06:00
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#include <linux/gpio.h>
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2008-04-10 06:31:47 -06:00
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#include <linux/init.h>
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#include <linux/module.h>
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2013-09-25 06:33:55 -06:00
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#include <linux/io.h>
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2015-01-14 18:32:26 -07:00
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#include <linux/syscore_ops.h>
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2008-08-05 09:14:15 -06:00
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#include <mach/hardware.h>
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2012-02-23 16:06:51 -07:00
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#include <mach/irqs.h>
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2008-04-10 06:31:47 -06:00
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static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return GPLR & GPIO_GPIO(offset);
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}
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static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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if (value)
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GPSR = GPIO_GPIO(offset);
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else
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GPCR = GPIO_GPIO(offset);
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}
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static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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unsigned long flags;
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local_irq_save(flags);
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GPDR &= ~GPIO_GPIO(offset);
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local_irq_restore(flags);
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return 0;
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}
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static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
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{
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unsigned long flags;
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local_irq_save(flags);
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sa1100_gpio_set(chip, offset, value);
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GPDR |= GPIO_GPIO(offset);
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local_irq_restore(flags);
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return 0;
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}
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2011-12-18 11:24:57 -07:00
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static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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2015-01-14 18:29:16 -07:00
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return IRQ_GPIO0 + offset;
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2011-12-18 11:24:57 -07:00
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}
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2008-04-10 06:31:47 -06:00
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static struct gpio_chip sa1100_gpio_chip = {
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.label = "gpio",
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.direction_input = sa1100_direction_input,
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.direction_output = sa1100_direction_output,
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.set = sa1100_gpio_set,
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.get = sa1100_gpio_get,
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2011-12-18 11:24:57 -07:00
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.to_irq = sa1100_to_irq,
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2008-04-10 06:31:47 -06:00
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.base = 0,
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.ngpio = GPIO_MAX + 1,
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};
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2015-01-14 18:32:26 -07:00
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/*
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* SA1100 GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* Use this instead of directly setting GRER/GFER.
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*/
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static int GPIO_IRQ_rising_edge;
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static int GPIO_IRQ_falling_edge;
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static int GPIO_IRQ_mask;
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static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
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{
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unsigned int mask;
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mask = BIT(d->hwirq);
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if (type == IRQ_TYPE_PROBE) {
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if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
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return 0;
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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if (type & IRQ_TYPE_EDGE_RISING)
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GPIO_IRQ_rising_edge |= mask;
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else
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GPIO_IRQ_rising_edge &= ~mask;
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if (type & IRQ_TYPE_EDGE_FALLING)
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GPIO_IRQ_falling_edge |= mask;
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else
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GPIO_IRQ_falling_edge &= ~mask;
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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return 0;
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}
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/*
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* GPIO IRQs must be acknowledged.
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*/
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static void sa1100_gpio_ack(struct irq_data *d)
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{
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GEDR = BIT(d->hwirq);
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}
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static void sa1100_gpio_mask(struct irq_data *d)
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{
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unsigned int mask = BIT(d->hwirq);
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GPIO_IRQ_mask &= ~mask;
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GRER &= ~mask;
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GFER &= ~mask;
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}
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static void sa1100_gpio_unmask(struct irq_data *d)
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{
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unsigned int mask = BIT(d->hwirq);
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GPIO_IRQ_mask |= mask;
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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}
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static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
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{
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if (on)
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PWER |= BIT(d->hwirq);
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else
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PWER &= ~BIT(d->hwirq);
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return 0;
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}
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/*
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* This is for GPIO IRQs
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*/
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static struct irq_chip sa1100_gpio_irq_chip = {
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.name = "GPIO",
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.irq_ack = sa1100_gpio_ack,
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.irq_mask = sa1100_gpio_mask,
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.irq_unmask = sa1100_gpio_unmask,
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.irq_set_type = sa1100_gpio_type,
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.irq_set_wake = sa1100_gpio_wake,
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};
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static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip,
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handle_edge_irq);
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2015-07-27 14:55:16 -06:00
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irq_set_noprobe(irq);
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2015-01-14 18:32:26 -07:00
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return 0;
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}
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2015-04-27 06:54:07 -06:00
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static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
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2015-01-14 18:32:26 -07:00
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.map = sa1100_gpio_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static struct irq_domain *sa1100_gpio_irqdomain;
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/*
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* IRQ 0-11 (GPIO) handler. We enter here with the
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* irq_controller_lock held, and IRQs disabled. Decode the IRQ
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* and call the handler.
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*/
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2015-09-14 02:42:37 -06:00
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static void sa1100_gpio_handler(struct irq_desc *desc)
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2015-01-14 18:32:26 -07:00
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{
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2015-07-12 16:11:27 -06:00
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unsigned int irq, mask;
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2015-01-14 18:32:26 -07:00
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mask = GEDR;
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do {
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/*
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* clear down all currently active IRQ sources.
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* We will be processing them all.
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*/
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GEDR = mask;
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irq = IRQ_GPIO0;
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do {
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if (mask & 1)
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generic_handle_irq(irq);
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mask >>= 1;
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irq++;
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} while (mask);
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mask = GEDR;
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} while (mask);
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}
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static int sa1100_gpio_suspend(void)
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{
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/*
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* Set the appropriate edges for wakeup.
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*/
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GRER = PWER & GPIO_IRQ_rising_edge;
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GFER = PWER & GPIO_IRQ_falling_edge;
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/*
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* Clear any pending GPIO interrupts.
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*/
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GEDR = GEDR;
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return 0;
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}
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static void sa1100_gpio_resume(void)
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{
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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}
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static struct syscore_ops sa1100_gpio_syscore_ops = {
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.suspend = sa1100_gpio_suspend,
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.resume = sa1100_gpio_resume,
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};
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static int __init sa1100_gpio_init_devicefs(void)
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{
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register_syscore_ops(&sa1100_gpio_syscore_ops);
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return 0;
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}
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device_initcall(sa1100_gpio_init_devicefs);
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2008-04-10 06:31:47 -06:00
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void __init sa1100_init_gpio(void)
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{
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2015-01-14 18:32:26 -07:00
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/* clear all GPIO edge detects */
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GFER = 0;
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GRER = 0;
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GEDR = -1;
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2008-04-10 06:31:47 -06:00
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gpiochip_add(&sa1100_gpio_chip);
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2015-01-14 18:32:26 -07:00
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sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
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28, IRQ_GPIO0,
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&sa1100_gpio_irqdomain_ops, NULL);
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/*
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* Install handlers for GPIO 0-10 edge detect interrupts
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*/
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irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
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/*
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* Install handler for GPIO 11-27 edge detect interrupts
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*/
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irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
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2008-04-10 06:31:47 -06:00
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}
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