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alistair23-linux/arch/arm/boot/dts/vfxxx.dtsi

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ARM: dts: vf: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-25 10:08:01 -06:00
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
ARM: dts: vf610: use new GPIO support Use GPIO support by adding SD card detection configuration and GPIO pinmux for Colibri's standard GPIO pins. Attach the GPIO pins to the iomuxc node to get the GPIO pin settings applied. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-04 06:07:08 -07:00
#include <dt-bindings/gpio/gpio.h>
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
/ {
aliases {
can0 = &can0;
can1 = &can1;
ARM: dts: vf610: Add alias for ethernet controller Add alias for FEC ethernet on Vybrid to allow bootloaders (like U-Boot) patch-in the MAC address using this alias. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-01-29 17:04:48 -07:00
ethernet0 = &fec0;
ethernet1 = &fec1;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
ARM: vf610: use zero based naming for GPIO nodes On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-16 10:06:15 -07:00
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
usbphy0 = &usbphy0;
usbphy1 = &usbphy1;
};
fxosc: fxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
sxosc: sxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ARM: dts: vf610: add system reset controller and syscon-reboot Add the system reset controller (SRC) module and use syscon-reboot to register a restart handler which restarts the SoC using the SRC SW_RST bit. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-12-02 10:11:59 -07:00
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&src>;
offset = <0x0>;
mask = <0x1000>;
};
ARM: dts: vf610-zii-dev: enable vf610 builtin temp sensor Vybrid has single internal temperature sensor connected to both internal ADC modules. vf610-zii-dev already has ADC0 enabled. Now, to get temperature sensor captured by iio_hwmon driver, need to configure iio_hwmon node to use that ADC. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-05-16 00:39:21 -06:00
tempsensor: iio-hwmon {
ARM: dts: vfxxx: Move nodes which have no reg property out of bus Move iio-hwmon node from soc node to root node. iio-hwmon node does not have any register properties and thus shouldn't be placed on the bus. This fixes the following build warnings with W=1: arch/arm/boot/dts/vf500-colibri-eval-v3.dtb: Warning (simple_bus_reg): Node /soc/iio-hwmon missing or empty reg/ranges property Based on a patch from Simon Horman for the renesas r8a7795 dtsi. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-11-29 11:54:42 -07:00
compatible = "iio-hwmon";
io-channels = <&adc0 16>, <&adc1 16>;
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupt-parent = <&mscm_ir>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
ranges;
aips0: aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ARM: dts: vfxxx: add missing reg properties Add missing reg properties to AIPS bus and Cortex-A5's PMU unit. This change avoids the following warnings: Warning (unit_address_vs_reg): Node /soc/aips-bus@40000000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000/pmu@40089000 has a unit name, but no reg property Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-02 00:13:41 -06:00
reg = <0x40000000 0x00070000>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
ranges;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
mscm_cpucfg: cpucfg@40001000 {
compatible = "fsl,vf610-mscm-cpucfg", "syscon";
reg = <0x40001000 0x800>;
};
mscm_ir: interrupt-controller@40001800 {
compatible = "fsl,vf610-mscm-ir";
reg = <0x40001800 0x400>;
fsl,cpucfg = <&mscm_cpucfg>;
interrupt-controller;
#interrupt-cells = <2>;
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x40018000 0x2000>,
<0x40024000 0x1000>,
<0x40025000 0x1000>;
dma-channels = <32>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
<9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX0>,
<&clks VF610_CLK_DMAMUX1>;
status = "disabled";
};
can0: flexcan@40020000 {
compatible = "fsl,vf610-flexcan";
reg = <0x40020000 0x4000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_FLEXCAN0>,
<&clks VF610_CLK_FLEXCAN0>;
clock-names = "ipg", "per";
status = "disabled";
};
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
dmas = <&edma0 0 2>,
<&edma0 0 3>;
dma-names = "rx","tx";
status = "disabled";
};
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
dmas = <&edma0 0 4>,
<&edma0 0 5>;
dma-names = "rx","tx";
status = "disabled";
};
uart2: serial@40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
dmas = <&edma0 0 6>,
<&edma0 0 7>;
dma-names = "rx","tx";
status = "disabled";
};
uart3: serial@4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
dmas = <&edma0 0 8>,
<&edma0 0 9>;
dma-names = "rx","tx";
status = "disabled";
};
ARM: dts: imx: Fix SPI bus warnings dtc has new checks for SPI buses. Fix the warnings in node names and unit-addresses. There's over 100 warnings for FSL boards, a few examples: arch/arm/boot/dts/imx28-duckbill-2-spi.dtb: Warning (spi_bus_bridge): /apb@80000000/apbh@80000000/ssp@80014000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx53-ppd.dtb: Warning (spi_bus_bridge): /soc/aips@50000000/spba@50000000/ecspi@50010000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning (spi_bus_reg): /soc/aips-bus@2000000/spba-bus@2000000/spi@2014000/mcp251x@1: SPI bus unit address format error, expected "0" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-13 12:12:29 -06:00
dspi0: spi@4002c000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
ARM: dts: vfxxx: Fix dspi[01] spi-num-chipselects. Per the Vybrid Reference Manual (section 3.8.6.1), dspi0 has 6 chip select signals associated with it, while dspi1 has only 4. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-11-18 20:54:39 -07:00
spi-num-chipselects = <6>;
ARM: dts: vfxxx: Enable DMA for DSPI on Vybrid Enable DMA for DSPI on Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-03 06:50:37 -06:00
dmas = <&edma1 1 12>,
<&edma1 1 13>;
dma-names = "rx", "tx";
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
status = "disabled";
};
ARM: dts: imx: Fix SPI bus warnings dtc has new checks for SPI buses. Fix the warnings in node names and unit-addresses. There's over 100 warnings for FSL boards, a few examples: arch/arm/boot/dts/imx28-duckbill-2-spi.dtb: Warning (spi_bus_bridge): /apb@80000000/apbh@80000000/ssp@80014000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx53-ppd.dtb: Warning (spi_bus_bridge): /soc/aips@50000000/spba@50000000/ecspi@50010000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning (spi_bus_reg): /soc/aips-bus@2000000/spba-bus@2000000/spi@2014000/mcp251x@1: SPI bus unit address format error, expected "0" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-13 12:12:29 -06:00
dspi1: spi@4002d000 {
ARM: vf610: add second DSPI instance Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-27 03:57:18 -07:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002d000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
ARM: vf610: add second DSPI instance Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-27 03:57:18 -07:00
clocks = <&clks VF610_CLK_DSPI1>;
clock-names = "dspi";
ARM: dts: vfxxx: Fix dspi[01] spi-num-chipselects. Per the Vybrid Reference Manual (section 3.8.6.1), dspi0 has 6 chip select signals associated with it, while dspi1 has only 4. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-11-18 20:54:39 -07:00
spi-num-chipselects = <4>;
ARM: dts: vfxxx: Enable DMA for DSPI on Vybrid Enable DMA for DSPI on Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-03 06:50:37 -06:00
dmas = <&edma1 1 14>,
<&edma1 1 15>;
dma-names = "rx", "tx";
ARM: vf610: add second DSPI instance Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-27 03:57:18 -07:00
status = "disabled";
};
ARM: dts: vf610: add remaining SAI instaces This adds the remaining SAI instances SAI0, SAI1 and SAI3. All instances are very similar, except that the DMA channel of SAI3 is available on MUX1 (compared to MUX0 for SAI0-SAI2). Also, SAI3 has a slightly different memory map due to a deeper FIFO, however in practice the current driver works for SAI3 fine. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-17 22:05:22 -06:00
sai0: sai@4002f000 {
compatible = "fsl,vf610-sai";
reg = <0x4002f000 0x1000>;
interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI0>,
<&clks VF610_CLK_SAI0_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 0 17>,
<&edma0 0 16>;
status = "disabled";
};
sai1: sai@40030000 {
compatible = "fsl,vf610-sai";
reg = <0x40030000 0x1000>;
interrupts = <85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI1>,
<&clks VF610_CLK_SAI1_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 0 19>,
<&edma0 0 18>;
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: fix clock definition for SAI2 So far, only the bus clock has been assigned, but in reality the SAI IP has for clock inputs. The driver has been updated to make use of the additional clock inputs by c3ecef21c3f2 ("ASoC: fsl_sai: add sai master mode support"). Due to a bug in the clock tree, the audio clock has been enabled none the less by the specified bus clock (see "ARM: imx: clk-vf610: fix SAI clock tree"), which made master mode even without the proper clock assigned working. This patch completes the clock definition for SAI2. On Vybrid, only two MCLK out of the four options are available (the first being the bus clock itself). See chapter 8.10.1.2.3 of the Vybrid Reference manual ("SAI transmitter and receiver options for MCLK selection"). Note: The audio clocks are only required in master mode. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-17 22:05:21 -06:00
clocks = <&clks VF610_CLK_SAI2>,
<&clks VF610_CLK_SAI2_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
dma-names = "tx", "rx";
dmas = <&edma0 0 21>,
<&edma0 0 20>;
status = "disabled";
};
ARM: dts: vf610: add remaining SAI instaces This adds the remaining SAI instances SAI0, SAI1 and SAI3. All instances are very similar, except that the DMA channel of SAI3 is available on MUX1 (compared to MUX0 for SAI0-SAI2). Also, SAI3 has a slightly different memory map due to a deeper FIFO, however in practice the current driver works for SAI3 fine. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-17 22:05:22 -06:00
sai3: sai@40032000 {
compatible = "fsl,vf610-sai";
reg = <0x40032000 0x1000>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_SAI3>,
<&clks VF610_CLK_SAI3_DIV>,
<&clks 0>, <&clks 0>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 9>,
<&edma0 1 8>;
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
pwm0: pwm@40038000 {
compatible = "fsl,vf610-ftm-pwm";
#pwm-cells = <3>;
reg = <0x40038000 0x1000>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
clocks = <&clks VF610_CLK_FTM0>,
<&clks VF610_CLK_FTM0_EXT_SEL>,
<&clks VF610_CLK_FTM0_FIX_SEL>,
<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
status = "disabled";
};
pwm1: pwm@40039000 {
compatible = "fsl,vf610-ftm-pwm";
#pwm-cells = <3>;
reg = <0x40039000 0x1000>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
clocks = <&clks VF610_CLK_FTM1>,
<&clks VF610_CLK_FTM1_EXT_SEL>,
<&clks VF610_CLK_FTM1_FIX_SEL>,
<&clks VF610_CLK_FTM1_EXT_FIX_EN>;
status = "disabled";
};
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
ARM: dts: vfxxx: Add io-channel-cells property for ADC node This commit adds io-channel-cells property to the ADC node. This property is required in order for an IIO consumer driver to work. Especially required for Colibri VF50, as the touchscreen driver uses ADC channels with the ADC driver based on IIO framework. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-07-16 09:13:19 -06:00
#io-channel-cells = <1>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
status = "disabled";
ARM: dts: add property for maximum ADC clock frequencies The ADC clock frequency is limited depending on modes used. Add device tree property which allow to set the mode used and the maximum frequency ratings for the instance. These allows to set the ADC clock to a frequency which is within specification according to the actual mode used. Acked-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-05-27 06:47:52 -06:00
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
};
ARM: dts: vf610: add display nodes Add the dcu and tcon nodes to enable the Display Controller Unit and Timing Controller in Vybrid's SoC level device-tree file. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-04 23:28:39 -06:00
tcon0: timing-controller@4003d000 {
compatible = "fsl,vf610-tcon";
reg = <0x4003d000 0x1000>;
clocks = <&clks VF610_CLK_TCON0>;
clock-names = "ipg";
status = "disabled";
};
ARM: dts: vf610: enable watchdog for Cortex-A5 dt's During restructuring of the device tree files the watchdog was changed to be disabled by default. However, since the watchdog instance is dedicated to the Cortex-A5, enable the peripheral by default in the base device tree vf500.dtsi. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-27 16:35:36 -07:00
wdoga5: wdog@4003e000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
status = "disabled";
};
ARM: dts: imx: Fix SPI bus warnings dtc has new checks for SPI buses. Fix the warnings in node names and unit-addresses. There's over 100 warnings for FSL boards, a few examples: arch/arm/boot/dts/imx28-duckbill-2-spi.dtb: Warning (spi_bus_bridge): /apb@80000000/apbh@80000000/ssp@80014000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx53-ppd.dtb: Warning (spi_bus_bridge): /soc/aips@50000000/spba@50000000/ecspi@50010000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning (spi_bus_reg): /soc/aips-bus@2000000/spba-bus@2000000/spi@2014000/mcp251x@1: SPI bus unit address format error, expected "0" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-13 12:12:29 -06:00
qspi0: spi@40044000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
ARM: dts: vf610: Add missing QuadSPI register mapping and names. Both 'reg' and 'reg-names' are required properties according to binding documentation, and both should contain two items. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-07-08 14:21:15 -06:00
reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
iomuxc: iomuxc@40048000 {
compatible = "fsl,vf610-iomuxc";
reg = <0x40048000 0x1000>;
};
ARM: vf610: use zero based naming for GPIO nodes On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-16 10:06:15 -07:00
gpio0: gpio@40049000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
compatible = "fsl,vf610-gpio";
reg = <0x40049000 0x1000 0x400ff000 0x40>;
gpio-controller;
#gpio-cells = <2>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
};
ARM: vf610: use zero based naming for GPIO nodes On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-16 10:06:15 -07:00
gpio1: gpio@4004a000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
compatible = "fsl,vf610-gpio";
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
gpio-controller;
#gpio-cells = <2>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
};
ARM: vf610: use zero based naming for GPIO nodes On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-16 10:06:15 -07:00
gpio2: gpio@4004b000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
compatible = "fsl,vf610-gpio";
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
gpio-controller;
#gpio-cells = <2>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
};
ARM: vf610: use zero based naming for GPIO nodes On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-16 10:06:15 -07:00
gpio3: gpio@4004c000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
compatible = "fsl,vf610-gpio";
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
};
ARM: vf610: use zero based naming for GPIO nodes On Vybrid, all peripherals are numbered starting with zero, including the GPIO and PORT module. However, the labels of the corresponding device tree nodes start with one, which is confusing. Fix that by renaming the labels of the gpio nodes in the device tree. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-16 10:06:15 -07:00
gpio4: gpio@4004d000 {
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
compatible = "fsl,vf610-gpio";
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
gpio-controller;
#gpio-cells = <2>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
};
anatop: anatop@40050000 {
compatible = "fsl,vf610-anatop", "syscon";
reg = <0x40050000 0x400>;
};
usbphy0: usbphy@40050800 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050800 0x400>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_USBPHY0>;
fsl,anatop = <&anatop>;
status = "disabled";
};
usbphy1: usbphy@40050c00 {
compatible = "fsl,vf610-usbphy";
reg = <0x40050c00 0x400>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_USBPHY1>;
fsl,anatop = <&anatop>;
status = "disabled";
};
ARM: dts: vf610: add display nodes Add the dcu and tcon nodes to enable the Display Controller Unit and Timing Controller in Vybrid's SoC level device-tree file. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-04 23:28:39 -06:00
dcu0: dcu@40058000 {
compatible = "fsl,vf610-dcu";
reg = <0x40058000 0x1200>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DCU0>,
<&clks VF610_CLK_DCU0_DIV>;
clock-names = "dcu", "pix";
fsl,tcon = <&tcon0>;
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
i2c0: i2c@40066000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
dmas = <&edma0 0 50>,
<&edma0 0 51>;
dma-names = "rx","tx";
status = "disabled";
};
ARM: dts: vf610: Extend I2C support to all available buses. This commit extends the existing Vybrid I2C support to cover buses i2c1, i2c2, and i2c3. Based in (very) large part on an initial patch by Stefan Agner that was just lacking a couple of DMA assignments. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-06-14 18:19:59 -06:00
i2c1: i2c@40067000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40067000 0x1000>;
interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C1>;
clock-names = "ipg";
dmas = <&edma0 0 52>,
<&edma0 0 53>;
dma-names = "rx","tx";
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clks: ccm@4006b000 {
compatible = "fsl,vf610-ccm";
reg = <0x4006b000 0x1000>;
clocks = <&sxosc>, <&fxosc>;
clock-names = "sxosc", "fxosc";
#clock-cells = <1>;
};
usbdev0: usb@40034000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x40034000 0x800>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
fsl,usbmisc = <&usbmisc0 0>;
dr_mode = "peripheral";
status = "disabled";
};
usbmisc0: usb@40034800 {
#index-cells = <1>;
compatible = "fsl,vf610-usbmisc";
reg = <0x40034800 0x200>;
clocks = <&clks VF610_CLK_USBC0>;
status = "disabled";
};
ARM: dts: vf610: add system reset controller and syscon-reboot Add the system reset controller (SRC) module and use syscon-reboot to register a restart handler which restarts the SoC using the SRC SW_RST bit. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-12-02 10:11:59 -07:00
src: src@4006e000 {
compatible = "fsl,vf610-src", "syscon";
reg = <0x4006e000 0x1000>;
ARM: dts: vf610: fix missing irqs While adding the MSCM interrupt router, all interrupts have been moved to vfxxx.dtsi again. However, some properties got lost. Readd the missing interrupt properties. Fixes: 97e6466ab9d0 ("ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-29 22:10:39 -06:00
interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: add system reset controller and syscon-reboot Add the system reset controller (SRC) module and use syscon-reboot to register a restart handler which restarts the SoC using the SRC SW_RST bit. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-12-02 10:11:59 -07:00
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
};
aips1: aips-bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ARM: dts: vfxxx: add missing reg properties Add missing reg properties to AIPS bus and Cortex-A5's PMU unit. This change avoids the following warnings: Warning (unit_address_vs_reg): Node /soc/aips-bus@40000000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000/pmu@40089000 has a unit name, but no reg property Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-02 00:13:41 -06:00
reg = <0x40080000 0x0007f000>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
ranges;
edma1: dma-controller@40098000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
reg = <0x40098000 0x2000>,
<0x400a1000 0x1000>,
<0x400a2000 0x1000>;
dma-channels = <32>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clock-names = "dmamux0", "dmamux1";
clocks = <&clks VF610_CLK_DMAMUX2>,
<&clks VF610_CLK_DMAMUX3>;
status = "disabled";
};
ARM: dts: vfxxx: Add node corresponding to OCOTP Add node corresponding to OCOTP IP block. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-01 19:30:22 -06:00
ocotp: ocotp@400a5000 {
ARM: dts: vfxxx: Add syscon compatible with OCOTP commit 2a6838d54128952ace6f0ca166dd8706abe46649 upstream. Add syscon compatibility with Vybrid OCOTP node. This is required to access the UID. Fixes: fa8d20c8dbb77 ("ARM: dts: vfxxx: Add node corresponding to OCOTP") Cc: stable@vger.kernel.org Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-21 15:21:02 -06:00
compatible = "fsl,vf610-ocotp", "syscon";
ARM: dts: vfxxx: Add node corresponding to OCOTP Add node corresponding to OCOTP IP block. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-01 19:30:22 -06:00
reg = <0x400a5000 0x1000>;
clocks = <&clks VF610_CLK_OCOTP>;
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
ARM: dts: vfxxx: Add SNVS node Add device tree node for the Secure Non-Volatile Storage (SNVS) on the VF610 platform. The SNVS block also has a Real Time Counter (RTC). Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-07 00:09:30 -07:00
snvs0: snvs@400a7000 {
ARM: dts: imx: update snvs to use syscon access register snvs is MFP device. Change dts to use syscon to allocate register resource. snvs power off also switch to common syscon-poweroff Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-05-26 10:25:59 -06:00
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x400a7000 0x2000>;
ARM: dts: vfxxx: Add SNVS node Add device tree node for the Secure Non-Volatile Storage (SNVS) on the VF610 platform. The SNVS block also has a Real Time Counter (RTC). Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-07 00:09:30 -07:00
ARM: dts: imx: update snvs to use syscon access register snvs is MFP device. Change dts to use syscon to allocate register resource. snvs power off also switch to common syscon-poweroff Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-05-26 10:25:59 -06:00
snvsrtc: snvs-rtc-lp {
ARM: dts: vfxxx: Add SNVS node Add device tree node for the Secure Non-Volatile Storage (SNVS) on the VF610 platform. The SNVS block also has a Real Time Counter (RTC). Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-07 00:09:30 -07:00
compatible = "fsl,sec-v4.0-mon-rtc-lp";
ARM: dts: imx: update snvs to use syscon access register snvs is MFP device. Change dts to use syscon to allocate register resource. snvs power off also switch to common syscon-poweroff Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-05-26 10:25:59 -06:00
regmap = <&snvs0>;
offset = <0x34>;
ARM: dts: vf610: fix missing irqs While adding the MSCM interrupt router, all interrupts have been moved to vfxxx.dtsi again. However, some properties got lost. Readd the missing interrupt properties. Fixes: 97e6466ab9d0 ("ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-29 22:10:39 -06:00
interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vfxxx: Add SNVS node Add device tree node for the Secure Non-Volatile Storage (SNVS) on the VF610 platform. The SNVS block also has a Real Time Counter (RTC). Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-07 00:09:30 -07:00
clocks = <&clks VF610_CLK_SNVS>;
clock-names = "snvs-rtc";
};
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
};
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
};
ARM: dts: imx: Fix SPI bus warnings dtc has new checks for SPI buses. Fix the warnings in node names and unit-addresses. There's over 100 warnings for FSL boards, a few examples: arch/arm/boot/dts/imx28-duckbill-2-spi.dtb: Warning (spi_bus_bridge): /apb@80000000/apbh@80000000/ssp@80014000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx53-ppd.dtb: Warning (spi_bus_bridge): /soc/aips@50000000/spba@50000000/ecspi@50010000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning (spi_bus_reg): /soc/aips-bus@2000000/spba-bus@2000000/spi@2014000/mcp251x@1: SPI bus unit address format error, expected "0" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-13 12:12:29 -06:00
dspi2: spi@400ac000 {
ARM: dts: vfxxx: Include support for dspi[23] functionality. Extend the existing Vybrid DSPI devicetree implementation to also describe the dspi2 and dspi3 functional blocks. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-11-18 20:54:40 -07:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x400ac000 0x1000>;
interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI2>;
clock-names = "dspi";
spi-num-chipselects = <2>;
ARM: dts: vfxxx: Enable DMA for DSPI2 and DSPI3 Enable DMA for DSPI2 and DSPI3 on Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-14 05:37:01 -07:00
dmas = <&edma1 0 10>,
<&edma1 0 11>;
dma-names = "rx", "tx";
ARM: dts: vfxxx: Include support for dspi[23] functionality. Extend the existing Vybrid DSPI devicetree implementation to also describe the dspi2 and dspi3 functional blocks. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-11-18 20:54:40 -07:00
status = "disabled";
};
ARM: dts: imx: Fix SPI bus warnings dtc has new checks for SPI buses. Fix the warnings in node names and unit-addresses. There's over 100 warnings for FSL boards, a few examples: arch/arm/boot/dts/imx28-duckbill-2-spi.dtb: Warning (spi_bus_bridge): /apb@80000000/apbh@80000000/ssp@80014000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx53-ppd.dtb: Warning (spi_bus_bridge): /soc/aips@50000000/spba@50000000/ecspi@50010000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning (spi_bus_reg): /soc/aips-bus@2000000/spba-bus@2000000/spi@2014000/mcp251x@1: SPI bus unit address format error, expected "0" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-13 12:12:29 -06:00
dspi3: spi@400ad000 {
ARM: dts: vfxxx: Include support for dspi[23] functionality. Extend the existing Vybrid DSPI devicetree implementation to also describe the dspi2 and dspi3 functional blocks. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-11-18 20:54:40 -07:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x400ad000 0x1000>;
interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_DSPI3>;
clock-names = "dspi";
spi-num-chipselects = <2>;
ARM: dts: vfxxx: Enable DMA for DSPI2 and DSPI3 Enable DMA for DSPI2 and DSPI3 on Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-14 05:37:01 -07:00
dmas = <&edma1 0 12>,
<&edma1 0 13>;
dma-names = "rx", "tx";
ARM: dts: vfxxx: Include support for dspi[23] functionality. Extend the existing Vybrid DSPI devicetree implementation to also describe the dspi2 and dspi3 functional blocks. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-11-18 20:54:40 -07:00
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
adc1: adc@400bb000 {
compatible = "fsl,vf610-adc";
reg = <0x400bb000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_ADC1>;
clock-names = "adc";
ARM: dts: vfxxx: Add io-channel-cells property for ADC node This commit adds io-channel-cells property to the ADC node. This property is required in order for an IIO consumer driver to work. Especially required for Colibri VF50, as the touchscreen driver uses ADC channels with the ADC driver based on IIO framework. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-07-16 09:13:19 -06:00
#io-channel-cells = <1>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
status = "disabled";
ARM: dts: vfxxx: Fix erroneous property in esdhc0 node Something seems to have gone wrong during the merging of the device tree changes with the following patch "ARM: dts: add property for maximum ADC clock frequencies" The property "fsl,adck-max-frequency" instead of being applied for the ADC1 node got applied to the esdhc0 node. This patch fixes it. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Fixes: def0641e2f61 ("ARM: dts: add property for maximum ADC clock frequencies") Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-17 23:48:48 -06:00
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
};
ARM: dts: vfxxx: Include support for esdhc0 functionality. Extend the existing Vybrid eSDHC devicetree implementation to also describe the esdhc0 functional block. Tested on a custom VF610-based board with a Toshiba THGBM1G5D2EBAI7 eMMC module attached to esdhc0. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-07-08 14:51:06 -06:00
esdhc0: esdhc@400b1000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b1000 0x1000>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC0>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
esdhc1: esdhc@400b2000 {
compatible = "fsl,imx53-esdhc";
reg = <0x400b2000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_IPG_BUS>,
<&clks VF610_CLK_PLATFORM_BUS>,
<&clks VF610_CLK_ESDHC1>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
usbh1: usb@400b4000 {
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
reg = <0x400b4000 0x800>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_USBC1>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
dr_mode = "host";
status = "disabled";
};
usbmisc1: usb@400b4800 {
#index-cells = <1>;
compatible = "fsl,vf610-usbmisc";
reg = <0x400b4800 0x200>;
clocks = <&clks VF610_CLK_USBC1>;
status = "disabled";
};
ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clock-names = "ftm-evt", "ftm-src",
"ftm-evt-counter-en", "ftm-src-counter-en";
clocks = <&clks VF610_CLK_FTM2>,
<&clks VF610_CLK_FTM3>,
<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
status = "disabled";
};
ARM: dts: imx: Fix SPI bus warnings dtc has new checks for SPI buses. Fix the warnings in node names and unit-addresses. There's over 100 warnings for FSL boards, a few examples: arch/arm/boot/dts/imx28-duckbill-2-spi.dtb: Warning (spi_bus_bridge): /apb@80000000/apbh@80000000/ssp@80014000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx53-ppd.dtb: Warning (spi_bus_bridge): /soc/aips@50000000/spba@50000000/ecspi@50010000: node name for SPI buses should be 'spi' arch/arm/boot/dts/imx6dl-colibri-eval-v3.dtb: Warning (spi_bus_reg): /soc/aips-bus@2000000/spba-bus@2000000/spi@2014000/mcp251x@1: SPI bus unit address format error, expected "0" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Stefan Agner <stefan@agner.ch> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-13 12:12:29 -06:00
qspi1: spi@400c4000 {
ARM: dts: vfxxx: Include support for qspi1 functionality. This commit extends the existing Vybrid QSPI devicetree implementation to also describe the qspi1 functional block. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-07-08 14:21:16 -06:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_QSPI1_EN>,
<&clks VF610_CLK_QSPI1>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
ARM: dts: vfxxx: Add DAC node for Vybrid SoC Add a device tree node entry for DAC peripheral on Vybrid SoC. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-21 23:18:36 -07:00
dac0: dac@400cc000 {
compatible = "fsl,vf610-dac";
reg = <0x400cc000 1000>;
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dac";
clocks = <&clks VF610_CLK_DAC0>;
status = "disabled";
};
dac1: dac@400cd000 {
compatible = "fsl,vf610-dac";
reg = <0x400cd000 1000>;
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dac";
clocks = <&clks VF610_CLK_DAC1>;
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET0>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET1>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
can1: flexcan@400d4000 {
compatible = "fsl,vf610-flexcan";
reg = <0x400d4000 0x4000>;
ARM: dts: vf610: add Miscellaneous System Control Module (MSCM) Add the Miscellaneous System Control Module (MSCM) to the base device tree for Vybrid SoC's. This module contains registers to get information of the individual and current (accessing) CPU. In a second block, there is an interrupt router, which handles the routing of the interrupts between the two CPU cores on VF6xx variants of the SoC. However, also on single core variants the interrupt router needs to be configured in order to receive interrupts on the CPU's interrupt controller. Almost all peripheral interrupts are routed through the router, hence the MSCM module is the default interrupt parent for this SoC. In a earlier commit the interrupt nodes were moved out of the peripheral nodes and specified in the CPU specific vf500.dtsi device tree. This allowed to use the base device tree vfxxx.dtsi also for a Cortex-M4 specific device tree, which uses different interrupt nodes due to the NVIC interrupt controller. However, since the interrupt parent for peripherals is the MSCM module independently which CPU the device tree is used for, we can move the interrupt nodes into the base device tree vfxxx.dtsi again. Depending on which CPU this base device tree will be used with, the correct parent interrupt controller has to be assigned to the MSCM-IR node (GIC or NVIC). The driver takes care of the parent interrupt controller specific needs (interrupt-cells). Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-03-01 15:41:29 -07:00
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
clocks = <&clks VF610_CLK_FLEXCAN1>,
<&clks VF610_CLK_FLEXCAN1>;
clock-names = "ipg", "per";
status = "disabled";
};
ARM: dts: vf610twr: add NAND flash controller peripherial This adds the NAND flash controller (NFC) peripherial. The driver supports the SLC NAND chips found on Freescale's Vybrid Tower System Module. The Micron NAND chip on the module needs 4-bit ECC per 512 byte page. Use 24-bit ECC per 2k page, which is supported by the driver. Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Reviewed-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-07 17:58:35 -06:00
nfc: nand@400e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-nfc";
reg = <0x400e0000 0x4000>;
interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_NFC>;
clock-names = "nfc";
status = "disabled";
};
ARM: dts: vf610: Extend I2C support to all available buses. This commit extends the existing Vybrid I2C support to cover buses i2c1, i2c2, and i2c3. Based in (very) large part on an initial patch by Stefan Agner that was just lacking a couple of DMA assignments. Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-06-14 18:19:59 -06:00
i2c2: i2c@400e6000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x400e6000 0x1000>;
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C2>;
clock-names = "ipg";
dmas = <&edma0 1 36>,
<&edma0 1 37>;
dma-names = "rx","tx";
status = "disabled";
};
i2c3: i2c@400e7000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x400e7000 0x1000>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_I2C3>;
clock-names = "ipg";
dmas = <&edma0 1 38>,
<&edma0 1 39>;
dma-names = "rx","tx";
status = "disabled";
};
ARM: dts: vf610: create generic base device trees This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-02 13:36:46 -07:00
};
};
};