2014-11-22 06:41:23 -07:00
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/*
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* SAMSUNG EXYNOS7 SoC device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos7-clk.h>
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/ {
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compatible = "samsung,exynos7";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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2014-11-22 06:41:33 -07:00
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_bus0;
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pinctrl2 = &pinctrl_nfc;
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pinctrl3 = &pinctrl_touch;
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pinctrl4 = &pinctrl_ff;
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pinctrl5 = &pinctrl_ese;
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pinctrl6 = &pinctrl_fsys0;
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pinctrl7 = &pinctrl_fsys1;
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};
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2014-11-22 06:41:23 -07:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x18000000>;
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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fin_pll: xxti {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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};
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gic: interrupt-controller@11001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x11001000 0x1000>,
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<0x11002000 0x1000>,
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<0x11004000 0x2000>,
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<0x11006000 0x2000>;
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};
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clock_topc: clock-controller@10570000 {
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compatible = "samsung,exynos7-clock-topc";
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reg = <0x10570000 0x10000>;
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#clock-cells = <1>;
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};
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clock_top0: clock-controller@105d0000 {
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compatible = "samsung,exynos7-clock-top0";
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reg = <0x105d0000 0xb000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll", "dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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clock_peric0: clock-controller@13610000 {
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compatible = "samsung,exynos7-clock-peric0";
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reg = <0x13610000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
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<&clock_top0 CLK_SCLK_UART0>;
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clock-names = "fin_pll", "dout_aclk_peric0_66",
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"sclk_uart0";
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};
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clock_peric1: clock-controller@14c80000 {
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compatible = "samsung,exynos7-clock-peric1";
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reg = <0x14c80000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
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<&clock_top0 CLK_SCLK_UART1>,
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<&clock_top0 CLK_SCLK_UART2>,
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<&clock_top0 CLK_SCLK_UART3>;
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clock-names = "fin_pll", "dout_aclk_peric1_66",
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"sclk_uart1", "sclk_uart2", "sclk_uart3";
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};
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clock_peris: clock-controller@10040000 {
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compatible = "samsung,exynos7-clock-peris";
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reg = <0x10040000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
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clock-names = "fin_pll", "dout_aclk_peris_66";
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};
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serial_0: serial@13630000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13630000 0x100>;
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interrupts = <0 440 0>;
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clocks = <&clock_peric0 PCLK_UART0>,
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<&clock_peric0 SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_1: serial@14c20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c20000 0x100>;
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interrupts = <0 456 0>;
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clocks = <&clock_peric1 PCLK_UART1>,
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<&clock_peric1 SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_2: serial@14c30000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c30000 0x100>;
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interrupts = <0 457 0>;
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clocks = <&clock_peric1 PCLK_UART2>,
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<&clock_peric1 SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_3: serial@14c40000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c40000 0x100>;
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interrupts = <0 458 0>;
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clocks = <&clock_peric1 PCLK_UART3>,
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<&clock_peric1 SCLK_UART3>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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2014-11-22 06:41:33 -07:00
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pinctrl_alive: pinctrl@10580000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x10580000 0x1000>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos7-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 16 0>;
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};
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};
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pinctrl_bus0: pinctrl@13470000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x13470000 0x1000>;
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interrupts = <0 383 0>;
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};
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pinctrl_nfc: pinctrl@14cd0000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14cd0000 0x1000>;
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interrupts = <0 473 0>;
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};
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pinctrl_touch: pinctrl@14ce0000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14ce0000 0x1000>;
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interrupts = <0 474 0>;
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};
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pinctrl_ff: pinctrl@14c90000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14c90000 0x1000>;
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interrupts = <0 475 0>;
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};
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pinctrl_ese: pinctrl@14ca0000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14ca0000 0x1000>;
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interrupts = <0 476 0>;
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};
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pinctrl_fsys0: pinctrl@10e60000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x10e60000 0x1000>;
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interrupts = <0 221 0>;
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};
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pinctrl_fsys1: pinctrl@15690000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x15690000 0x1000>;
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interrupts = <0 203 0>;
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};
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2014-11-22 06:41:23 -07:00
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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<1 14 0xff01>,
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<1 11 0xff01>,
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<1 10 0xff01>;
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};
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};
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};
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2014-11-22 06:41:33 -07:00
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#include "exynos7-pinctrl.dtsi"
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