2014-01-21 00:47:06 -07:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/fs.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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#include "io.h"
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#ifdef CONFIG_B4860G100
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static struct gpiobus gbus;
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#endif /* CONFIG_B4860G100 */
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static inline void byte0_out(unsigned char data);
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static inline void byte1_out(unsigned char data);
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static inline void xl_cclk_b(int32_t i);
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/* Assert and Deassert CCLK */
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void xl_shift_cclk(int count)
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{
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int i;
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for (i = 0; i < count; i++) {
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xl_cclk_b(1);
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xl_cclk_b(0);
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}
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}
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int xl_supported_prog_bus_width(enum wbus bus_bytes)
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{
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switch (bus_bytes) {
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case bus_1byte:
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break;
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case bus_2byte:
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break;
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default:
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pr_err("unsupported program bus width %d\n",
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bus_bytes);
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return 0;
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}
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return 1;
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}
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/* Serialize byte and clock each bit on target's DIN and CCLK pins */
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void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata)
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{
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/*
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* supports 1 and 2 bytes programming mode
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*/
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if (likely(bus_byte == bus_2byte))
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byte0_out(pdata[0]);
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byte1_out(pdata[1]);
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xl_shift_cclk(1);
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}
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/*
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* generic bit swap for xilinx SYSTEMMAP FPGA programming
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*/
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static inline unsigned char bitswap(unsigned char s)
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{
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unsigned char d;
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d = (((s&0x80)>>7) | ((s&0x40)>>5) | ((s&0x20)>>3) | ((s&0x10)>>1) |
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((s&0x08)<<1) | ((s&0x04)<<3) | ((s&0x02)<<5) | ((s&0x01)<<7));
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return d;
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}
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#ifdef CONFIG_B4860G100
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/*
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* ======================================================================
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* board specific configuration
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*/
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static inline void mpc85xx_gpio_set_dir(
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int32_t port,
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uint32_t mask,
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uint32_t dir)
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{
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dir |= (in_be32(gbus.r[port]+GPDIR) & ~mask);
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out_be32(gbus.r[port]+GPDIR, dir);
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}
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static inline void mpc85xx_gpio_set(int32_t port, uint32_t mask, uint32_t val)
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{
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/* First mask off the unwanted parts of "dir" and "val" */
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val &= mask;
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/* Now read in the values we're supposed to preserve */
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val |= (in_be32(gbus.r[port]+GPDAT) & ~mask);
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out_be32(gbus.r[port]+GPDAT, val);
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}
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static inline uint32_t mpc85xx_gpio_get(int32_t port, uint32_t mask)
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{
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/* Read the requested values */
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return in_be32(gbus.r[port]+GPDAT) & mask;
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}
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static inline void mpc85xx_gpio_set_low(int32_t port, uint32_t gpios)
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{
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mpc85xx_gpio_set(port, gpios, 0x00000000);
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}
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static inline void mpc85xx_gpio_set_high(int32_t port, uint32_t gpios)
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{
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mpc85xx_gpio_set(port, gpios, 0xFFFFFFFF);
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}
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static inline void gpio_set_value(int32_t port, uint32_t gpio, uint32_t value)
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{
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int32_t g;
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g = 31 - gpio;
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if (value)
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mpc85xx_gpio_set_high(port, 1U << g);
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else
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mpc85xx_gpio_set_low(port, 1U << g);
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}
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static inline int gpio_get_value(int32_t port, uint32_t gpio)
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{
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int32_t g;
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g = 31 - gpio;
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return !!mpc85xx_gpio_get(port, 1U << g);
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}
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static inline void xl_cclk_b(int32_t i)
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{
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gpio_set_value(XL_CCLK_PORT, XL_CCLK_PIN, i);
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}
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void xl_program_b(int32_t i)
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{
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gpio_set_value(XL_PROGN_PORT, XL_PROGN_PIN, i);
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}
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void xl_rdwr_b(int32_t i)
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{
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gpio_set_value(XL_RDWRN_PORT, XL_RDWRN_PIN, i);
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}
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void xl_csi_b(int32_t i)
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{
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gpio_set_value(XL_CSIN_PORT, XL_CSIN_PIN, i);
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}
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int xl_get_init_b(void)
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{
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return gpio_get_value(XL_INITN_PORT, XL_INITN_PIN);
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}
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int xl_get_done_b(void)
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{
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return gpio_get_value(XL_DONE_PORT, XL_DONE_PIN);
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}
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/* G100 specific bit swap and remmap (to gpio pins) for byte 0 */
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static inline uint32_t bit_remap_byte0(uint32_t s)
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{
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uint32_t d;
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d = (((s&0x80)>>7) | ((s&0x40)>>5) | ((s&0x20)>>3) | ((s&0x10)>>1) |
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((s&0x08)<<1) | ((s&0x04)<<3) | ((s&0x02)<<6) | ((s&0x01)<<9));
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return d;
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}
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/*
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* G100 specific MSB, in this order [byte0 | byte1], out
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*/
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static inline void byte0_out(unsigned char data)
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{
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uint32_t swap32;
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swap32 = bit_remap_byte0((uint32_t) data) << 8;
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mpc85xx_gpio_set(0, 0x0002BF00, (uint32_t) swap32);
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}
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/*
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* G100 specific LSB, in this order [byte0 | byte1], out
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*/
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static inline void byte1_out(unsigned char data)
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{
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mpc85xx_gpio_set(0, 0x000000FF, (uint32_t) bitswap(data));
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}
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/*
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* configurable per device type for different I/O config
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*/
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int xl_init_io(void)
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{
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struct device_node *np;
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const u32 *p_reg;
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int reg, cnt;
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cnt = 0;
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memset(&gbus, 0, sizeof(struct gpiobus));
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for_each_compatible_node(np, NULL, "fsl,qoriq-gpio") {
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p_reg = of_get_property(np, "reg", NULL);
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if (p_reg == NULL)
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break;
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reg = (int) *p_reg;
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gbus.r[cnt] = of_iomap(np, 0);
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if (!gbus.r[cnt]) {
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pr_err("not findding gpio cell-index %d\n", cnt);
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return -ENODEV;
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}
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cnt++;
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}
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mpc85xx_gpio_set_dir(0, 0x0002BFFF, 0x0002BFFF);
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mpc85xx_gpio_set_dir(1, 0x00240060, 0x00240060);
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gbus.ngpio = cnt;
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return 0;
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}
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#else /* placeholder for boards with different config */
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void xl_program_b(int32_t i)
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{
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return;
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}
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void xl_rdwr_b(int32_t i)
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{
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return;
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}
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void xl_csi_b(int32_t i)
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{
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return;
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}
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int xl_get_init_b(void)
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{
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return -1;
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}
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int xl_get_done_b(void)
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{
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return -1;
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}
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static inline void byte0_out(unsigned char data)
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{
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return;
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}
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static inline void byte1_out(unsigned char data)
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{
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return;
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}
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static inline void xl_cclk_b(int32_t i)
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{
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return;
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}
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/*
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* configurable per device type for different I/O config
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*/
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2014-03-01 15:47:01 -07:00
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int xl_init_io(void)
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2014-01-21 00:47:06 -07:00
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{
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return -1;
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}
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#endif /* CONFIG_B4860G100 */
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