2009-09-03 11:14:05 -06:00
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/*
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2010-02-22 22:09:32 -07:00
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* omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
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2009-09-03 11:14:05 -06:00
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*
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2011-07-09 19:14:05 -06:00
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* Copyright (C) 2009-2011 Nokia Corporation
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2012-04-19 04:04:31 -06:00
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* Copyright (C) 2012 Texas Instruments, Inc.
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2009-09-03 11:14:05 -06:00
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX handle crossbar/shared link difference for L3?
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2010-02-22 22:09:32 -07:00
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* XXX these should be marked initdata for multi-OMAP kernels
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2009-09-03 11:14:05 -06:00
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*/
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2009-10-20 10:40:47 -06:00
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#include <plat/omap_hwmod.h>
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2009-09-03 11:14:05 -06:00
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#include <mach/irqs.h>
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2009-10-20 10:40:47 -06:00
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#include <plat/cpu.h>
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#include <plat/dma.h>
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2010-09-27 08:49:30 -06:00
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#include <plat/serial.h>
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2010-09-29 15:10:12 -06:00
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#include <plat/i2c.h>
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2010-12-07 17:26:56 -07:00
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#include <plat/gpio.h>
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2011-02-24 13:51:46 -07:00
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#include <plat/mcbsp.h>
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2011-02-17 10:53:10 -07:00
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#include <plat/mcspi.h>
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2011-02-23 00:14:05 -07:00
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#include <plat/dmtimer.h>
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2011-03-01 14:12:56 -07:00
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#include <plat/mmc.h>
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2011-02-22 00:51:15 -07:00
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#include <plat/l3_2xxx.h>
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2009-09-03 11:14:05 -06:00
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2010-02-22 22:09:34 -07:00
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#include "omap_hwmod_common_data.h"
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2009-09-03 11:14:05 -06:00
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#include "prm-regbits-24xx.h"
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2010-09-23 08:32:40 -06:00
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#include "cm-regbits-24xx.h"
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OMAP2+: wd_timer: disable on boot via hwmod postsetup mechanism
The OMAP watchdog timer IP blocks require a specific set of register
writes to occur before they will be disabled[1], even if the device
clocks appear to be disabled in the CM_*CLKEN registers. In the MPU
watchdog case, failure to execute this reset sequence will eventually
cause the watchdog to reset the OMAP unexpectedly.
Previously, the code to disable this watchdog was manually called from
mach-omap2/devices.c during device initialization. This causes the
watchdog to be unconditionally disabled for a portion of kernel
initialization. This should be controllable by the board-*.c files,
since some system integrators will want full watchdog coverage of
kernel initialization. Also, the watchdog disable code was not
connected to the hwmod shutdown code. This means that calling
omap_hwmod_shutdown() will not, in fact, disable the watchdog, and the
goal of omap_hwmod_shutdown() is to be able to shutdown any on-chip
OMAP device.
To resolve the latter problem, populate the pre_shutdown pointer in
the watchdog timer hwmod classes with a function that executes the
watchdog shutdown sequence. This allows the hwmod code to fully
disable the watchdog.
Then, to allow some board files to support watchdog coverage
throughout kernel initialization, add common code to mach-omap2/io.c
to cause the MPU watchdog to be disabled on boot unless a board file
specifically requests it to remain enabled. Board files can do this
by changing the watchdog timer hwmod's postsetup state between the
omap2_init_common_infrastructure() and omap2_init_common_devices()
function calls.
1. OMAP34xx Multimedia Device Silicon Revision 3.1.x Rev. ZH
[SWPU222H], Section 16.4.3.6, "Start/Stop Sequence for WDTs (Using
WDTi.WSPR Register)"
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Charulatha Varadarajan <charu@ti.com>
2010-12-21 15:39:15 -07:00
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#include "wd_timer.h"
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2009-09-03 11:14:05 -06:00
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2010-02-22 22:09:32 -07:00
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/*
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* OMAP2430 hardware module integration data
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*
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2012-04-19 04:04:33 -06:00
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* All of the data in this section should be autogeneratable from the
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2010-02-22 22:09:32 -07:00
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* TI hardware database or other technical documentation. Data that
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* is driver-specific or driver-kernel integration-specific belongs
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* elsewhere.
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*/
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2012-04-19 04:04:33 -06:00
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/*
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* IP blocks
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*/
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2011-02-22 00:51:15 -07:00
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2012-04-19 04:04:33 -06:00
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/* IVA2 (IVA2) */
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2010-07-26 16:34:33 -06:00
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static struct omap_hwmod omap2430_iva_hwmod = {
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.name = "iva",
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.class = &iva_hwmod_class,
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};
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2010-09-29 15:10:12 -06:00
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/* I2C common */
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static struct omap_hwmod_class_sysconfig i2c_sysc = {
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.rev_offs = 0x00,
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.sysc_offs = 0x20,
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.syss_offs = 0x10,
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2011-03-10 22:43:05 -07:00
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
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SYSS_HAS_RESET_STATUS),
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2010-09-29 15:10:12 -06:00
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class i2c_class = {
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.name = "i2c",
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.sysc = &i2c_sysc,
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2011-07-10 05:27:15 -06:00
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.rev = OMAP_I2C_IP_VERSION_1,
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2011-07-10 05:27:16 -06:00
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.reset = &omap_i2c_reset,
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2010-09-29 15:10:12 -06:00
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};
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2010-12-21 21:08:34 -07:00
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static struct omap_i2c_dev_attr i2c_dev_attr = {
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2010-09-29 15:10:12 -06:00
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.fifo_depth = 8, /* bytes */
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2011-07-10 05:27:16 -06:00
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.flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
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OMAP_I2C_FLAG_BUS_SHIFT_2 |
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OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
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2010-09-29 15:10:12 -06:00
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};
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2010-12-21 21:08:34 -07:00
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/* I2C1 */
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2010-09-29 15:10:12 -06:00
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static struct omap_hwmod omap2430_i2c1_hwmod = {
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.name = "i2c1",
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2011-07-10 05:27:14 -06:00
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.flags = HWMOD_16BIT_REG,
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2011-07-09 19:14:07 -06:00
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.mpu_irqs = omap2_i2c1_mpu_irqs,
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2011-07-09 19:14:07 -06:00
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.sdma_reqs = omap2_i2c1_sdma_reqs,
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2010-09-29 15:10:12 -06:00
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.main_clk = "i2chs1_fck",
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.prcm = {
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.omap2 = {
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/*
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* NOTE: The CM_FCLKEN* and CM_ICLKEN* for
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* I2CHS IP's do not follow the usual pattern.
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* prcm_reg_id alone cannot be used to program
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* the iclk and fclk. Needs to be handled using
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2011-03-30 19:57:33 -06:00
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* additional flags when clk handling is moved
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2010-09-29 15:10:12 -06:00
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* to hwmod framework.
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*/
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
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},
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},
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.class = &i2c_class,
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2010-12-21 21:08:34 -07:00
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.dev_attr = &i2c_dev_attr,
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2010-09-29 15:10:12 -06:00
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};
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/* I2C2 */
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static struct omap_hwmod omap2430_i2c2_hwmod = {
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.name = "i2c2",
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2011-07-10 05:27:14 -06:00
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.flags = HWMOD_16BIT_REG,
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2011-07-09 19:14:07 -06:00
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.mpu_irqs = omap2_i2c2_mpu_irqs,
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2011-07-09 19:14:07 -06:00
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.sdma_reqs = omap2_i2c2_sdma_reqs,
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2010-09-29 15:10:12 -06:00
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.main_clk = "i2chs2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
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},
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},
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.class = &i2c_class,
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2010-12-21 21:08:34 -07:00
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.dev_attr = &i2c_dev_attr,
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2010-09-29 15:10:12 -06:00
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};
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2010-12-07 17:26:56 -07:00
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/* gpio5 */
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static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
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{ .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
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2011-07-09 19:14:06 -06:00
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{ .irq = -1 }
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2010-12-07 17:26:56 -07:00
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};
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static struct omap_hwmod omap2430_gpio5_hwmod = {
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.name = "gpio5",
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2011-04-05 09:40:15 -06:00
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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2010-12-07 17:26:56 -07:00
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.mpu_irqs = omap243x_gpio5_irqs,
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.main_clk = "gpio5_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 2,
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.module_bit = OMAP2430_EN_GPIO5_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
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},
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},
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2011-07-09 19:14:08 -06:00
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.class = &omap2xxx_gpio_hwmod_class,
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2012-04-19 04:04:33 -06:00
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.dev_attr = &omap2xxx_gpio_dev_attr,
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2010-12-07 17:26:56 -07:00
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};
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2010-12-20 19:27:18 -07:00
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/* dma attributes */
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static struct omap_dma_dev_attr dma_dev_attr = {
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.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
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IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
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.lch_count = 32,
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};
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static struct omap_hwmod omap2430_dma_system_hwmod = {
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.name = "dma",
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2011-07-09 19:14:08 -06:00
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.class = &omap2xxx_dma_hwmod_class,
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2011-07-09 19:14:07 -06:00
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.mpu_irqs = omap2_dma_system_irqs,
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2010-12-20 19:27:18 -07:00
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.main_clk = "core_l3_ck",
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.dev_attr = &dma_dev_attr,
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.flags = HWMOD_NO_IDLEST,
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};
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2011-02-24 13:51:32 -07:00
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/* mailbox */
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static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
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{ .irq = 26 },
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2011-07-09 19:14:06 -06:00
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{ .irq = -1 }
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2011-02-24 13:51:32 -07:00
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};
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static struct omap_hwmod omap2430_mailbox_hwmod = {
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.name = "mailbox",
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2011-07-09 19:14:08 -06:00
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.class = &omap2xxx_mailbox_hwmod_class,
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2011-02-24 13:51:32 -07:00
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.mpu_irqs = omap2430_mailbox_irqs,
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.main_clk = "mailboxes_ick",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
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},
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},
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};
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2011-02-17 10:53:10 -07:00
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/* mcspi3 */
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static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
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{ .irq = 91 },
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2011-07-09 19:14:06 -06:00
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{ .irq = -1 }
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2011-02-17 10:53:10 -07:00
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};
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static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
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{ .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
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{ .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
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{ .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
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{ .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
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2011-07-09 19:14:07 -06:00
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{ .dma_req = -1 }
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2011-02-17 10:53:10 -07:00
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};
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static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
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.num_chipselect = 2,
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};
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static struct omap_hwmod omap2430_mcspi3_hwmod = {
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2012-04-19 04:03:50 -06:00
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.name = "mcspi3",
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2011-02-17 10:53:10 -07:00
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.mpu_irqs = omap2430_mcspi3_mpu_irqs,
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.sdma_reqs = omap2430_mcspi3_sdma_reqs,
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.main_clk = "mcspi3_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 2,
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.module_bit = OMAP2430_EN_MCSPI3_SHIFT,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
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},
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},
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2011-07-09 19:14:08 -06:00
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.class = &omap2xxx_mcspi_class,
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.dev_attr = &omap_mcspi3_dev_attr,
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2011-02-17 10:53:10 -07:00
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};
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2012-04-19 04:04:33 -06:00
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/* usbhsotg */
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2011-02-16 23:37:17 -07:00
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static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
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.rev_offs = 0x0400,
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.sysc_offs = 0x0404,
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.syss_offs = 0x0408,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class usbotg_class = {
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.name = "usbotg",
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.sysc = &omap2430_usbhsotg_sysc,
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};
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/* usb_otg_hs */
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static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
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{ .name = "mc", .irq = 92 },
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{ .name = "dma", .irq = 93 },
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2011-07-09 19:14:06 -06:00
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{ .irq = -1 }
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2011-02-16 23:37:17 -07:00
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};
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static struct omap_hwmod omap2430_usbhsotg_hwmod = {
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.name = "usb_otg_hs",
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.mpu_irqs = omap2430_usbhsotg_mpu_irqs,
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.main_clk = "usbhs_ick",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_USBHS_MASK,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
|
|
|
|
.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.class = &usbotg_class,
|
|
|
|
/*
|
|
|
|
* Erratum ID: i479 idle_req / idle_ack mechanism potentially
|
|
|
|
* broken when autoidle is enabled
|
|
|
|
* workaround is to disable the autoidle bit at module level.
|
|
|
|
*/
|
|
|
|
.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
|
|
|
|
| HWMOD_SWSUP_MSTANDBY,
|
|
|
|
};
|
|
|
|
|
2011-02-24 13:51:46 -07:00
|
|
|
/*
|
|
|
|
* 'mcbsp' class
|
|
|
|
* multi channel buffered serial port controller
|
|
|
|
*/
|
|
|
|
|
|
|
|
static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
|
|
|
|
.rev_offs = 0x007C,
|
|
|
|
.sysc_offs = 0x008C,
|
|
|
|
.sysc_flags = (SYSC_HAS_SOFTRESET),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
|
|
|
|
.name = "mcbsp",
|
|
|
|
.sysc = &omap2430_mcbsp_sysc,
|
|
|
|
.rev = MCBSP_CONFIG_TYPE2,
|
|
|
|
};
|
2011-02-22 11:54:12 -07:00
|
|
|
|
2011-02-24 13:51:46 -07:00
|
|
|
/* mcbsp1 */
|
|
|
|
static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
|
|
|
|
{ .name = "tx", .irq = 59 },
|
|
|
|
{ .name = "rx", .irq = 60 },
|
|
|
|
{ .name = "ovr", .irq = 61 },
|
|
|
|
{ .name = "common", .irq = 64 },
|
2011-07-09 19:14:06 -06:00
|
|
|
{ .irq = -1 }
|
2011-02-24 13:51:46 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap2430_mcbsp1_hwmod = {
|
|
|
|
.name = "mcbsp1",
|
|
|
|
.class = &omap2430_mcbsp_hwmod_class,
|
|
|
|
.mpu_irqs = omap2430_mcbsp1_irqs,
|
2011-07-09 19:14:07 -06:00
|
|
|
.sdma_reqs = omap2_mcbsp1_sdma_reqs,
|
2011-02-24 13:51:46 -07:00
|
|
|
.main_clk = "mcbsp1_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap2 = {
|
|
|
|
.prcm_reg_id = 1,
|
|
|
|
.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
|
|
|
|
.module_offs = CORE_MOD,
|
|
|
|
.idlest_reg_id = 1,
|
|
|
|
.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp2 */
|
|
|
|
static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
|
|
|
|
{ .name = "tx", .irq = 62 },
|
|
|
|
{ .name = "rx", .irq = 63 },
|
|
|
|
{ .name = "common", .irq = 16 },
|
2011-07-09 19:14:06 -06:00
|
|
|
{ .irq = -1 }
|
2011-02-24 13:51:46 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap2430_mcbsp2_hwmod = {
|
|
|
|
.name = "mcbsp2",
|
|
|
|
.class = &omap2430_mcbsp_hwmod_class,
|
|
|
|
.mpu_irqs = omap2430_mcbsp2_irqs,
|
2011-07-09 19:14:07 -06:00
|
|
|
.sdma_reqs = omap2_mcbsp2_sdma_reqs,
|
2011-02-24 13:51:46 -07:00
|
|
|
.main_clk = "mcbsp2_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap2 = {
|
|
|
|
.prcm_reg_id = 1,
|
|
|
|
.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
|
|
|
|
.module_offs = CORE_MOD,
|
|
|
|
.idlest_reg_id = 1,
|
|
|
|
.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp3 */
|
|
|
|
static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
|
|
|
|
{ .name = "tx", .irq = 89 },
|
|
|
|
{ .name = "rx", .irq = 90 },
|
|
|
|
{ .name = "common", .irq = 17 },
|
2011-07-09 19:14:06 -06:00
|
|
|
{ .irq = -1 }
|
2011-02-24 13:51:46 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap2430_mcbsp3_hwmod = {
|
|
|
|
.name = "mcbsp3",
|
|
|
|
.class = &omap2430_mcbsp_hwmod_class,
|
|
|
|
.mpu_irqs = omap2430_mcbsp3_irqs,
|
2011-07-09 19:14:07 -06:00
|
|
|
.sdma_reqs = omap2_mcbsp3_sdma_reqs,
|
2011-02-24 13:51:46 -07:00
|
|
|
.main_clk = "mcbsp3_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap2 = {
|
|
|
|
.prcm_reg_id = 1,
|
|
|
|
.module_bit = OMAP2430_EN_MCBSP3_SHIFT,
|
|
|
|
.module_offs = CORE_MOD,
|
|
|
|
.idlest_reg_id = 2,
|
|
|
|
.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp4 */
|
|
|
|
static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
|
|
|
|
{ .name = "tx", .irq = 54 },
|
|
|
|
{ .name = "rx", .irq = 55 },
|
|
|
|
{ .name = "common", .irq = 18 },
|
2011-07-09 19:14:06 -06:00
|
|
|
{ .irq = -1 }
|
2011-02-24 13:51:46 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
|
|
|
|
{ .name = "rx", .dma_req = 20 },
|
|
|
|
{ .name = "tx", .dma_req = 19 },
|
2011-07-09 19:14:07 -06:00
|
|
|
{ .dma_req = -1 }
|
2011-02-24 13:51:46 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap2430_mcbsp4_hwmod = {
|
|
|
|
.name = "mcbsp4",
|
|
|
|
.class = &omap2430_mcbsp_hwmod_class,
|
|
|
|
.mpu_irqs = omap2430_mcbsp4_irqs,
|
|
|
|
.sdma_reqs = omap2430_mcbsp4_sdma_chs,
|
|
|
|
.main_clk = "mcbsp4_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap2 = {
|
|
|
|
.prcm_reg_id = 1,
|
|
|
|
.module_bit = OMAP2430_EN_MCBSP4_SHIFT,
|
|
|
|
.module_offs = CORE_MOD,
|
|
|
|
.idlest_reg_id = 2,
|
|
|
|
.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* mcbsp5 */
|
|
|
|
static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
|
|
|
|
{ .name = "tx", .irq = 81 },
|
|
|
|
{ .name = "rx", .irq = 82 },
|
|
|
|
{ .name = "common", .irq = 19 },
|
2011-07-09 19:14:06 -06:00
|
|
|
{ .irq = -1 }
|
2011-02-24 13:51:46 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
|
|
|
|
{ .name = "rx", .dma_req = 22 },
|
|
|
|
{ .name = "tx", .dma_req = 21 },
|
2011-07-09 19:14:07 -06:00
|
|
|
{ .dma_req = -1 }
|
2011-02-24 13:51:46 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap2430_mcbsp5_hwmod = {
|
|
|
|
.name = "mcbsp5",
|
|
|
|
.class = &omap2430_mcbsp_hwmod_class,
|
|
|
|
.mpu_irqs = omap2430_mcbsp5_irqs,
|
|
|
|
.sdma_reqs = omap2430_mcbsp5_sdma_chs,
|
|
|
|
.main_clk = "mcbsp5_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap2 = {
|
|
|
|
.prcm_reg_id = 1,
|
|
|
|
.module_bit = OMAP2430_EN_MCBSP5_SHIFT,
|
|
|
|
.module_offs = CORE_MOD,
|
|
|
|
.idlest_reg_id = 2,
|
|
|
|
.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
2011-02-22 11:54:12 -07:00
|
|
|
|
2011-03-01 14:12:55 -07:00
|
|
|
/* MMC/SD/SDIO common */
|
|
|
|
static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
|
|
|
|
.rev_offs = 0x1fc,
|
|
|
|
.sysc_offs = 0x10,
|
|
|
|
.syss_offs = 0x14,
|
|
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
|
|
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
|
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_class omap2430_mmc_class = {
|
|
|
|
.name = "mmc",
|
|
|
|
.sysc = &omap2430_mmc_sysc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* MMC/SD/SDIO1 */
|
|
|
|
static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
|
|
|
|
{ .irq = 83 },
|
2011-07-09 19:14:06 -06:00
|
|
|
{ .irq = -1 }
|
2011-03-01 14:12:55 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
|
|
|
|
{ .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
|
2011-07-09 19:14:07 -06:00
|
|
|
{ .dma_req = -1 }
|
2011-03-01 14:12:55 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
|
|
|
|
{ .role = "dbck", .clk = "mmchsdb1_fck" },
|
|
|
|
};
|
|
|
|
|
2011-03-01 14:12:56 -07:00
|
|
|
static struct omap_mmc_dev_attr mmc1_dev_attr = {
|
|
|
|
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
|
|
|
|
};
|
|
|
|
|
2011-03-01 14:12:55 -07:00
|
|
|
static struct omap_hwmod omap2430_mmc1_hwmod = {
|
|
|
|
.name = "mmc1",
|
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
|
|
.mpu_irqs = omap2430_mmc1_mpu_irqs,
|
|
|
|
.sdma_reqs = omap2430_mmc1_sdma_reqs,
|
|
|
|
.opt_clks = omap2430_mmc1_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
|
|
|
|
.main_clk = "mmchs1_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap2 = {
|
|
|
|
.module_offs = CORE_MOD,
|
|
|
|
.prcm_reg_id = 2,
|
|
|
|
.module_bit = OMAP2430_EN_MMCHS1_SHIFT,
|
|
|
|
.idlest_reg_id = 2,
|
|
|
|
.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
2011-03-01 14:12:56 -07:00
|
|
|
.dev_attr = &mmc1_dev_attr,
|
2011-03-01 14:12:55 -07:00
|
|
|
.class = &omap2430_mmc_class,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* MMC/SD/SDIO2 */
|
|
|
|
static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
|
|
|
|
{ .irq = 86 },
|
2011-07-09 19:14:06 -06:00
|
|
|
{ .irq = -1 }
|
2011-03-01 14:12:55 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
|
|
|
|
{ .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
|
|
|
|
{ .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
|
2011-07-09 19:14:07 -06:00
|
|
|
{ .dma_req = -1 }
|
2011-03-01 14:12:55 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
|
|
|
|
{ .role = "dbck", .clk = "mmchsdb2_fck" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod omap2430_mmc2_hwmod = {
|
|
|
|
.name = "mmc2",
|
|
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
|
|
.mpu_irqs = omap2430_mmc2_mpu_irqs,
|
|
|
|
.sdma_reqs = omap2430_mmc2_sdma_reqs,
|
|
|
|
.opt_clks = omap2430_mmc2_opt_clks,
|
|
|
|
.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
|
|
|
|
.main_clk = "mmchs2_fck",
|
|
|
|
.prcm = {
|
|
|
|
.omap2 = {
|
|
|
|
.module_offs = CORE_MOD,
|
|
|
|
.prcm_reg_id = 2,
|
|
|
|
.module_bit = OMAP2430_EN_MMCHS2_SHIFT,
|
|
|
|
.idlest_reg_id = 2,
|
|
|
|
.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.class = &omap2430_mmc_class,
|
|
|
|
};
|
2011-02-22 11:54:12 -07:00
|
|
|
|
2012-04-19 04:04:33 -06:00
|
|
|
/*
|
|
|
|
* interfaces
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* L3 -> L4_CORE interface */
|
|
|
|
/* l3_core -> usbhsotg interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
|
|
|
|
.master = &omap2430_usbhsotg_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2xxx_l3_main_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "core_l3_ck",
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* L4 CORE -> I2C1 interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_i2c1_hwmod,
|
|
|
|
.clk = "i2c1_ick",
|
|
|
|
.addr = omap2_i2c1_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* L4 CORE -> I2C2 interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_i2c2_hwmod,
|
|
|
|
.clk = "i2c2_ick",
|
|
|
|
.addr = omap2_i2c2_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = OMAP243X_HS_BASE,
|
|
|
|
.pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core ->usbhsotg interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_usbhsotg_hwmod,
|
|
|
|
.clk = "usb_l4_ick",
|
|
|
|
.addr = omap2430_usbhsotg_addrs,
|
|
|
|
.user = OCP_USER_MPU,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* L4 CORE -> MMC1 interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mmc1_hwmod,
|
|
|
|
.clk = "mmchs1_ick",
|
|
|
|
.addr = omap2430_mmc1_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* L4 CORE -> MMC2 interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mmc2_hwmod,
|
|
|
|
.clk = "mmchs2_ick",
|
|
|
|
.addr = omap2430_mmc2_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4 core -> mcspi3 interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mcspi3_hwmod,
|
|
|
|
.clk = "mcspi3_ick",
|
|
|
|
.addr = omap2430_mcspi3_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* IVA2 <- L3 interface */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l3__iva = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l3_main_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_iva_hwmod,
|
|
|
|
.clk = "dsp_fck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x49018000,
|
|
|
|
.pa_end = 0x49018000 + SZ_1K - 1,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> timer1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap2xxx_timer1_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "gpt1_ick",
|
|
|
|
.addr = omap2430_timer1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> wd_timer2 */
|
|
|
|
static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x49016000,
|
|
|
|
.pa_end = 0x4901607f,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap2xxx_wd_timer2_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "mpu_wdt_ick",
|
|
|
|
.addr = omap2430_wd_timer2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> gpio1 */
|
|
|
|
static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4900C000,
|
|
|
|
.pa_end = 0x4900C1ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap2xxx_gpio1_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "gpios_ick",
|
|
|
|
.addr = omap2430_gpio1_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> gpio2 */
|
|
|
|
static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x4900E000,
|
|
|
|
.pa_end = 0x4900E1ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap2xxx_gpio2_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "gpios_ick",
|
|
|
|
.addr = omap2430_gpio2_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> gpio3 */
|
|
|
|
static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x49010000,
|
|
|
|
.pa_end = 0x490101ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap2xxx_gpio3_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "gpios_ick",
|
|
|
|
.addr = omap2430_gpio3_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_wkup -> gpio4 */
|
|
|
|
static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x49012000,
|
|
|
|
.pa_end = 0x490121ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
|
|
.slave = &omap2xxx_gpio4_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "gpios_ick",
|
|
|
|
.addr = omap2430_gpio4_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> gpio5 */
|
|
|
|
static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
|
|
|
|
{
|
|
|
|
.pa_start = 0x480B6000,
|
|
|
|
.pa_end = 0x480B61ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_gpio5_hwmod,
|
|
|
|
.clk = "gpio5_ick",
|
|
|
|
.addr = omap2430_gpio5_addr_space,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* dma_system -> L3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
|
|
|
|
.master = &omap2430_dma_system_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2xxx_l3_main_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.clk = "core_l3_ck",
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> dma_system */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_dma_system_hwmod,
|
|
|
|
.clk = "sdma_ick",
|
|
|
|
.addr = omap2_dma_system_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> mailbox */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mailbox_hwmod,
|
|
|
|
.addr = omap2_mailbox_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> mcbsp1 */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mcbsp1_hwmod,
|
|
|
|
.clk = "mcbsp1_ick",
|
|
|
|
.addr = omap2_mcbsp1_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> mcbsp2 */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mcbsp2_hwmod,
|
|
|
|
.clk = "mcbsp2_ick",
|
|
|
|
.addr = omap2xxx_mcbsp2_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "mpu",
|
|
|
|
.pa_start = 0x4808C000,
|
|
|
|
.pa_end = 0x4808C0ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> mcbsp3 */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mcbsp3_hwmod,
|
|
|
|
.clk = "mcbsp3_ick",
|
|
|
|
.addr = omap2430_mcbsp3_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "mpu",
|
|
|
|
.pa_start = 0x4808E000,
|
|
|
|
.pa_end = 0x4808E0ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> mcbsp4 */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mcbsp4_hwmod,
|
|
|
|
.clk = "mcbsp4_ick",
|
|
|
|
.addr = omap2430_mcbsp4_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
|
|
|
|
{
|
|
|
|
.name = "mpu",
|
|
|
|
.pa_start = 0x48096000,
|
|
|
|
.pa_end = 0x480960ff,
|
|
|
|
.flags = ADDR_TYPE_RT
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* l4_core -> mcbsp5 */
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
|
2012-04-19 04:04:33 -06:00
|
|
|
.master = &omap2xxx_l4_core_hwmod,
|
2012-04-19 04:04:33 -06:00
|
|
|
.slave = &omap2430_mcbsp5_hwmod,
|
|
|
|
.clk = "mcbsp5_ick",
|
|
|
|
.addr = omap2430_mcbsp5_addrs,
|
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
|
};
|
|
|
|
|
2012-04-19 04:04:31 -06:00
|
|
|
static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
|
2012-04-19 04:04:34 -06:00
|
|
|
&omap2xxx_l3_main__l4_core,
|
|
|
|
&omap2xxx_mpu__l3_main,
|
|
|
|
&omap2xxx_dss__l3,
|
2012-04-19 04:04:31 -06:00
|
|
|
&omap2430_usbhsotg__l3,
|
|
|
|
&omap2430_l4_core__i2c1,
|
|
|
|
&omap2430_l4_core__i2c2,
|
2012-04-19 04:04:34 -06:00
|
|
|
&omap2xxx_l4_core__l4_wkup,
|
2012-04-19 04:04:31 -06:00
|
|
|
&omap2_l4_core__uart1,
|
|
|
|
&omap2_l4_core__uart2,
|
|
|
|
&omap2_l4_core__uart3,
|
|
|
|
&omap2430_l4_core__usbhsotg,
|
|
|
|
&omap2430_l4_core__mmc1,
|
|
|
|
&omap2430_l4_core__mmc2,
|
2012-04-19 04:04:34 -06:00
|
|
|
&omap2xxx_l4_core__mcspi1,
|
|
|
|
&omap2xxx_l4_core__mcspi2,
|
2012-04-19 04:04:31 -06:00
|
|
|
&omap2430_l4_core__mcspi3,
|
|
|
|
&omap2430_l3__iva,
|
|
|
|
&omap2430_l4_wkup__timer1,
|
2012-04-19 04:04:34 -06:00
|
|
|
&omap2xxx_l4_core__timer2,
|
|
|
|
&omap2xxx_l4_core__timer3,
|
|
|
|
&omap2xxx_l4_core__timer4,
|
|
|
|
&omap2xxx_l4_core__timer5,
|
|
|
|
&omap2xxx_l4_core__timer6,
|
|
|
|
&omap2xxx_l4_core__timer7,
|
|
|
|
&omap2xxx_l4_core__timer8,
|
|
|
|
&omap2xxx_l4_core__timer9,
|
|
|
|
&omap2xxx_l4_core__timer10,
|
|
|
|
&omap2xxx_l4_core__timer11,
|
|
|
|
&omap2xxx_l4_core__timer12,
|
2012-04-19 04:04:31 -06:00
|
|
|
&omap2430_l4_wkup__wd_timer2,
|
2012-04-19 04:04:34 -06:00
|
|
|
&omap2xxx_l4_core__dss,
|
|
|
|
&omap2xxx_l4_core__dss_dispc,
|
|
|
|
&omap2xxx_l4_core__dss_rfbi,
|
|
|
|
&omap2xxx_l4_core__dss_venc,
|
2012-04-19 04:04:31 -06:00
|
|
|
&omap2430_l4_wkup__gpio1,
|
|
|
|
&omap2430_l4_wkup__gpio2,
|
|
|
|
&omap2430_l4_wkup__gpio3,
|
|
|
|
&omap2430_l4_wkup__gpio4,
|
|
|
|
&omap2430_l4_core__gpio5,
|
|
|
|
&omap2430_dma_system__l3,
|
|
|
|
&omap2430_l4_core__dma_system,
|
|
|
|
&omap2430_l4_core__mailbox,
|
|
|
|
&omap2430_l4_core__mcbsp1,
|
|
|
|
&omap2430_l4_core__mcbsp2,
|
|
|
|
&omap2430_l4_core__mcbsp3,
|
|
|
|
&omap2430_l4_core__mcbsp4,
|
|
|
|
&omap2430_l4_core__mcbsp5,
|
2009-09-03 11:14:05 -06:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2010-02-22 22:09:32 -07:00
|
|
|
int __init omap2430_hwmod_init(void)
|
|
|
|
{
|
2012-04-19 04:04:31 -06:00
|
|
|
return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
|
2010-02-22 22:09:32 -07:00
|
|
|
}
|