2009-05-28 14:23:52 -06:00
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/*
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* linux/arch/arm/mach-omap2/gpmc-onenand.c
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*
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* Copyright (C) 2006 - 2009 Nokia Corporation
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* Contacts: Juha Yrjola
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* Tony Lindgren
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2011-07-31 08:52:44 -06:00
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#include <linux/string.h>
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2009-05-28 14:23:52 -06:00
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/onenand_regs.h>
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#include <linux/io.h>
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2012-08-24 07:21:06 -06:00
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#include <linux/platform_data/mtd-onenand-omap2.h>
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2012-06-04 22:41:48 -06:00
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#include <linux/err.h>
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2009-05-28 14:23:52 -06:00
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#include <asm/mach/flash.h>
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2012-10-04 23:07:27 -06:00
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#include "gpmc.h"
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2012-08-31 11:59:07 -06:00
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#include "soc.h"
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2012-09-28 23:02:42 -06:00
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#include "gpmc-onenand.h"
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2012-08-31 11:59:07 -06:00
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2012-08-30 13:53:23 -06:00
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#define ONENAND_IO_SIZE SZ_128K
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2012-06-04 22:41:48 -06:00
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#define ONENAND_FLAG_SYNCREAD (1 << 0)
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#define ONENAND_FLAG_SYNCWRITE (1 << 1)
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#define ONENAND_FLAG_HF (1 << 2)
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#define ONENAND_FLAG_VHF (1 << 3)
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static unsigned onenand_flags;
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static unsigned latency;
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2009-05-28 14:23:52 -06:00
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static struct omap_onenand_platform_data *gpmc_onenand_data;
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2012-08-30 13:53:23 -06:00
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static struct resource gpmc_onenand_resource = {
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.flags = IORESOURCE_MEM,
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};
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2009-05-28 14:23:52 -06:00
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static struct platform_device gpmc_onenand_device = {
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.name = "omap2-onenand",
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.id = -1,
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2012-08-30 13:53:23 -06:00
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.num_resources = 1,
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.resource = &gpmc_onenand_resource,
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2009-05-28 14:23:52 -06:00
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};
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2012-06-04 22:41:48 -06:00
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static struct gpmc_timings omap2_onenand_calc_async_timings(void)
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2009-05-28 14:23:52 -06:00
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{
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2012-11-09 05:35:17 -07:00
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struct gpmc_device_timings dev_t;
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2009-05-28 14:23:52 -06:00
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struct gpmc_timings t;
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_aavdh = 7;
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const int t_ce = 76;
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const int t_aa = 76;
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const int t_oe = 20;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_wpl = 40;
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const int t_wph = 30;
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2012-11-09 05:35:17 -07:00
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memset(&dev_t, 0, sizeof(dev_t));
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dev_t.mux = true;
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dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
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dev_t.t_avdp_w = dev_t.t_avdp_r;
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dev_t.t_aavdh = t_aavdh * 1000;
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dev_t.t_aa = t_aa * 1000;
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dev_t.t_ce = t_ce * 1000;
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dev_t.t_oe = t_oe * 1000;
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dev_t.t_cez_r = t_cez * 1000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.t_wpl = t_wpl * 1000;
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dev_t.t_wph = t_wph * 1000;
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gpmc_calc_timings(&t, &dev_t);
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2009-05-28 14:23:52 -06:00
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2012-06-04 22:41:48 -06:00
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return t;
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}
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static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
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{
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2009-05-28 14:23:52 -06:00
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/* Configure GPMC for asynchronous read */
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
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GPMC_CONFIG1_DEVICESIZE_16 |
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GPMC_CONFIG1_MUXADDDATA);
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2012-06-04 22:41:48 -06:00
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return gpmc_cs_set_timings(cs, t);
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}
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static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
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{
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u32 reg;
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2009-06-23 04:30:24 -06:00
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/* Ensure sync read and sync write are disabled */
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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2009-05-28 14:23:52 -06:00
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}
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2012-06-04 22:41:48 -06:00
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static void set_onenand_cfg(void __iomem *onenand_base)
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2009-05-28 14:23:52 -06:00
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{
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u32 reg;
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
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reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
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ONENAND_SYS_CFG1_BL_16;
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2012-06-04 22:41:48 -06:00
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if (onenand_flags & ONENAND_FLAG_SYNCREAD)
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2009-05-28 14:23:52 -06:00
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reg |= ONENAND_SYS_CFG1_SYNC_READ;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
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2012-06-04 22:41:48 -06:00
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
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2009-05-28 14:23:52 -06:00
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reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
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2012-06-04 22:41:48 -06:00
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if (onenand_flags & ONENAND_FLAG_HF)
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2009-05-28 14:23:52 -06:00
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reg |= ONENAND_SYS_CFG1_HF;
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else
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reg &= ~ONENAND_SYS_CFG1_HF;
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2012-06-04 22:41:48 -06:00
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if (onenand_flags & ONENAND_FLAG_VHF)
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2011-02-07 01:46:58 -07:00
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reg |= ONENAND_SYS_CFG1_VHF;
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else
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reg &= ~ONENAND_SYS_CFG1_VHF;
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2009-05-28 14:23:52 -06:00
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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}
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2011-02-07 01:47:00 -07:00
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static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
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2012-06-28 12:41:29 -06:00
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void __iomem *onenand_base)
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2011-02-07 01:47:00 -07:00
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{
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u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
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2012-06-28 12:41:29 -06:00
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int freq;
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2011-02-07 01:47:00 -07:00
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switch ((ver >> 4) & 0xf) {
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case 0:
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freq = 40;
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break;
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case 1:
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freq = 54;
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break;
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case 2:
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freq = 66;
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break;
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case 3:
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freq = 83;
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break;
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case 4:
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freq = 104;
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break;
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default:
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freq = 54;
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break;
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}
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return freq;
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}
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2012-06-04 22:41:48 -06:00
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static struct gpmc_timings
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omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
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2012-06-28 12:41:29 -06:00
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int freq)
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2009-05-28 14:23:52 -06:00
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{
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2012-11-09 05:35:17 -07:00
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struct gpmc_device_timings dev_t;
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2009-05-28 14:23:52 -06:00
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struct gpmc_timings t;
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_wpl = 40;
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const int t_wph = 30;
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int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
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2012-11-09 05:35:17 -07:00
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int div, gpmc_clk_ns;
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2009-05-28 14:23:52 -06:00
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2012-06-04 22:41:48 -06:00
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if (cfg->flags & ONENAND_SYNC_READ)
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onenand_flags = ONENAND_FLAG_SYNCREAD;
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else if (cfg->flags & ONENAND_SYNC_READWRITE)
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onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
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2009-05-28 14:23:52 -06:00
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switch (freq) {
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2010-12-09 02:22:50 -07:00
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case 104:
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min_gpmc_clk_period = 9600; /* 104 MHz */
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t_ces = 3;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 3;
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t_aavdh = 6;
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2011-02-07 01:46:58 -07:00
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t_rdyo = 6;
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2010-12-09 02:22:50 -07:00
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break;
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2009-05-28 14:23:52 -06:00
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case 83:
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2010-12-09 01:48:27 -07:00
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min_gpmc_clk_period = 12000; /* 83 MHz */
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2009-05-28 14:23:52 -06:00
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t_ces = 5;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 9;
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break;
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case 66:
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2010-12-09 01:48:27 -07:00
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min_gpmc_clk_period = 15000; /* 66 MHz */
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2009-05-28 14:23:52 -06:00
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t_ces = 6;
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t_avds = 5;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 11;
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break;
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default:
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2010-12-09 01:48:27 -07:00
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min_gpmc_clk_period = 18500; /* 54 MHz */
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2009-05-28 14:23:52 -06:00
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t_ces = 7;
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t_avds = 7;
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t_avdh = 7;
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t_ach = 9;
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t_aavdh = 7;
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t_rdyo = 15;
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2012-06-04 22:41:48 -06:00
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onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
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2009-05-28 14:23:52 -06:00
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break;
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}
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2012-08-19 06:59:45 -06:00
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div = gpmc_calc_divider(min_gpmc_clk_period);
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2009-05-28 14:23:52 -06:00
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gpmc_clk_ns = gpmc_ticks_to_ns(div);
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if (gpmc_clk_ns < 15) /* >66Mhz */
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2012-06-04 22:41:48 -06:00
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onenand_flags |= ONENAND_FLAG_HF;
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else
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onenand_flags &= ~ONENAND_FLAG_HF;
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2011-02-07 01:46:58 -07:00
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if (gpmc_clk_ns < 12) /* >83Mhz */
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2012-06-04 22:41:48 -06:00
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onenand_flags |= ONENAND_FLAG_VHF;
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else
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onenand_flags &= ~ONENAND_FLAG_VHF;
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if (onenand_flags & ONENAND_FLAG_VHF)
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2011-02-07 01:46:58 -07:00
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latency = 8;
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2012-06-04 22:41:48 -06:00
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else if (onenand_flags & ONENAND_FLAG_HF)
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2009-05-28 14:23:52 -06:00
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latency = 6;
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else if (gpmc_clk_ns >= 25) /* 40 MHz*/
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latency = 3;
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else
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latency = 4;
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2012-06-04 22:41:48 -06:00
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/* Set synchronous read timings */
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2012-11-09 05:35:17 -07:00
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memset(&dev_t, 0, sizeof(dev_t));
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2009-05-28 14:23:52 -06:00
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2012-11-09 05:35:17 -07:00
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dev_t.mux = true;
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dev_t.sync_read = true;
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2012-06-04 22:41:48 -06:00
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
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2012-11-09 05:35:17 -07:00
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dev_t.sync_write = true;
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2009-05-28 14:23:52 -06:00
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} else {
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2012-11-09 05:35:17 -07:00
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dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
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dev_t.t_wpl = t_wpl * 1000;
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dev_t.t_wph = t_wph * 1000;
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dev_t.t_aavdh = t_aavdh * 1000;
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2009-05-28 14:23:52 -06:00
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}
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2012-11-09 05:35:17 -07:00
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dev_t.ce_xdelay = true;
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dev_t.avd_xdelay = true;
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dev_t.oe_xdelay = true;
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dev_t.we_xdelay = true;
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dev_t.clk = min_gpmc_clk_period;
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dev_t.t_bacc = dev_t.clk;
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dev_t.t_ces = t_ces * 1000;
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dev_t.t_avds = t_avds * 1000;
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dev_t.t_avdh = t_avdh * 1000;
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dev_t.t_ach = t_ach * 1000;
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dev_t.cyc_iaa = (latency + 1);
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dev_t.t_cez_r = t_cez * 1000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.cyc_aavdh_oe = 1;
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dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
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gpmc_calc_timings(&t, &dev_t);
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2009-05-28 14:23:52 -06:00
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2012-06-04 22:41:48 -06:00
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return t;
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}
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static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
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{
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unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
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unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
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2009-05-28 14:23:52 -06:00
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/* Configure GPMC for synchronous read */
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
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GPMC_CONFIG1_WRAPBURST_SUPP |
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GPMC_CONFIG1_READMULTIPLE_SUPP |
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(sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
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(sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
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(sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
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GPMC_CONFIG1_PAGE_LEN(2) |
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(cpu_is_omap34xx() ? 0 :
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(GPMC_CONFIG1_WAIT_READ_MON |
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GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
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GPMC_CONFIG1_DEVICESIZE_16 |
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GPMC_CONFIG1_DEVICETYPE_NOR |
|
|
|
|
GPMC_CONFIG1_MUXADDDATA);
|
|
|
|
|
2012-06-04 22:41:48 -06:00
|
|
|
return gpmc_cs_set_timings(cs, t);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap2_onenand_setup_async(void __iomem *onenand_base)
|
|
|
|
{
|
|
|
|
struct gpmc_timings t;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
omap2_onenand_set_async_mode(onenand_base);
|
|
|
|
|
|
|
|
t = omap2_onenand_calc_async_timings();
|
|
|
|
|
|
|
|
ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
|
|
|
|
if (IS_ERR_VALUE(ret))
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
omap2_onenand_set_async_mode(onenand_base);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
|
|
|
|
{
|
|
|
|
int ret, freq = *freq_ptr;
|
|
|
|
struct gpmc_timings t;
|
|
|
|
|
|
|
|
if (!freq) {
|
|
|
|
/* Very first call freq is not known */
|
2012-06-28 12:41:29 -06:00
|
|
|
freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
|
2012-06-04 22:41:48 -06:00
|
|
|
set_onenand_cfg(onenand_base);
|
|
|
|
}
|
|
|
|
|
2012-06-28 12:41:29 -06:00
|
|
|
t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
|
2009-05-28 14:23:52 -06:00
|
|
|
|
2012-06-04 22:41:48 -06:00
|
|
|
ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
|
|
|
|
if (IS_ERR_VALUE(ret))
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
set_onenand_cfg(onenand_base);
|
2009-05-28 14:23:52 -06:00
|
|
|
|
2011-02-07 01:46:59 -07:00
|
|
|
*freq_ptr = freq;
|
|
|
|
|
2009-05-28 14:23:52 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-07 01:46:59 -07:00
|
|
|
static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
|
2009-05-28 14:23:52 -06:00
|
|
|
{
|
|
|
|
struct device *dev = &gpmc_onenand_device.dev;
|
2012-06-04 22:41:48 -06:00
|
|
|
unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
|
|
|
|
int ret;
|
2009-05-28 14:23:52 -06:00
|
|
|
|
2012-06-04 22:41:48 -06:00
|
|
|
ret = omap2_onenand_setup_async(onenand_base);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "unable to set to async mode\n");
|
|
|
|
return ret;
|
2009-05-28 14:23:52 -06:00
|
|
|
}
|
|
|
|
|
2012-06-04 22:41:48 -06:00
|
|
|
if (!(gpmc_onenand_data->flags & l))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
|
|
|
|
if (ret)
|
|
|
|
dev_err(dev, "unable to set to sync mode\n");
|
|
|
|
return ret;
|
2009-05-28 14:23:52 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
|
|
|
{
|
2012-08-30 13:53:23 -06:00
|
|
|
int err;
|
|
|
|
|
2009-05-28 14:23:52 -06:00
|
|
|
gpmc_onenand_data = _onenand_data;
|
|
|
|
gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
|
|
|
|
gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
|
|
|
|
|
|
|
|
if (cpu_is_omap24xx() &&
|
|
|
|
(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
|
|
|
|
printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
|
|
|
|
gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
|
|
|
|
gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
|
|
|
|
}
|
|
|
|
|
2012-10-05 00:09:54 -06:00
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
|
|
|
|
else
|
|
|
|
gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
|
|
|
|
|
2012-08-30 13:53:23 -06:00
|
|
|
err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
|
|
|
|
(unsigned long *)&gpmc_onenand_resource.start);
|
|
|
|
if (err < 0) {
|
|
|
|
pr_err("%s: Cannot request GPMC CS\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
gpmc_onenand_resource.end = gpmc_onenand_resource.start +
|
|
|
|
ONENAND_IO_SIZE - 1;
|
|
|
|
|
2009-05-28 14:23:52 -06:00
|
|
|
if (platform_device_register(&gpmc_onenand_device) < 0) {
|
2012-08-30 13:53:23 -06:00
|
|
|
pr_err("%s: Unable to register OneNAND device\n", __func__);
|
|
|
|
gpmc_cs_free(gpmc_onenand_data->cs);
|
2009-05-28 14:23:52 -06:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|