2017-02-15 03:15:20 -07:00
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/*
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* Actions Semi S500 SoC
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*
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* Copyright (c) 2016-2017 Andreas Färber
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "actions,s500";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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};
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x0>;
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2017-02-26 09:24:54 -07:00
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enable-method = "actions,s500-smp";
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2017-02-15 03:15:20 -07:00
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x1>;
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2017-02-26 09:24:54 -07:00
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enable-method = "actions,s500-smp";
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2017-02-15 03:15:20 -07:00
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x2>;
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2017-02-26 09:24:54 -07:00
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enable-method = "actions,s500-smp";
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2017-02-15 03:15:20 -07:00
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x3>;
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2017-02-26 09:24:54 -07:00
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enable-method = "actions,s500-smp";
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2017-02-15 03:15:20 -07:00
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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hosc: hosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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scu: scu@b0020000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xb0020000 0x100>;
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};
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global_timer: timer@b0020200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xb0020200 0x100>;
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interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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status = "disabled";
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};
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twd_timer: timer@b0020600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xb0020600 0x20>;
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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status = "disabled";
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};
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twd_wdt: wdt@b0020620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0xb0020620 0xe0>;
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interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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status = "disabled";
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};
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gic: interrupt-controller@b0021000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0xb0021000 0x1000>,
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<0xb0020100 0x0100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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l2: cache-controller@b0022000 {
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compatible = "arm,pl310-cache";
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reg = <0xb0022000 0x1000>;
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cache-unified;
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cache-level = <2>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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arm,tag-latency = <3 3 2>;
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arm,data-latency = <5 3 3>;
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};
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uart0: serial@b0120000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0120000 0x2000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@b0122000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0122000 0x2000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart2: serial@b0124000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0124000 0x2000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart3: serial@b0126000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0126000 0x2000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart4: serial@b0128000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb0128000 0x2000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart5: serial@b012a000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb012a000 0x2000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart6: serial@b012c000 {
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compatible = "actions,s500-uart", "actions,owl-uart";
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reg = <0xb012c000 0x2000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer: timer@b0168000 {
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compatible = "actions,s500-timer";
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reg = <0xb0168000 0x8000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
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};
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2017-02-25 20:08:53 -07:00
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sps: power-controller@b01b0100 {
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compatible = "actions,s500-sps";
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reg = <0xb01b0100 0x100>;
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#power-domain-cells = <1>;
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};
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2017-02-15 03:15:20 -07:00
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};
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};
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