alistair23-linux/arch/sparc/kernel/cpumap.c

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 08:07:57 -06:00
// SPDX-License-Identifier: GPL-2.0
sparc64: fix and optimize irq distribution irq_choose_cpu() should compare the affinity mask against cpu_online_map rather than CPU_MASK_ALL, since irq_select_affinity() sets the interrupt's affinity mask to cpu_online_map "and" CPU_MASK_ALL (which ends up being just cpu_online_map). The mask comparison in irq_choose_cpu() will always fail since the two masks are not the same. So the CPU chosen is the first CPU in the intersection of cpu_online_map and CPU_MASK_ALL, which is always CPU0. That means all interrupts are reassigned to CPU0... Distributing interrupts to CPUs in a linearly increasing round robin fashion is not optimal for the UltraSPARC T1/T2. Also, the irq_rover in irq_choose_cpu() causes an interrupt to be assigned to a different processor each time the interrupt is allocated and released. This may lead to an unbalanced distribution over time. A static mapping of interrupts to processors is done to optimize and balance interrupt distribution. For the T1/T2, interrupts are spread to different cores first, and then to strands within a core. The following is some benchmarks showing the effects of interrupt distribution on a T2. The test was done with iperf using a pair of T5220 boxes, each with a 10GBe NIU (XAUI) connected back to back. TCP | Stock Linear RR IRQ Optimized IRQ Streams | 2.6.30-rc5 Distribution Distribution | GBits/sec GBits/sec GBits/sec --------+----------------------------------------- 1 0.839 0.862 0.868 8 1.16 4.96 5.88 16 1.15 6.40 8.04 100 1.09 7.28 8.68 Signed-off-by: Hong H. Pham <hong.pham@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-06-04 03:10:11 -06:00
/* cpumap.c: used for optimizing CPU assignment
*
* Copyright (C) 2009 Hong H. Pham <hong.pham@windriver.com>
*/
#include <linux/export.h>
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
#include <linux/slab.h>
sparc64: fix and optimize irq distribution irq_choose_cpu() should compare the affinity mask against cpu_online_map rather than CPU_MASK_ALL, since irq_select_affinity() sets the interrupt's affinity mask to cpu_online_map "and" CPU_MASK_ALL (which ends up being just cpu_online_map). The mask comparison in irq_choose_cpu() will always fail since the two masks are not the same. So the CPU chosen is the first CPU in the intersection of cpu_online_map and CPU_MASK_ALL, which is always CPU0. That means all interrupts are reassigned to CPU0... Distributing interrupts to CPUs in a linearly increasing round robin fashion is not optimal for the UltraSPARC T1/T2. Also, the irq_rover in irq_choose_cpu() causes an interrupt to be assigned to a different processor each time the interrupt is allocated and released. This may lead to an unbalanced distribution over time. A static mapping of interrupts to processors is done to optimize and balance interrupt distribution. For the T1/T2, interrupts are spread to different cores first, and then to strands within a core. The following is some benchmarks showing the effects of interrupt distribution on a T2. The test was done with iperf using a pair of T5220 boxes, each with a 10GBe NIU (XAUI) connected back to back. TCP | Stock Linear RR IRQ Optimized IRQ Streams | 2.6.30-rc5 Distribution Distribution | GBits/sec GBits/sec GBits/sec --------+----------------------------------------- 1 0.839 0.862 0.868 8 1.16 4.96 5.88 16 1.15 6.40 8.04 100 1.09 7.28 8.68 Signed-off-by: Hong H. Pham <hong.pham@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-06-04 03:10:11 -06:00
#include <linux/kernel.h>
#include <linux/cpumask.h>
#include <linux/spinlock.h>
#include <asm/cpudata.h>
#include "cpumap.h"
enum {
CPUINFO_LVL_ROOT = 0,
CPUINFO_LVL_NODE,
CPUINFO_LVL_CORE,
CPUINFO_LVL_PROC,
CPUINFO_LVL_MAX,
};
enum {
ROVER_NO_OP = 0,
/* Increment rover every time level is visited */
ROVER_INC_ON_VISIT = 1 << 0,
/* Increment parent's rover every time rover wraps around */
ROVER_INC_PARENT_ON_LOOP = 1 << 1,
};
struct cpuinfo_node {
int id;
int level;
int num_cpus; /* Number of CPUs in this hierarchy */
int parent_index;
int child_start; /* Array index of the first child node */
int child_end; /* Array index of the last child node */
int rover; /* Child node iterator */
};
struct cpuinfo_level {
int start_index; /* Index of first node of a level in a cpuinfo tree */
int end_index; /* Index of last node of a level in a cpuinfo tree */
int num_nodes; /* Number of nodes in a level in a cpuinfo tree */
};
struct cpuinfo_tree {
int total_nodes;
/* Offsets into nodes[] for each level of the tree */
struct cpuinfo_level level[CPUINFO_LVL_MAX];
sparc64: Replace zero-length array with flexible-array The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] sizeof(flexible-array-member) triggers a warning because flexible array members have incomplete type[1]. There are some instances of code in which the sizeof operator is being incorrectly/erroneously applied to zero-length arrays and the result is zero. Such instances may be hiding some bugs. So, this work (flexible-array member conversions) will also help to get completely rid of those sorts of issues. This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-05-07 13:23:02 -06:00
struct cpuinfo_node nodes[];
sparc64: fix and optimize irq distribution irq_choose_cpu() should compare the affinity mask against cpu_online_map rather than CPU_MASK_ALL, since irq_select_affinity() sets the interrupt's affinity mask to cpu_online_map "and" CPU_MASK_ALL (which ends up being just cpu_online_map). The mask comparison in irq_choose_cpu() will always fail since the two masks are not the same. So the CPU chosen is the first CPU in the intersection of cpu_online_map and CPU_MASK_ALL, which is always CPU0. That means all interrupts are reassigned to CPU0... Distributing interrupts to CPUs in a linearly increasing round robin fashion is not optimal for the UltraSPARC T1/T2. Also, the irq_rover in irq_choose_cpu() causes an interrupt to be assigned to a different processor each time the interrupt is allocated and released. This may lead to an unbalanced distribution over time. A static mapping of interrupts to processors is done to optimize and balance interrupt distribution. For the T1/T2, interrupts are spread to different cores first, and then to strands within a core. The following is some benchmarks showing the effects of interrupt distribution on a T2. The test was done with iperf using a pair of T5220 boxes, each with a 10GBe NIU (XAUI) connected back to back. TCP | Stock Linear RR IRQ Optimized IRQ Streams | 2.6.30-rc5 Distribution Distribution | GBits/sec GBits/sec GBits/sec --------+----------------------------------------- 1 0.839 0.862 0.868 8 1.16 4.96 5.88 16 1.15 6.40 8.04 100 1.09 7.28 8.68 Signed-off-by: Hong H. Pham <hong.pham@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-06-04 03:10:11 -06:00
};
static struct cpuinfo_tree *cpuinfo_tree;
static u16 cpu_distribution_map[NR_CPUS];
static DEFINE_SPINLOCK(cpu_map_lock);
/* Niagara optimized cpuinfo tree traversal. */
static const int niagara_iterate_method[] = {
[CPUINFO_LVL_ROOT] = ROVER_NO_OP,
/* Strands (or virtual CPUs) within a core may not run concurrently
* on the Niagara, as instruction pipeline(s) are shared. Distribute
* work to strands in different cores first for better concurrency.
* Go to next NUMA node when all cores are used.
*/
[CPUINFO_LVL_NODE] = ROVER_INC_ON_VISIT|ROVER_INC_PARENT_ON_LOOP,
/* Strands are grouped together by proc_id in cpuinfo_sparc, i.e.
* a proc_id represents an instruction pipeline. Distribute work to
* strands in different proc_id groups if the core has multiple
* instruction pipelines (e.g. the Niagara 2/2+ has two).
*/
[CPUINFO_LVL_CORE] = ROVER_INC_ON_VISIT,
/* Pick the next strand in the proc_id group. */
[CPUINFO_LVL_PROC] = ROVER_INC_ON_VISIT,
};
/* Generic cpuinfo tree traversal. Distribute work round robin across NUMA
* nodes.
*/
static const int generic_iterate_method[] = {
[CPUINFO_LVL_ROOT] = ROVER_INC_ON_VISIT,
[CPUINFO_LVL_NODE] = ROVER_NO_OP,
[CPUINFO_LVL_CORE] = ROVER_INC_PARENT_ON_LOOP,
[CPUINFO_LVL_PROC] = ROVER_INC_ON_VISIT|ROVER_INC_PARENT_ON_LOOP,
};
static int cpuinfo_id(int cpu, int level)
{
int id;
switch (level) {
case CPUINFO_LVL_ROOT:
id = 0;
break;
case CPUINFO_LVL_NODE:
id = cpu_to_node(cpu);
break;
case CPUINFO_LVL_CORE:
id = cpu_data(cpu).core_id;
break;
case CPUINFO_LVL_PROC:
id = cpu_data(cpu).proc_id;
break;
default:
id = -EINVAL;
}
return id;
}
/*
* Enumerate the CPU information in __cpu_data to determine the start index,
* end index, and number of nodes for each level in the cpuinfo tree. The
* total number of cpuinfo nodes required to build the tree is returned.
*/
static int enumerate_cpuinfo_nodes(struct cpuinfo_level *tree_level)
{
int prev_id[CPUINFO_LVL_MAX];
int i, n, num_nodes;
for (i = CPUINFO_LVL_ROOT; i < CPUINFO_LVL_MAX; i++) {
struct cpuinfo_level *lv = &tree_level[i];
prev_id[i] = -1;
lv->start_index = lv->end_index = lv->num_nodes = 0;
}
num_nodes = 1; /* Include the root node */
for (i = 0; i < num_possible_cpus(); i++) {
if (!cpu_online(i))
continue;
n = cpuinfo_id(i, CPUINFO_LVL_NODE);
if (n > prev_id[CPUINFO_LVL_NODE]) {
tree_level[CPUINFO_LVL_NODE].num_nodes++;
prev_id[CPUINFO_LVL_NODE] = n;
num_nodes++;
}
n = cpuinfo_id(i, CPUINFO_LVL_CORE);
if (n > prev_id[CPUINFO_LVL_CORE]) {
tree_level[CPUINFO_LVL_CORE].num_nodes++;
prev_id[CPUINFO_LVL_CORE] = n;
num_nodes++;
}
n = cpuinfo_id(i, CPUINFO_LVL_PROC);
if (n > prev_id[CPUINFO_LVL_PROC]) {
tree_level[CPUINFO_LVL_PROC].num_nodes++;
prev_id[CPUINFO_LVL_PROC] = n;
num_nodes++;
}
}
tree_level[CPUINFO_LVL_ROOT].num_nodes = 1;
n = tree_level[CPUINFO_LVL_NODE].num_nodes;
tree_level[CPUINFO_LVL_NODE].start_index = 1;
tree_level[CPUINFO_LVL_NODE].end_index = n;
n++;
tree_level[CPUINFO_LVL_CORE].start_index = n;
n += tree_level[CPUINFO_LVL_CORE].num_nodes;
tree_level[CPUINFO_LVL_CORE].end_index = n - 1;
tree_level[CPUINFO_LVL_PROC].start_index = n;
n += tree_level[CPUINFO_LVL_PROC].num_nodes;
tree_level[CPUINFO_LVL_PROC].end_index = n - 1;
return num_nodes;
}
/* Build a tree representation of the CPU hierarchy using the per CPU
* information in __cpu_data. Entries in __cpu_data[0..NR_CPUS] are
* assumed to be sorted in ascending order based on node, core_id, and
* proc_id (in order of significance).
*/
static struct cpuinfo_tree *build_cpuinfo_tree(void)
{
struct cpuinfo_tree *new_tree;
struct cpuinfo_node *node;
struct cpuinfo_level tmp_level[CPUINFO_LVL_MAX];
int num_cpus[CPUINFO_LVL_MAX];
int level_rover[CPUINFO_LVL_MAX];
int prev_id[CPUINFO_LVL_MAX];
int n, id, cpu, prev_cpu, last_cpu, level;
n = enumerate_cpuinfo_nodes(tmp_level);
new_tree = kzalloc(struct_size(new_tree, nodes, n), GFP_ATOMIC);
sparc64: fix and optimize irq distribution irq_choose_cpu() should compare the affinity mask against cpu_online_map rather than CPU_MASK_ALL, since irq_select_affinity() sets the interrupt's affinity mask to cpu_online_map "and" CPU_MASK_ALL (which ends up being just cpu_online_map). The mask comparison in irq_choose_cpu() will always fail since the two masks are not the same. So the CPU chosen is the first CPU in the intersection of cpu_online_map and CPU_MASK_ALL, which is always CPU0. That means all interrupts are reassigned to CPU0... Distributing interrupts to CPUs in a linearly increasing round robin fashion is not optimal for the UltraSPARC T1/T2. Also, the irq_rover in irq_choose_cpu() causes an interrupt to be assigned to a different processor each time the interrupt is allocated and released. This may lead to an unbalanced distribution over time. A static mapping of interrupts to processors is done to optimize and balance interrupt distribution. For the T1/T2, interrupts are spread to different cores first, and then to strands within a core. The following is some benchmarks showing the effects of interrupt distribution on a T2. The test was done with iperf using a pair of T5220 boxes, each with a 10GBe NIU (XAUI) connected back to back. TCP | Stock Linear RR IRQ Optimized IRQ Streams | 2.6.30-rc5 Distribution Distribution | GBits/sec GBits/sec GBits/sec --------+----------------------------------------- 1 0.839 0.862 0.868 8 1.16 4.96 5.88 16 1.15 6.40 8.04 100 1.09 7.28 8.68 Signed-off-by: Hong H. Pham <hong.pham@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-06-04 03:10:11 -06:00
if (!new_tree)
return NULL;
new_tree->total_nodes = n;
memcpy(&new_tree->level, tmp_level, sizeof(tmp_level));
prev_cpu = cpu = cpumask_first(cpu_online_mask);
sparc64: fix and optimize irq distribution irq_choose_cpu() should compare the affinity mask against cpu_online_map rather than CPU_MASK_ALL, since irq_select_affinity() sets the interrupt's affinity mask to cpu_online_map "and" CPU_MASK_ALL (which ends up being just cpu_online_map). The mask comparison in irq_choose_cpu() will always fail since the two masks are not the same. So the CPU chosen is the first CPU in the intersection of cpu_online_map and CPU_MASK_ALL, which is always CPU0. That means all interrupts are reassigned to CPU0... Distributing interrupts to CPUs in a linearly increasing round robin fashion is not optimal for the UltraSPARC T1/T2. Also, the irq_rover in irq_choose_cpu() causes an interrupt to be assigned to a different processor each time the interrupt is allocated and released. This may lead to an unbalanced distribution over time. A static mapping of interrupts to processors is done to optimize and balance interrupt distribution. For the T1/T2, interrupts are spread to different cores first, and then to strands within a core. The following is some benchmarks showing the effects of interrupt distribution on a T2. The test was done with iperf using a pair of T5220 boxes, each with a 10GBe NIU (XAUI) connected back to back. TCP | Stock Linear RR IRQ Optimized IRQ Streams | 2.6.30-rc5 Distribution Distribution | GBits/sec GBits/sec GBits/sec --------+----------------------------------------- 1 0.839 0.862 0.868 8 1.16 4.96 5.88 16 1.15 6.40 8.04 100 1.09 7.28 8.68 Signed-off-by: Hong H. Pham <hong.pham@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-06-04 03:10:11 -06:00
/* Initialize all levels in the tree with the first CPU */
for (level = CPUINFO_LVL_PROC; level >= CPUINFO_LVL_ROOT; level--) {
n = new_tree->level[level].start_index;
level_rover[level] = n;
node = &new_tree->nodes[n];
id = cpuinfo_id(cpu, level);
if (unlikely(id < 0)) {
kfree(new_tree);
return NULL;
}
node->id = id;
node->level = level;
node->num_cpus = 1;
node->parent_index = (level > CPUINFO_LVL_ROOT)
? new_tree->level[level - 1].start_index : -1;
node->child_start = node->child_end = node->rover =
(level == CPUINFO_LVL_PROC)
? cpu : new_tree->level[level + 1].start_index;
prev_id[level] = node->id;
num_cpus[level] = 1;
}
for (last_cpu = (num_possible_cpus() - 1); last_cpu >= 0; last_cpu--) {
if (cpu_online(last_cpu))
break;
}
while (++cpu <= last_cpu) {
if (!cpu_online(cpu))
continue;
for (level = CPUINFO_LVL_PROC; level >= CPUINFO_LVL_ROOT;
level--) {
id = cpuinfo_id(cpu, level);
if (unlikely(id < 0)) {
kfree(new_tree);
return NULL;
}
if ((id != prev_id[level]) || (cpu == last_cpu)) {
prev_id[level] = id;
node = &new_tree->nodes[level_rover[level]];
node->num_cpus = num_cpus[level];
num_cpus[level] = 1;
if (cpu == last_cpu)
node->num_cpus++;
/* Connect tree node to parent */
if (level == CPUINFO_LVL_ROOT)
node->parent_index = -1;
else
node->parent_index =
level_rover[level - 1];
if (level == CPUINFO_LVL_PROC) {
node->child_end =
(cpu == last_cpu) ? cpu : prev_cpu;
} else {
node->child_end =
level_rover[level + 1] - 1;
}
/* Initialize the next node in the same level */
n = ++level_rover[level];
if (n <= new_tree->level[level].end_index) {
node = &new_tree->nodes[n];
node->id = id;
node->level = level;
/* Connect node to child */
node->child_start = node->child_end =
node->rover =
(level == CPUINFO_LVL_PROC)
? cpu : level_rover[level + 1];
}
} else
num_cpus[level]++;
}
prev_cpu = cpu;
}
return new_tree;
}
static void increment_rover(struct cpuinfo_tree *t, int node_index,
int root_index, const int *rover_inc_table)
{
struct cpuinfo_node *node = &t->nodes[node_index];
int top_level, level;
top_level = t->nodes[root_index].level;
for (level = node->level; level >= top_level; level--) {
node->rover++;
if (node->rover <= node->child_end)
return;
node->rover = node->child_start;
/* If parent's rover does not need to be adjusted, stop here. */
if ((level == top_level) ||
!(rover_inc_table[level] & ROVER_INC_PARENT_ON_LOOP))
return;
node = &t->nodes[node->parent_index];
}
}
static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
{
const int *rover_inc_table;
int level, new_index, index = root_index;
switch (sun4v_chip_type) {
case SUN4V_CHIP_NIAGARA1:
case SUN4V_CHIP_NIAGARA2:
case SUN4V_CHIP_NIAGARA3:
case SUN4V_CHIP_NIAGARA4:
case SUN4V_CHIP_NIAGARA5:
case SUN4V_CHIP_SPARC_M6:
case SUN4V_CHIP_SPARC_M7:
case SUN4V_CHIP_SPARC_M8:
case SUN4V_CHIP_SPARC_SN:
case SUN4V_CHIP_SPARC64X:
sparc64: fix and optimize irq distribution irq_choose_cpu() should compare the affinity mask against cpu_online_map rather than CPU_MASK_ALL, since irq_select_affinity() sets the interrupt's affinity mask to cpu_online_map "and" CPU_MASK_ALL (which ends up being just cpu_online_map). The mask comparison in irq_choose_cpu() will always fail since the two masks are not the same. So the CPU chosen is the first CPU in the intersection of cpu_online_map and CPU_MASK_ALL, which is always CPU0. That means all interrupts are reassigned to CPU0... Distributing interrupts to CPUs in a linearly increasing round robin fashion is not optimal for the UltraSPARC T1/T2. Also, the irq_rover in irq_choose_cpu() causes an interrupt to be assigned to a different processor each time the interrupt is allocated and released. This may lead to an unbalanced distribution over time. A static mapping of interrupts to processors is done to optimize and balance interrupt distribution. For the T1/T2, interrupts are spread to different cores first, and then to strands within a core. The following is some benchmarks showing the effects of interrupt distribution on a T2. The test was done with iperf using a pair of T5220 boxes, each with a 10GBe NIU (XAUI) connected back to back. TCP | Stock Linear RR IRQ Optimized IRQ Streams | 2.6.30-rc5 Distribution Distribution | GBits/sec GBits/sec GBits/sec --------+----------------------------------------- 1 0.839 0.862 0.868 8 1.16 4.96 5.88 16 1.15 6.40 8.04 100 1.09 7.28 8.68 Signed-off-by: Hong H. Pham <hong.pham@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-06-04 03:10:11 -06:00
rover_inc_table = niagara_iterate_method;
break;
default:
rover_inc_table = generic_iterate_method;
}
for (level = t->nodes[root_index].level; level < CPUINFO_LVL_MAX;
level++) {
new_index = t->nodes[index].rover;
if (rover_inc_table[level] & ROVER_INC_ON_VISIT)
increment_rover(t, index, root_index, rover_inc_table);
index = new_index;
}
return index;
}
static void _cpu_map_rebuild(void)
{
int i;
if (cpuinfo_tree) {
kfree(cpuinfo_tree);
cpuinfo_tree = NULL;
}
cpuinfo_tree = build_cpuinfo_tree();
if (!cpuinfo_tree)
return;
/* Build CPU distribution map that spans all online CPUs. No need
* to check if the CPU is online, as that is done when the cpuinfo
* tree is being built.
*/
for (i = 0; i < cpuinfo_tree->nodes[0].num_cpus; i++)
cpu_distribution_map[i] = iterate_cpu(cpuinfo_tree, 0);
}
/* Fallback if the cpuinfo tree could not be built. CPU mapping is linear
* round robin.
*/
static int simple_map_to_cpu(unsigned int index)
{
int i, end, cpu_rover;
cpu_rover = 0;
end = index % num_online_cpus();
for (i = 0; i < num_possible_cpus(); i++) {
if (cpu_online(cpu_rover)) {
if (cpu_rover >= end)
return cpu_rover;
cpu_rover++;
}
}
/* Impossible, since num_online_cpus() <= num_possible_cpus() */
return cpumask_first(cpu_online_mask);
sparc64: fix and optimize irq distribution irq_choose_cpu() should compare the affinity mask against cpu_online_map rather than CPU_MASK_ALL, since irq_select_affinity() sets the interrupt's affinity mask to cpu_online_map "and" CPU_MASK_ALL (which ends up being just cpu_online_map). The mask comparison in irq_choose_cpu() will always fail since the two masks are not the same. So the CPU chosen is the first CPU in the intersection of cpu_online_map and CPU_MASK_ALL, which is always CPU0. That means all interrupts are reassigned to CPU0... Distributing interrupts to CPUs in a linearly increasing round robin fashion is not optimal for the UltraSPARC T1/T2. Also, the irq_rover in irq_choose_cpu() causes an interrupt to be assigned to a different processor each time the interrupt is allocated and released. This may lead to an unbalanced distribution over time. A static mapping of interrupts to processors is done to optimize and balance interrupt distribution. For the T1/T2, interrupts are spread to different cores first, and then to strands within a core. The following is some benchmarks showing the effects of interrupt distribution on a T2. The test was done with iperf using a pair of T5220 boxes, each with a 10GBe NIU (XAUI) connected back to back. TCP | Stock Linear RR IRQ Optimized IRQ Streams | 2.6.30-rc5 Distribution Distribution | GBits/sec GBits/sec GBits/sec --------+----------------------------------------- 1 0.839 0.862 0.868 8 1.16 4.96 5.88 16 1.15 6.40 8.04 100 1.09 7.28 8.68 Signed-off-by: Hong H. Pham <hong.pham@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2009-06-04 03:10:11 -06:00
}
static int _map_to_cpu(unsigned int index)
{
struct cpuinfo_node *root_node;
if (unlikely(!cpuinfo_tree)) {
_cpu_map_rebuild();
if (!cpuinfo_tree)
return simple_map_to_cpu(index);
}
root_node = &cpuinfo_tree->nodes[0];
#ifdef CONFIG_HOTPLUG_CPU
if (unlikely(root_node->num_cpus != num_online_cpus())) {
_cpu_map_rebuild();
if (!cpuinfo_tree)
return simple_map_to_cpu(index);
}
#endif
return cpu_distribution_map[index % root_node->num_cpus];
}
int map_to_cpu(unsigned int index)
{
int mapped_cpu;
unsigned long flag;
spin_lock_irqsave(&cpu_map_lock, flag);
mapped_cpu = _map_to_cpu(index);
#ifdef CONFIG_HOTPLUG_CPU
while (unlikely(!cpu_online(mapped_cpu)))
mapped_cpu = _map_to_cpu(index);
#endif
spin_unlock_irqrestore(&cpu_map_lock, flag);
return mapped_cpu;
}
EXPORT_SYMBOL(map_to_cpu);
void cpu_map_rebuild(void)
{
unsigned long flag;
spin_lock_irqsave(&cpu_map_lock, flag);
_cpu_map_rebuild();
spin_unlock_irqrestore(&cpu_map_lock, flag);
}