2012-08-03 09:26:11 -06:00
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/*
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* Freescale MXS SPI master driver
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*
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* Copyright 2012 DENX Software Engineering, GmbH.
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* Rework and transition to new API by:
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* Marek Vasut <marex@denx.de>
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*
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* Based on previous attempt by:
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* Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Based on code from U-Boot bootloader by:
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* Marek Vasut <marex@denx.de>
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*
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* Based on spi-stmp.c, which is:
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* Author: Dmitry Pervushin <dimka@embeddedalley.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/highmem.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/completion.h>
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#include <linux/gpio.h>
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#include <linux/regulator/consumer.h>
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#include <linux/module.h>
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#include <linux/stmp_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/mxs-spi.h>
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#define DRIVER_NAME "mxs-spi"
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mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
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/* Use 10S timeout for very long transfers, it should suffice. */
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#define SSP_TIMEOUT 10000
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2012-08-03 09:26:11 -06:00
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2012-08-03 09:26:13 -06:00
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#define SG_MAXLEN 0xff00
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2013-10-01 14:14:50 -06:00
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/*
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* Flags for txrx functions. More efficient that using an argument register for
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* each one.
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*/
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#define TXRX_WRITE (1<<0) /* This is a write */
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#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
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2012-08-03 09:26:11 -06:00
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struct mxs_spi {
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struct mxs_ssp ssp;
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2012-08-03 09:26:13 -06:00
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struct completion c;
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2013-10-01 14:15:47 -06:00
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unsigned int sck; /* Rate requested (vs actual) */
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2012-08-03 09:26:11 -06:00
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};
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static int mxs_spi_setup_transfer(struct spi_device *dev,
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2013-10-01 14:15:40 -06:00
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const struct spi_transfer *t)
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2012-08-03 09:26:11 -06:00
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{
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struct mxs_spi *spi = spi_master_get_devdata(dev->master);
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struct mxs_ssp *ssp = &spi->ssp;
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2013-10-01 14:15:40 -06:00
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const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
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2012-08-03 09:26:11 -06:00
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if (hz == 0) {
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2013-10-01 14:15:40 -06:00
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dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
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2012-08-03 09:26:11 -06:00
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return -EINVAL;
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}
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2013-10-01 14:15:47 -06:00
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if (hz != spi->sck) {
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mxs_ssp_set_clk_rate(ssp, hz);
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/*
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* Save requested rate, hz, rather than the actual rate,
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* ssp->clk_rate. Otherwise we would set the rate every trasfer
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* when the actual rate is not quite the same as requested rate.
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*/
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spi->sck = hz;
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/*
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* Perhaps we should return an error if the actual clock is
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* nowhere close to what was requested?
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*/
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}
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2012-08-03 09:26:11 -06:00
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2013-10-01 14:14:25 -06:00
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writel(BM_SSP_CTRL0_LOCK_CS,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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2012-08-03 09:26:11 -06:00
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writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
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2013-10-01 14:15:40 -06:00
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BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
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((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
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((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
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ssp->base + HW_SSP_CTRL1(ssp));
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2012-08-03 09:26:11 -06:00
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writel(0x0, ssp->base + HW_SSP_CMD0);
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writel(0x0, ssp->base + HW_SSP_CMD1);
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return 0;
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}
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static int mxs_spi_setup(struct spi_device *dev)
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{
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if (!dev->bits_per_word)
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dev->bits_per_word = 8;
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2013-10-01 14:15:25 -06:00
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return 0;
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2012-08-03 09:26:11 -06:00
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}
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2013-10-01 14:15:54 -06:00
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static u32 mxs_spi_cs_to_reg(unsigned cs)
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2012-08-03 09:26:11 -06:00
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{
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2013-10-01 14:15:54 -06:00
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u32 select = 0;
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2012-08-03 09:26:11 -06:00
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/*
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* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
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*
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* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
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* in HW_SSP_CTRL0 register do have multiple usage, please refer to
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* the datasheet for further details. In SPI mode, they are used to
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* toggle the chip-select lines (nCS pins).
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*/
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if (cs & 1)
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select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
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if (cs & 2)
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select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
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return select;
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}
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static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
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{
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2012-09-03 20:40:18 -06:00
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const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
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2012-08-03 09:26:11 -06:00
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struct mxs_ssp *ssp = &spi->ssp;
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2013-10-01 14:15:54 -06:00
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u32 reg;
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2012-08-03 09:26:11 -06:00
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2012-09-03 20:40:18 -06:00
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do {
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2012-08-03 09:26:11 -06:00
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reg = readl_relaxed(ssp->base + offset);
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2012-09-03 20:40:18 -06:00
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if (!set)
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reg = ~reg;
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2012-08-03 09:26:11 -06:00
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2012-09-03 20:40:18 -06:00
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reg &= mask;
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2012-08-03 09:26:11 -06:00
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2012-09-03 20:40:18 -06:00
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if (reg == mask)
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return 0;
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} while (time_before(jiffies, timeout));
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2012-08-03 09:26:11 -06:00
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2012-09-03 20:40:18 -06:00
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return -ETIMEDOUT;
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2012-08-03 09:26:11 -06:00
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}
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2012-08-03 09:26:13 -06:00
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static void mxs_ssp_dma_irq_callback(void *param)
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{
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struct mxs_spi *spi = param;
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complete(&spi->c);
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}
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static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
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{
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struct mxs_ssp *ssp = dev_id;
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dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
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__func__, __LINE__,
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readl(ssp->base + HW_SSP_CTRL1(ssp)),
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readl(ssp->base + HW_SSP_STATUS(ssp)));
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return IRQ_HANDLED;
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}
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2013-10-01 14:15:04 -06:00
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static int mxs_spi_txrx_dma(struct mxs_spi *spi,
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2012-08-03 09:26:13 -06:00
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unsigned char *buf, int len,
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2013-10-01 14:14:50 -06:00
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unsigned int flags)
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2012-08-03 09:26:13 -06:00
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{
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struct mxs_ssp *ssp = &spi->ssp;
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mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
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struct dma_async_tx_descriptor *desc = NULL;
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const bool vmalloced_buf = is_vmalloc_addr(buf);
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const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
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const int sgs = DIV_ROUND_UP(len, desc_len);
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2012-08-03 09:26:13 -06:00
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int sg_count;
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mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
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int min, ret;
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2013-10-01 14:15:54 -06:00
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u32 ctrl0;
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mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
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struct page *vm_page;
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void *sg_buf;
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struct {
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2013-10-01 14:15:54 -06:00
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u32 pio[4];
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mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
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struct scatterlist sg;
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} *dma_xfer;
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if (!len)
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2012-08-03 09:26:13 -06:00
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return -EINVAL;
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
|
|
|
|
dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
|
|
|
|
if (!dma_xfer)
|
|
|
|
return -ENOMEM;
|
2012-08-03 09:26:13 -06:00
|
|
|
|
2013-11-14 15:32:02 -07:00
|
|
|
reinit_completion(&spi->c);
|
2012-08-03 09:26:13 -06:00
|
|
|
|
2013-10-01 14:15:04 -06:00
|
|
|
/* Chip select was already programmed into CTRL0 */
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
|
2013-10-01 14:14:57 -06:00
|
|
|
ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
|
|
|
|
BM_SSP_CTRL0_READ);
|
2013-10-01 14:15:04 -06:00
|
|
|
ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
|
2013-10-01 14:14:50 -06:00
|
|
|
if (!(flags & TXRX_WRITE))
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
ctrl0 |= BM_SSP_CTRL0_READ;
|
2012-08-03 09:26:13 -06:00
|
|
|
|
|
|
|
/* Queue the DMA data transfer. */
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
for (sg_count = 0; sg_count < sgs; sg_count++) {
|
2013-10-01 14:14:50 -06:00
|
|
|
/* Prepare the transfer descriptor. */
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
min = min(len, desc_len);
|
|
|
|
|
2013-10-01 14:14:50 -06:00
|
|
|
/*
|
|
|
|
* De-assert CS on last segment if flag is set (i.e., no more
|
|
|
|
* transfers will follow)
|
|
|
|
*/
|
|
|
|
if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
|
|
|
|
|
2012-12-25 22:48:51 -07:00
|
|
|
if (ssp->devid == IMX23_SSP) {
|
|
|
|
ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
ctrl0 |= min;
|
2012-12-25 22:48:51 -07:00
|
|
|
}
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
|
|
|
|
dma_xfer[sg_count].pio[0] = ctrl0;
|
|
|
|
dma_xfer[sg_count].pio[3] = min;
|
|
|
|
|
|
|
|
if (vmalloced_buf) {
|
|
|
|
vm_page = vmalloc_to_page(buf);
|
|
|
|
if (!vm_page) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_vmalloc;
|
|
|
|
}
|
|
|
|
sg_buf = page_address(vm_page) +
|
|
|
|
((size_t)buf & ~PAGE_MASK);
|
|
|
|
} else {
|
|
|
|
sg_buf = buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
|
|
|
|
ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
|
2013-10-01 14:14:50 -06:00
|
|
|
(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
|
|
|
|
len -= min;
|
|
|
|
buf += min;
|
|
|
|
|
|
|
|
/* Queue the PIO register write transfer. */
|
|
|
|
desc = dmaengine_prep_slave_sg(ssp->dmach,
|
|
|
|
(struct scatterlist *)dma_xfer[sg_count].pio,
|
|
|
|
(ssp->devid == IMX23_SSP) ? 1 : 4,
|
|
|
|
DMA_TRANS_NONE,
|
|
|
|
sg_count ? DMA_PREP_INTERRUPT : 0);
|
|
|
|
if (!desc) {
|
|
|
|
dev_err(ssp->dev,
|
|
|
|
"Failed to get PIO reg. write descriptor.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_mapped;
|
|
|
|
}
|
|
|
|
|
|
|
|
desc = dmaengine_prep_slave_sg(ssp->dmach,
|
|
|
|
&dma_xfer[sg_count].sg, 1,
|
2013-10-01 14:14:50 -06:00
|
|
|
(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
|
|
|
|
if (!desc) {
|
|
|
|
dev_err(ssp->dev,
|
|
|
|
"Failed to get DMA data write descriptor.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_mapped;
|
|
|
|
}
|
2012-08-03 09:26:13 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The last descriptor must have this callback,
|
|
|
|
* to finish the DMA transaction.
|
|
|
|
*/
|
|
|
|
desc->callback = mxs_ssp_dma_irq_callback;
|
|
|
|
desc->callback_param = spi;
|
|
|
|
|
|
|
|
/* Start the transfer. */
|
|
|
|
dmaengine_submit(desc);
|
|
|
|
dma_async_issue_pending(ssp->dmach);
|
|
|
|
|
|
|
|
ret = wait_for_completion_timeout(&spi->c,
|
|
|
|
msecs_to_jiffies(SSP_TIMEOUT));
|
|
|
|
if (!ret) {
|
|
|
|
dev_err(ssp->dev, "DMA transfer timeout\n");
|
|
|
|
ret = -ETIMEDOUT;
|
2012-10-13 20:32:56 -06:00
|
|
|
dmaengine_terminate_all(ssp->dmach);
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
goto err_vmalloc;
|
2012-08-03 09:26:13 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = 0;
|
|
|
|
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
err_vmalloc:
|
|
|
|
while (--sg_count >= 0) {
|
|
|
|
err_mapped:
|
|
|
|
dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
|
2013-10-01 14:14:50 -06:00
|
|
|
(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
|
2012-08-03 09:26:13 -06:00
|
|
|
}
|
|
|
|
|
mxs/spi: Fix issues when doing long continuous transfer
When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-03 20:40:15 -06:00
|
|
|
kfree(dma_xfer);
|
|
|
|
|
2012-08-03 09:26:13 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-10-01 14:15:04 -06:00
|
|
|
static int mxs_spi_txrx_pio(struct mxs_spi *spi,
|
2012-08-03 09:26:11 -06:00
|
|
|
unsigned char *buf, int len,
|
2013-10-01 14:14:50 -06:00
|
|
|
unsigned int flags)
|
2012-08-03 09:26:11 -06:00
|
|
|
{
|
|
|
|
struct mxs_ssp *ssp = &spi->ssp;
|
|
|
|
|
2013-10-01 14:14:39 -06:00
|
|
|
writel(BM_SSP_CTRL0_IGNORE_CRC,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
2012-08-03 09:26:11 -06:00
|
|
|
|
|
|
|
while (len--) {
|
2013-10-01 14:14:50 -06:00
|
|
|
if (len == 0 && (flags & TXRX_DEASSERT_CS))
|
2013-10-01 14:14:32 -06:00
|
|
|
writel(BM_SSP_CTRL0_IGNORE_CRC,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
2012-08-03 09:26:11 -06:00
|
|
|
|
|
|
|
if (ssp->devid == IMX23_SSP) {
|
|
|
|
writel(BM_SSP_CTRL0_XFER_COUNT,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
|
|
|
writel(1,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
|
|
|
} else {
|
|
|
|
writel(1, ssp->base + HW_SSP_XFER_SIZE);
|
|
|
|
}
|
|
|
|
|
2013-10-01 14:14:50 -06:00
|
|
|
if (flags & TXRX_WRITE)
|
2012-08-03 09:26:11 -06:00
|
|
|
writel(BM_SSP_CTRL0_READ,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
|
|
|
else
|
|
|
|
writel(BM_SSP_CTRL0_READ,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
|
|
|
|
|
|
|
writel(BM_SSP_CTRL0_RUN,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
|
|
|
|
|
|
|
if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
2013-10-01 14:14:50 -06:00
|
|
|
if (flags & TXRX_WRITE)
|
2012-08-03 09:26:11 -06:00
|
|
|
writel(*buf, ssp->base + HW_SSP_DATA(ssp));
|
|
|
|
|
|
|
|
writel(BM_SSP_CTRL0_DATA_XFER,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
|
|
|
|
2013-10-01 14:14:50 -06:00
|
|
|
if (!(flags & TXRX_WRITE)) {
|
2012-08-03 09:26:11 -06:00
|
|
|
if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
|
|
|
|
BM_SSP_STATUS_FIFO_EMPTY, 0))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
buf++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (len <= 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxs_spi_transfer_one(struct spi_master *master,
|
|
|
|
struct spi_message *m)
|
|
|
|
{
|
|
|
|
struct mxs_spi *spi = spi_master_get_devdata(master);
|
|
|
|
struct mxs_ssp *ssp = &spi->ssp;
|
|
|
|
struct spi_transfer *t, *tmp_t;
|
2013-10-01 14:14:50 -06:00
|
|
|
unsigned int flag;
|
2012-08-03 09:26:11 -06:00
|
|
|
int status = 0;
|
|
|
|
|
2013-10-01 14:15:04 -06:00
|
|
|
/* Program CS register bits here, it will be used for all transfers. */
|
|
|
|
writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
|
|
|
|
writel(mxs_spi_cs_to_reg(m->spi->chip_select),
|
|
|
|
ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
|
2012-08-03 09:26:11 -06:00
|
|
|
|
|
|
|
list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
|
|
|
|
|
|
|
|
status = mxs_spi_setup_transfer(m->spi, t);
|
|
|
|
if (status)
|
|
|
|
break;
|
|
|
|
|
2013-10-01 14:14:50 -06:00
|
|
|
/* De-assert on last transfer, inverted by cs_change flag */
|
|
|
|
flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
|
|
|
|
TXRX_DEASSERT_CS : 0;
|
2012-08-03 09:26:11 -06:00
|
|
|
|
2012-08-03 09:26:13 -06:00
|
|
|
/*
|
|
|
|
* Small blocks can be transfered via PIO.
|
|
|
|
* Measured by empiric means:
|
|
|
|
*
|
|
|
|
* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
|
|
|
|
*
|
|
|
|
* DMA only: 2.164808 seconds, 473.0KB/s
|
|
|
|
* Combined: 1.676276 seconds, 610.9KB/s
|
|
|
|
*/
|
2012-09-03 20:40:17 -06:00
|
|
|
if (t->len < 32) {
|
2012-08-03 09:26:13 -06:00
|
|
|
writel(BM_SSP_CTRL1_DMA_ENABLE,
|
|
|
|
ssp->base + HW_SSP_CTRL1(ssp) +
|
|
|
|
STMP_OFFSET_REG_CLR);
|
|
|
|
|
|
|
|
if (t->tx_buf)
|
2013-10-01 14:15:04 -06:00
|
|
|
status = mxs_spi_txrx_pio(spi,
|
2012-08-03 09:26:13 -06:00
|
|
|
(void *)t->tx_buf,
|
2013-10-01 14:14:50 -06:00
|
|
|
t->len, flag | TXRX_WRITE);
|
2012-08-03 09:26:13 -06:00
|
|
|
if (t->rx_buf)
|
2013-10-01 14:15:04 -06:00
|
|
|
status = mxs_spi_txrx_pio(spi,
|
2012-08-03 09:26:13 -06:00
|
|
|
t->rx_buf, t->len,
|
2013-10-01 14:14:50 -06:00
|
|
|
flag);
|
2012-08-03 09:26:13 -06:00
|
|
|
} else {
|
|
|
|
writel(BM_SSP_CTRL1_DMA_ENABLE,
|
|
|
|
ssp->base + HW_SSP_CTRL1(ssp) +
|
|
|
|
STMP_OFFSET_REG_SET);
|
|
|
|
|
|
|
|
if (t->tx_buf)
|
2013-10-01 14:15:04 -06:00
|
|
|
status = mxs_spi_txrx_dma(spi,
|
2012-08-03 09:26:13 -06:00
|
|
|
(void *)t->tx_buf, t->len,
|
2013-10-01 14:14:50 -06:00
|
|
|
flag | TXRX_WRITE);
|
2012-08-03 09:26:13 -06:00
|
|
|
if (t->rx_buf)
|
2013-10-01 14:15:04 -06:00
|
|
|
status = mxs_spi_txrx_dma(spi,
|
2012-08-03 09:26:13 -06:00
|
|
|
t->rx_buf, t->len,
|
2013-10-01 14:14:50 -06:00
|
|
|
flag);
|
2012-08-03 09:26:13 -06:00
|
|
|
}
|
2012-08-03 09:26:11 -06:00
|
|
|
|
2012-08-23 20:34:18 -06:00
|
|
|
if (status) {
|
|
|
|
stmp_reset_block(ssp->base);
|
2012-08-03 09:26:11 -06:00
|
|
|
break;
|
2012-08-23 20:34:18 -06:00
|
|
|
}
|
2012-08-03 09:26:11 -06:00
|
|
|
|
2012-09-03 20:40:16 -06:00
|
|
|
m->actual_length += t->len;
|
2012-08-03 09:26:11 -06:00
|
|
|
}
|
|
|
|
|
2012-10-13 20:32:55 -06:00
|
|
|
m->status = status;
|
2012-08-03 09:26:11 -06:00
|
|
|
spi_finalize_current_message(master);
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id mxs_spi_dt_ids[] = {
|
|
|
|
{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
|
|
|
|
{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
static int mxs_spi_probe(struct platform_device *pdev)
|
2012-08-03 09:26:11 -06:00
|
|
|
{
|
|
|
|
const struct of_device_id *of_id =
|
|
|
|
of_match_device(mxs_spi_dt_ids, &pdev->dev);
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct spi_master *master;
|
|
|
|
struct mxs_spi *spi;
|
|
|
|
struct mxs_ssp *ssp;
|
2013-02-25 20:07:32 -07:00
|
|
|
struct resource *iores;
|
2012-08-03 09:26:11 -06:00
|
|
|
struct clk *clk;
|
|
|
|
void __iomem *base;
|
2013-02-25 20:07:32 -07:00
|
|
|
int devid, clk_freq;
|
|
|
|
int ret = 0, irq_err;
|
2012-08-03 09:26:11 -06:00
|
|
|
|
2012-08-22 14:38:35 -06:00
|
|
|
/*
|
|
|
|
* Default clock speed for the SPI core. 160MHz seems to
|
|
|
|
* work reasonably well with most SPI flashes, so use this
|
|
|
|
* as a default. Override with "clock-frequency" DT prop.
|
|
|
|
*/
|
|
|
|
const int clk_freq_default = 160000000;
|
|
|
|
|
2012-08-03 09:26:11 -06:00
|
|
|
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2012-08-03 09:26:13 -06:00
|
|
|
irq_err = platform_get_irq(pdev, 0);
|
2013-07-21 19:29:54 -06:00
|
|
|
if (irq_err < 0)
|
2012-08-03 09:26:11 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
2013-01-21 03:09:18 -07:00
|
|
|
base = devm_ioremap_resource(&pdev->dev, iores);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
2012-08-03 09:26:11 -06:00
|
|
|
|
|
|
|
clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(clk))
|
|
|
|
return PTR_ERR(clk);
|
|
|
|
|
2013-02-25 20:07:32 -07:00
|
|
|
devid = (enum mxs_ssp_id) of_id->data;
|
|
|
|
ret = of_property_read_u32(np, "clock-frequency",
|
|
|
|
&clk_freq);
|
|
|
|
if (ret)
|
2012-08-22 14:38:35 -06:00
|
|
|
clk_freq = clk_freq_default;
|
2012-08-03 09:26:11 -06:00
|
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*spi));
|
|
|
|
if (!master)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
master->transfer_one_message = mxs_spi_transfer_one;
|
|
|
|
master->setup = mxs_spi_setup;
|
2013-05-21 20:36:35 -06:00
|
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
2012-08-03 09:26:11 -06:00
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
|
|
|
master->num_chipselect = 3;
|
|
|
|
master->dev.of_node = np;
|
|
|
|
master->flags = SPI_MASTER_HALF_DUPLEX;
|
|
|
|
|
|
|
|
spi = spi_master_get_devdata(master);
|
|
|
|
ssp = &spi->ssp;
|
|
|
|
ssp->dev = &pdev->dev;
|
|
|
|
ssp->clk = clk;
|
|
|
|
ssp->base = base;
|
|
|
|
ssp->devid = devid;
|
2012-08-03 09:26:13 -06:00
|
|
|
|
2012-08-23 20:56:27 -06:00
|
|
|
init_completion(&spi->c);
|
|
|
|
|
2012-08-03 09:26:13 -06:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
|
|
|
|
DRIVER_NAME, ssp);
|
|
|
|
if (ret)
|
|
|
|
goto out_master_free;
|
|
|
|
|
2013-02-25 20:07:32 -07:00
|
|
|
ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
|
2012-08-03 09:26:13 -06:00
|
|
|
if (!ssp->dmach) {
|
|
|
|
dev_err(ssp->dev, "Failed to request DMA\n");
|
2013-04-03 07:06:40 -06:00
|
|
|
ret = -ENODEV;
|
2012-08-03 09:26:13 -06:00
|
|
|
goto out_master_free;
|
|
|
|
}
|
2012-08-03 09:26:11 -06:00
|
|
|
|
2013-07-09 21:16:28 -06:00
|
|
|
ret = clk_prepare_enable(ssp->clk);
|
|
|
|
if (ret)
|
|
|
|
goto out_dma_release;
|
|
|
|
|
2012-08-22 14:38:35 -06:00
|
|
|
clk_set_rate(ssp->clk, clk_freq);
|
2012-08-03 09:26:11 -06:00
|
|
|
|
2013-07-09 21:16:29 -06:00
|
|
|
ret = stmp_reset_block(ssp->base);
|
|
|
|
if (ret)
|
|
|
|
goto out_disable_clk;
|
2012-08-03 09:26:11 -06:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
|
2013-09-23 22:32:56 -06:00
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
2012-08-03 09:26:11 -06:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
|
2013-07-09 21:16:28 -06:00
|
|
|
goto out_disable_clk;
|
2012-08-03 09:26:11 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2013-07-09 21:16:28 -06:00
|
|
|
out_disable_clk:
|
2012-08-03 09:26:11 -06:00
|
|
|
clk_disable_unprepare(ssp->clk);
|
2013-07-09 21:16:28 -06:00
|
|
|
out_dma_release:
|
2013-07-09 21:16:27 -06:00
|
|
|
dma_release_channel(ssp->dmach);
|
2012-08-03 09:26:13 -06:00
|
|
|
out_master_free:
|
2012-08-03 09:26:11 -06:00
|
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
static int mxs_spi_remove(struct platform_device *pdev)
|
2012-08-03 09:26:11 -06:00
|
|
|
{
|
|
|
|
struct spi_master *master;
|
|
|
|
struct mxs_spi *spi;
|
|
|
|
struct mxs_ssp *ssp;
|
|
|
|
|
2013-11-15 00:50:31 -07:00
|
|
|
master = platform_get_drvdata(pdev);
|
2012-08-03 09:26:11 -06:00
|
|
|
spi = spi_master_get_devdata(master);
|
|
|
|
ssp = &spi->ssp;
|
|
|
|
|
|
|
|
clk_disable_unprepare(ssp->clk);
|
2013-07-09 21:16:27 -06:00
|
|
|
dma_release_channel(ssp->dmach);
|
2012-08-03 09:26:11 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver mxs_spi_driver = {
|
|
|
|
.probe = mxs_spi_probe,
|
2012-12-07 09:57:14 -07:00
|
|
|
.remove = mxs_spi_remove,
|
2012-08-03 09:26:11 -06:00
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = mxs_spi_dt_ids,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(mxs_spi_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
|
|
|
|
MODULE_DESCRIPTION("MXS SPI master driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("platform:mxs-spi");
|