xtensa: s6000 variant
Support for the Stretch S6000 Xtensa core variant. Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>hifive-unleashed-5.1
Johannes Weiner
Chris Zankel
parent
eff35af9c0
commit
000af2c5a8
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@ -32,6 +32,9 @@ config GENERIC_HWEIGHT
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config GENERIC_HARDIRQS
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def_bool y
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config GENERIC_GPIO
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def_bool y
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config ARCH_HAS_ILOG2_U32
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def_bool n
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@ -69,6 +72,11 @@ config XTENSA_VARIANT_DC232B
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select MMU
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help
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This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
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config XTENSA_VARIANT_S6000
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bool "s6000 - Stretch software configurable processor"
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select VARIANT_IRQ_SWITCH
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select ARCH_REQUIRE_GPIOLIB
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endchoice
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config XTENSA_UNALIGNED_USER
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@ -15,6 +15,7 @@
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variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
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variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b
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variant-$(CONFIG_XTENSA_VARIANT_S6000) := s6000
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variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
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VARIANT = $(variant-y)
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@ -0,0 +1,56 @@
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/*
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* Generic GPIO API implementation for xtensa.
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*
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* Stolen from x86, which is derived from the generic GPIO API for powerpc:
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*
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* Copyright (c) 2007-2008 MontaVista Software, Inc.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _ASM_XTENSA_GPIO_H
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#define _ASM_XTENSA_GPIO_H
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#include <asm-generic/gpio.h>
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#ifdef CONFIG_GPIOLIB
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/*
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* Just call gpiolib.
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*/
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static inline int gpio_get_value(unsigned int gpio)
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{
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return __gpio_get_value(gpio);
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}
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static inline void gpio_set_value(unsigned int gpio, int value)
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{
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__gpio_set_value(gpio, value);
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}
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static inline int gpio_cansleep(unsigned int gpio)
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{
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return __gpio_cansleep(gpio);
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}
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/*
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* Not implemented, yet.
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*/
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static inline int gpio_to_irq(unsigned int gpio)
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{
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return -ENOSYS;
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}
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static inline int irq_to_gpio(unsigned int irq)
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{
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return -EINVAL;
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}
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#endif /* CONFIG_GPIOLIB */
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#endif /* _ASM_XTENSA_GPIO_H */
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@ -0,0 +1,3 @@
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# s6000 Makefile
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obj-y += irq.o gpio.o
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@ -0,0 +1,71 @@
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/*
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* s6000 gpio driver
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*
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* Copyright (c) 2009 emlix GmbH
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* Authors: Oskar Schirmer <os@emlix.com>
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* Johannes Weiner <jw@emlix.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <variant/hardware.h>
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#define S6_GPIO_DATA 0x000
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#define S6_GPIO_IS 0x404
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#define S6_GPIO_IBE 0x408
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#define S6_GPIO_IEV 0x40C
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#define S6_GPIO_IE 0x410
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#define S6_GPIO_RIS 0x414
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#define S6_GPIO_MIS 0x418
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#define S6_GPIO_IC 0x41C
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#define S6_GPIO_AFSEL 0x420
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#define S6_GPIO_DIR 0x800
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#define S6_GPIO_BANK(nr) ((nr) * 0x1000)
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#define S6_GPIO_MASK(nr) (4 << (nr))
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#define S6_GPIO_OFFSET(nr) \
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(S6_GPIO_BANK((nr) >> 3) + S6_GPIO_MASK((nr) & 7))
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static int direction_input(struct gpio_chip *chip, unsigned int off)
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{
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writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off));
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return 0;
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}
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static int get(struct gpio_chip *chip, unsigned int off)
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{
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return readb(S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
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}
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static int direction_output(struct gpio_chip *chip, unsigned int off, int val)
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{
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unsigned rel = S6_GPIO_OFFSET(off);
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writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel);
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writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel);
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return 0;
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}
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static void set(struct gpio_chip *chip, unsigned int off, int val)
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{
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writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
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}
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static struct gpio_chip gpiochip = {
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.owner = THIS_MODULE,
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.direction_input = direction_input,
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.get = get,
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.direction_output = direction_output,
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.set = set,
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.base = 0,
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.ngpio = 24,
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.can_sleep = 0, /* no blocking io needed */
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.exported = 0, /* no exporting to userspace */
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};
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static int gpio_init(void)
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{
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return gpiochip_add(&gpiochip);
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}
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device_initcall(gpio_init);
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@ -0,0 +1,259 @@
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#ifndef __XTENSA_S6000_HARDWARE_H
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#define __XTENSA_S6000_HARDWARE_H
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#define S6_SCLK 1843200
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#define S6_MEM_REG 0x20000000
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#define S6_MEM_EFI 0x33F00000
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#define S6_MEM_PCIE_DATARAM1 0x34000000
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#define S6_MEM_XLMI 0x37F80000
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#define S6_MEM_PIF_DATARAM1 0x37FFC000
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#define S6_MEM_GMAC 0x38000000
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#define S6_MEM_I2S 0x3A000000
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#define S6_MEM_EGIB 0x3C000000
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#define S6_MEM_PCIE_CFG 0x3E000000
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#define S6_MEM_PIF_DATARAM 0x3FFE0000
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#define S6_MEM_XLMI_DATARAM 0x3FFF0000
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#define S6_MEM_DDR 0x40000000
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#define S6_MEM_PCIE_APER 0xC0000000
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#define S6_MEM_AUX 0xF0000000
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/* Device addresses */
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#define S6_REG_SCB S6_MEM_REG
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#define S6_REG_NB (S6_REG_SCB + 0x10000)
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#define S6_REG_LMSDMA (S6_REG_SCB + 0x20000)
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#define S6_REG_NI (S6_REG_SCB + 0x30000)
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#define S6_REG_NIDMA (S6_REG_SCB + 0x40000)
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#define S6_REG_NS (S6_REG_SCB + 0x50000)
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#define S6_REG_DDR (S6_REG_SCB + 0x60000)
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#define S6_REG_GREG1 (S6_REG_SCB + 0x70000)
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#define S6_REG_DP (S6_REG_SCB + 0x80000)
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#define S6_REG_DPDMA (S6_REG_SCB + 0x90000)
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#define S6_REG_EGIB (S6_REG_SCB + 0xA0000)
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#define S6_REG_PCIE (S6_REG_SCB + 0xB0000)
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#define S6_REG_I2S (S6_REG_SCB + 0xC0000)
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#define S6_REG_GMAC (S6_REG_SCB + 0xD0000)
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#define S6_REG_HIFDMA (S6_REG_SCB + 0xE0000)
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#define S6_REG_GREG2 (S6_REG_SCB + 0xF0000)
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#define S6_REG_APB S6_REG_SCB
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#define S6_REG_UART (S6_REG_APB + 0x0000)
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#define S6_REG_INTC (S6_REG_APB + 0x2000)
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#define S6_REG_SPI (S6_REG_APB + 0x3000)
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#define S6_REG_I2C (S6_REG_APB + 0x4000)
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#define S6_REG_GPIO (S6_REG_APB + 0x8000)
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/* Global register block */
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#define S6_GREG1_PLL_LOCKCLEAR 0x000
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#define S6_GREG1_PLL_LOCK_SYS 0
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#define S6_GREG1_PLL_LOCK_IO 1
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#define S6_GREG1_PLL_LOCK_AIM 2
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#define S6_GREG1_PLL_LOCK_DP0 3
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#define S6_GREG1_PLL_LOCK_DP2 4
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#define S6_GREG1_PLL_LOCK_DDR 5
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#define S6_GREG1_PLL_LOCKSTAT 0x004
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#define S6_GREG1_PLL_LOCKSTAT_CURLOCK 0
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#define S6_GREG1_PLL_LOCKSTAT_EVERUNLCK 8
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#define S6_GREG1_PLLSEL 0x010
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#define S6_GREG1_PLLSEL_AIM 0
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#define S6_GREG1_PLLSEL_AIM_DDR2 0
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#define S6_GREG1_PLLSEL_AIM_300MHZ 1
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#define S6_GREG1_PLLSEL_AIM_240MHZ 2
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#define S6_GREG1_PLLSEL_AIM_200MHZ 3
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#define S6_GREG1_PLLSEL_AIM_150MHZ 4
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#define S6_GREG1_PLLSEL_AIM_120MHZ 5
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#define S6_GREG1_PLLSEL_AIM_40MHZ 6
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#define S6_GREG1_PLLSEL_AIM_PLLAIMREF 7
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#define S6_GREG1_PLLSEL_AIM_MASK 7
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#define S6_GREG1_PLLSEL_DDR 8
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#define S6_GREG1_PLLSEL_DDR_HS 0
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#define S6_GREG1_PLLSEL_DDR_333MHZ 1
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#define S6_GREG1_PLLSEL_DDR_250MHZ 2
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#define S6_GREG1_PLLSEL_DDR_200MHZ 3
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#define S6_GREG1_PLLSEL_DDR_167MHZ 4
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#define S6_GREG1_PLLSEL_DDR_100MHZ 5
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#define S6_GREG1_PLLSEL_DDR_33MHZ 6
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#define S6_GREG1_PLLSEL_DDR_PLLIOREF 7
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#define S6_GREG1_PLLSEL_DDR_MASK 7
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#define S6_GREG1_PLLSEL_GMAC 16
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#define S6_GREG1_PLLSEL_GMAC_125MHZ 0
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#define S6_GREG1_PLLSEL_GMAC_25MHZ 1
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#define S6_GREG1_PLLSEL_GMAC_2500KHZ 2
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#define S6_GREG1_PLLSEL_GMAC_EXTERN 3
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#define S6_GREG1_PLLSEL_GMAC_MASK 3
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#define S6_GREG1_PLLSEL_GMII 18
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#define S6_GREG1_PLLSEL_GMII_111MHZ 0
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#define S6_GREG1_PLLSEL_GMII_IOREF 1
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#define S6_GREG1_PLLSEL_GMII_NONE 2
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#define S6_GREG1_PLLSEL_GMII_125MHZ 3
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#define S6_GREG1_PLLSEL_GMII_MASK 3
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#define S6_GREG1_SYSUNLOCKCNT 0x020
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#define S6_GREG1_IOUNLOCKCNT 0x024
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#define S6_GREG1_AIMUNLOCKCNT 0x028
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#define S6_GREG1_DP0UNLOCKCNT 0x02C
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#define S6_GREG1_DP2UNLOCKCNT 0x030
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#define S6_GREG1_DDRUNLOCKCNT 0x034
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#define S6_GREG1_CLKBAL0 0x040
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#define S6_GREG1_CLKBAL0_LSGB 0
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#define S6_GREG1_CLKBAL0_LSPX 8
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#define S6_GREG1_CLKBAL0_MEMDO 16
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#define S6_GREG1_CLKBAL0_HSXT1 24
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#define S6_GREG1_CLKBAL1 0x044
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#define S6_GREG1_CLKBAL1_HSISEF 0
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#define S6_GREG1_CLKBAL1_HSNI 8
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#define S6_GREG1_CLKBAL1_HSNS 16
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#define S6_GREG1_CLKBAL1_HSISEFCFG 24
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#define S6_GREG1_CLKBAL2 0x048
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#define S6_GREG1_CLKBAL2_LSNB 0
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#define S6_GREG1_CLKBAL2_LSSB 8
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#define S6_GREG1_CLKBAL2_LSREST 24
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#define S6_GREG1_CLKBAL3 0x04C
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#define S6_GREG1_CLKBAL3_ISEFXAD 0
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#define S6_GREG1_CLKBAL3_ISEFLMS 8
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#define S6_GREG1_CLKBAL3_ISEFISEF 16
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#define S6_GREG1_CLKBAL3_DDRDD 24
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#define S6_GREG1_CLKBAL4 0x050
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#define S6_GREG1_CLKBAL4_DDRDP 0
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#define S6_GREG1_CLKBAL4_DDRDO 8
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#define S6_GREG1_CLKBAL4_DDRNB 16
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#define S6_GREG1_CLKBAL4_DDRLMS 24
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#define S6_GREG1_BLOCKENA 0x100
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#define S6_GREG1_BLOCK_DDR 0
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#define S6_GREG1_BLOCK_DP 1
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#define S6_GREG1_BLOCK_NSNI 2
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#define S6_GREG1_BLOCK_PCIE 3
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#define S6_GREG1_BLOCK_GMAC 4
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#define S6_GREG1_BLOCK_I2S 5
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#define S6_GREG1_BLOCK_EGIB 6
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#define S6_GREG1_BLOCK_SB 7
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#define S6_GREG1_BLOCK_XT1 8
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#define S6_GREG1_CLKGATE 0x104
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#define S6_GREG1_BGATE_AIMNORTH 9
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#define S6_GREG1_BGATE_AIMEAST 10
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#define S6_GREG1_BGATE_AIMWEST 11
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#define S6_GREG1_BGATE_AIMSOUTH 12
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#define S6_GREG1_CHIPRES 0x108
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#define S6_GREG1_CHIPRES_SOFTRES 0
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#define S6_GREG1_CHIPRES_LOSTLOCK 1
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#define S6_GREG1_RESETCAUSE 0x10C
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#define S6_GREG1_RESETCAUSE_RESETN 0
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#define S6_GREG1_RESETCAUSE_GLOBAL 1
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#define S6_GREG1_RESETCAUSE_WDOGTIMER 2
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#define S6_GREG1_RESETCAUSE_SWCHIP 3
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#define S6_GREG1_RESETCAUSE_PLLSYSLOSS 4
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#define S6_GREG1_RESETCAUSE_PCIE 5
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#define S6_GREG1_RESETCAUSE_CREATEDGLOB 6
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#define S6_GREG1_REFCLOCKCNT 0x110
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#define S6_GREG1_RESETTIMER 0x114
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#define S6_GREG1_NMITIMER 0x118
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#define S6_GREG1_GLOBAL_TIMER 0x11C
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#define S6_GREG1_TIMER0 0x180
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#define S6_GREG1_TIMER1 0x184
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#define S6_GREG1_UARTCLOCKSEL 0x204
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#define S6_GREG1_CHIPVERSPACKG 0x208
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#define S6_GREG1_CHIPVERSPACKG_CHIPVID 0
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#define S6_GREG1_CHIPVERSPACKG_PACKSEL 8
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#define S6_GREG1_ONDIETERMCTRL 0x20C
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#define S6_GREG1_ONDIETERMCTRL_WEST 0
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#define S6_GREG1_ONDIETERMCTRL_NORTH 2
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#define S6_GREG1_ONDIETERMCTRL_EAST 4
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#define S6_GREG1_ONDIETERMCTRL_SOUTH 6
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#define S6_GREG1_ONDIETERMCTRL_NONE 0
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#define S6_GREG1_ONDIETERMCTRL_75OHM 2
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#define S6_GREG1_ONDIETERMCTRL_MASK 3
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#define S6_GREG1_BOOT_CFG0 0x210
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#define S6_GREG1_BOOT_CFG0_AIMSTRONG 1
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#define S6_GREG1_BOOT_CFG0_MINIBOOTDL 2
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#define S6_GREG1_BOOT_CFG0_OCDGPIO8SET 5
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#define S6_GREG1_BOOT_CFG0_OCDGPIOENA 6
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#define S6_GREG1_BOOT_CFG0_DOWNSTREAM 7
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV 8
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_300MHZ 1
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_240MHZ 2
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_200MHZ 3
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_150MHZ 4
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_120MHZ 5
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_40MHZ 6
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#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_MASK 7
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#define S6_GREG1_BOOT_CFG0_BALHSLMS 12
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#define S6_GREG1_BOOT_CFG0_BALHSNB 18
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#define S6_GREG1_BOOT_CFG0_BALHSXAD 24
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#define S6_GREG1_BOOT_CFG1 0x214
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#define S6_GREG1_BOOT_CFG1_PCIE1LANE 1
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#define S6_GREG1_BOOT_CFG1_MPLLPRESCALE 2
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#define S6_GREG1_BOOT_CFG1_MPLLNCY 4
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#define S6_GREG1_BOOT_CFG1_MPLLNCY5 9
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#define S6_GREG1_BOOT_CFG1_BALHSREST 14
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#define S6_GREG1_BOOT_CFG1_BALHSPSMEMS 20
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#define S6_GREG1_BOOT_CFG1_BALLSGI 26
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#define S6_GREG1_BOOT_CFG2 0x218
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#define S6_GREG1_BOOT_CFG2_PEID 0
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#define S6_GREG1_BOOT_CFG3 0x21C
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#define S6_GREG1_DRAMBUSYHOLDOF 0x220
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#define S6_GREG1_DRAMBUSYHOLDOF_XT0 0
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#define S6_GREG1_DRAMBUSYHOLDOF_XT1 4
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#define S6_GREG1_DRAMBUSYHOLDOF_XT_MASK 7
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#define S6_GREG1_PCIEBAR1SIZE 0x224
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#define S6_GREG1_PCIEBAR2SIZE 0x228
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#define S6_GREG1_PCIEVENDOR 0x22C
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#define S6_GREG1_PCIEDEVICE 0x230
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#define S6_GREG1_PCIEREV 0x234
|
||||
#define S6_GREG1_PCIECLASS 0x238
|
||||
#define S6_GREG1_XT1DCACHEMISS 0x240
|
||||
#define S6_GREG1_XT1ICACHEMISS 0x244
|
||||
#define S6_GREG1_HWSEMAPHORE(n) (0x400 + 4 * (n))
|
||||
#define S6_GREG1_HWSEMAPHORE_NB 16
|
||||
|
||||
/* peripheral interrupt numbers */
|
||||
|
||||
#define S6_INTC_GPIO(n) (n) /* 0..3 */
|
||||
#define S6_INTC_I2C 4
|
||||
#define S6_INTC_SPI 5
|
||||
#define S6_INTC_NB_ERR 6
|
||||
#define S6_INTC_DMA_LMSERR 7
|
||||
#define S6_INTC_DMA_LMSLOWWMRK(n) (8 + (n)) /* 0..11 */
|
||||
#define S6_INTC_DMA_LMSPENDCNT(n) (20 + (n)) /* 0..11 */
|
||||
#define S6_INTC_DMA HOSTLOWWMRK(n) (32 + (n)) /* 0..6 */
|
||||
#define S6_INTC_DMA_HOSTPENDCNT(n) (39 + (n)) /* 0..6 */
|
||||
#define S6_INTC_DMA_HOSTERR 46
|
||||
#define S6_INTC_UART(n) (47 + (n)) /* 0..1 */
|
||||
#define S6_INTC_XAD 49
|
||||
#define S6_INTC_NI_ERR 50
|
||||
#define S6_INTC_NI_INFIFOFULL 51
|
||||
#define S6_INTC_DMA_NIERR 52
|
||||
#define S6_INTC_DMA_NILOWWMRK(n) (53 + (n)) /* 0..3 */
|
||||
#define S6_INTC_DMA_NIPENDCNT(n) (57 + (n)) /* 0..3 */
|
||||
#define S6_INTC_DDR 61
|
||||
#define S6_INTC_NS_ERR 62
|
||||
#define S6_INTC_EFI_CFGERR 63
|
||||
#define S6_INTC_EFI_ISEFTEST 64
|
||||
#define S6_INTC_EFI_WRITEERR 65
|
||||
#define S6_INTC_NMI_TIMER 66
|
||||
#define S6_INTC_PLLLOCK_SYS 67
|
||||
#define S6_INTC_PLLLOCK_IO 68
|
||||
#define S6_INTC_PLLLOCK_AIM 69
|
||||
#define S6_INTC_PLLLOCK_DP0 70
|
||||
#define S6_INTC_PLLLOCK_DP2 71
|
||||
#define S6_INTC_I2S_ERR 72
|
||||
#define S6_INTC_GMAC_STAT 73
|
||||
#define S6_INTC_GMAC_ERR 74
|
||||
#define S6_INTC_GIB_ERR 75
|
||||
#define S6_INTC_PCIE_ERR 76
|
||||
#define S6_INTC_PCIE_MSI(n) (77 + (n)) /* 0..3 */
|
||||
#define S6_INTC_PCIE_INTA 81
|
||||
#define S6_INTC_PCIE_INTB 82
|
||||
#define S6_INTC_PCIE_INTC 83
|
||||
#define S6_INTC_PCIE_INTD 84
|
||||
#define S6_INTC_SW(n) (85 + (n)) /* 0..9 */
|
||||
#define S6_INTC_SW_ENABLE(n) (85 + 256 + (n))
|
||||
#define S6_INTC_DMA_DP_ERR 95
|
||||
#define S6_INTC_DMA_DPLOWWMRK(n) (96 + (n)) /* 0..3 */
|
||||
#define S6_INTC_DMA_DPPENDCNT(n) (100 + (n)) /* 0..3 */
|
||||
#define S6_INTC_DMA_DPTERMCNT(n) (104 + (n)) /* 0..3 */
|
||||
#define S6_INTC_TIMER0 108
|
||||
#define S6_INTC_TIMER1 109
|
||||
#define S6_INTC_DMA_HOSTTERMCNT(n) (110 + (n)) /* 0..6 */
|
||||
|
||||
#endif /* __XTENSA_S6000_HARDWARE_H */
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#ifndef __XTENSA_S6000_IRQ_H
|
||||
#define __XTENSA_S6000_IRQ_H
|
||||
|
||||
#define NO_IRQ (-1)
|
||||
|
||||
extern void variant_irq_enable(unsigned int irq);
|
||||
extern void variant_irq_disable(unsigned int irq);
|
||||
|
||||
#endif /* __XTENSA_S6000_IRQ_H */
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* s6000 irq crossbar
|
||||
*
|
||||
* Copyright (c) 2009 emlix GmbH
|
||||
* Authors: Johannes Weiner <jw@emlix.com>
|
||||
* Oskar Schirmer <os@emlix.com>
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <variant/hardware.h>
|
||||
|
||||
/* S6_REG_INTC */
|
||||
#define INTC_STATUS 0x000
|
||||
#define INTC_RAW 0x010
|
||||
#define INTC_STATUS_AG 0x100
|
||||
#define INTC_CFG(n) (0x200 + 4 * (n))
|
||||
|
||||
/*
|
||||
* The s6000 has a crossbar that multiplexes interrupt output lines
|
||||
* from the peripherals to input lines on the xtensa core.
|
||||
*
|
||||
* We leave the mapping decisions to the platform as it depends on the
|
||||
* actually connected peripherals which distribution makes sense.
|
||||
*/
|
||||
extern const signed char *platform_irq_mappings[NR_IRQS];
|
||||
|
||||
static unsigned long scp_to_intc_enable[] = {
|
||||
#define TO_INTC_ENABLE(n) (((n) << 1) + 1)
|
||||
TO_INTC_ENABLE(0),
|
||||
TO_INTC_ENABLE(1),
|
||||
TO_INTC_ENABLE(2),
|
||||
TO_INTC_ENABLE(3),
|
||||
TO_INTC_ENABLE(4),
|
||||
TO_INTC_ENABLE(5),
|
||||
TO_INTC_ENABLE(6),
|
||||
TO_INTC_ENABLE(7),
|
||||
TO_INTC_ENABLE(8),
|
||||
TO_INTC_ENABLE(9),
|
||||
TO_INTC_ENABLE(10),
|
||||
TO_INTC_ENABLE(11),
|
||||
TO_INTC_ENABLE(12),
|
||||
-1,
|
||||
-1,
|
||||
TO_INTC_ENABLE(13),
|
||||
-1,
|
||||
TO_INTC_ENABLE(14),
|
||||
-1,
|
||||
TO_INTC_ENABLE(15),
|
||||
#undef TO_INTC_ENABLE
|
||||
};
|
||||
|
||||
static void irq_set(unsigned int irq, int enable)
|
||||
{
|
||||
unsigned long en;
|
||||
const signed char *m = platform_irq_mappings[irq];
|
||||
|
||||
if (!m)
|
||||
return;
|
||||
en = enable ? scp_to_intc_enable[irq] : 0;
|
||||
while (*m >= 0) {
|
||||
writel(en, S6_REG_INTC + INTC_CFG(*m));
|
||||
m++;
|
||||
}
|
||||
}
|
||||
|
||||
void variant_irq_enable(unsigned int irq)
|
||||
{
|
||||
irq_set(irq, 1);
|
||||
}
|
||||
|
||||
void variant_irq_disable(unsigned int irq)
|
||||
{
|
||||
irq_set(irq, 0);
|
||||
}
|
||||
Loading…
Reference in New Issue