spi: stm32: add support for STM32F4
Add routines, registers & bitfield definition. Also baud rate divisor definitions for STM32F4 SPI. This version supports full-duplex, simplex TX and half-duplex TX communication with 8 or 16-bit per word. DMA capability is optionally supported for transfer longer than 16 bytes. For transfer less than 16 bytes frames can be send in discontinuous mode. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
Cezary Gapinski
Mark Brown
parent
55166853b2
commit
00505edf95
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@ -20,6 +20,59 @@
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#define DRIVER_NAME "spi_stm32"
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/* STM32F4 SPI registers */
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#define STM32F4_SPI_CR1 0x00
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#define STM32F4_SPI_CR2 0x04
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#define STM32F4_SPI_SR 0x08
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#define STM32F4_SPI_DR 0x0C
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#define STM32F4_SPI_I2SCFGR 0x1C
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/* STM32F4_SPI_CR1 bit fields */
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#define STM32F4_SPI_CR1_CPHA BIT(0)
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#define STM32F4_SPI_CR1_CPOL BIT(1)
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#define STM32F4_SPI_CR1_MSTR BIT(2)
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#define STM32F4_SPI_CR1_BR_SHIFT 3
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#define STM32F4_SPI_CR1_BR GENMASK(5, 3)
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#define STM32F4_SPI_CR1_SPE BIT(6)
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#define STM32F4_SPI_CR1_LSBFRST BIT(7)
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#define STM32F4_SPI_CR1_SSI BIT(8)
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#define STM32F4_SPI_CR1_SSM BIT(9)
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#define STM32F4_SPI_CR1_RXONLY BIT(10)
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#define STM32F4_SPI_CR1_DFF BIT(11)
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#define STM32F4_SPI_CR1_CRCNEXT BIT(12)
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#define STM32F4_SPI_CR1_CRCEN BIT(13)
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#define STM32F4_SPI_CR1_BIDIOE BIT(14)
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#define STM32F4_SPI_CR1_BIDIMODE BIT(15)
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#define STM32F4_SPI_CR1_BR_MIN 0
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#define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
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/* STM32F4_SPI_CR2 bit fields */
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#define STM32F4_SPI_CR2_RXDMAEN BIT(0)
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#define STM32F4_SPI_CR2_TXDMAEN BIT(1)
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#define STM32F4_SPI_CR2_SSOE BIT(2)
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#define STM32F4_SPI_CR2_FRF BIT(4)
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#define STM32F4_SPI_CR2_ERRIE BIT(5)
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#define STM32F4_SPI_CR2_RXNEIE BIT(6)
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#define STM32F4_SPI_CR2_TXEIE BIT(7)
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/* STM32F4_SPI_SR bit fields */
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#define STM32F4_SPI_SR_RXNE BIT(0)
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#define STM32F4_SPI_SR_TXE BIT(1)
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#define STM32F4_SPI_SR_CHSIDE BIT(2)
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#define STM32F4_SPI_SR_UDR BIT(3)
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#define STM32F4_SPI_SR_CRCERR BIT(4)
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#define STM32F4_SPI_SR_MODF BIT(5)
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#define STM32F4_SPI_SR_OVR BIT(6)
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#define STM32F4_SPI_SR_BSY BIT(7)
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#define STM32F4_SPI_SR_FRE BIT(8)
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/* STM32F4_SPI_I2SCFGR bit fields */
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#define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
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/* STM32F4 SPI Baud Rate min/max divisor */
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#define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
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#define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
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/* STM32H7 SPI registers */
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#define STM32H7_SPI_CR1 0x00
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#define STM32H7_SPI_CR2 0x04
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@ -116,6 +169,12 @@
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#define SPI_1HZ_NS 1000000000
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/*
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* use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
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* without fifo buffers.
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*/
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#define SPI_DMA_MIN_BYTES 16
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/**
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* stm32_spi_reg - stm32 SPI register & bitfield desc
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* @reg: register offset
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@ -257,6 +316,21 @@ struct stm32_spi {
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dma_addr_t phys_addr;
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};
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static const struct stm32_spi_regspec stm32f4_spi_regspec = {
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.en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
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.dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
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.dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
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.cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
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.cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
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.lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
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.br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
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.rx = { STM32F4_SPI_DR },
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.tx = { STM32F4_SPI_DR },
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};
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static const struct stm32_spi_regspec stm32h7_spi_regspec = {
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/* SPI data transfer is enabled but spi_ker_ck is idle.
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* CFG1 and CFG2 registers are write protected when SPE is enabled.
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@ -315,6 +389,16 @@ static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
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return count;
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}
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/**
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* stm32f4_spi_get_bpw_mask - Return bits per word mask
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* @spi: pointer to the spi controller data structure
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*/
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static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
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{
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dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
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return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
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}
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/**
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* stm32h7_spi_get_bpw_mask - Return bits per word mask
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* @spi: pointer to the spi controller data structure
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@ -408,6 +492,35 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
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return fthlv;
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}
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/**
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* stm32f4_spi_write_tx - Write bytes to Transmit Data Register
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* @spi: pointer to the spi controller data structure
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*
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* Read from tx_buf depends on remaining bytes to avoid to read beyond
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* tx_buf end.
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*/
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static void stm32f4_spi_write_tx(struct stm32_spi *spi)
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{
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if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
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STM32F4_SPI_SR_TXE)) {
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u32 offs = spi->cur_xferlen - spi->tx_len;
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if (spi->cur_bpw == 16) {
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const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
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writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
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spi->tx_len -= sizeof(u16);
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} else {
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const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
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writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
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spi->tx_len -= sizeof(u8);
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}
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}
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dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
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}
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/**
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* stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
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* @spi: pointer to the spi controller data structure
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@ -443,6 +556,35 @@ static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
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dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
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}
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/**
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* stm32f4_spi_read_rx - Read bytes from Receive Data Register
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* @spi: pointer to the spi controller data structure
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*
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* Write in rx_buf depends on remaining bytes to avoid to write beyond
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* rx_buf end.
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*/
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static void stm32f4_spi_read_rx(struct stm32_spi *spi)
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{
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if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
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STM32F4_SPI_SR_RXNE)) {
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u32 offs = spi->cur_xferlen - spi->rx_len;
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if (spi->cur_bpw == 16) {
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u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
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*rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
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spi->rx_len -= sizeof(u16);
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} else {
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u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
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*rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
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spi->rx_len -= sizeof(u8);
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}
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}
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dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
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}
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/**
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* stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
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* @spi: pointer to the spi controller data structure
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@ -501,6 +643,54 @@ static void stm32_spi_enable(struct stm32_spi *spi)
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spi->cfg->regs->en.mask);
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}
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/**
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* stm32f4_spi_disable - Disable SPI controller
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* @spi: pointer to the spi controller data structure
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*/
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static void stm32f4_spi_disable(struct stm32_spi *spi)
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{
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unsigned long flags;
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u32 sr;
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dev_dbg(spi->dev, "disable controller\n");
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spin_lock_irqsave(&spi->lock, flags);
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if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
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STM32F4_SPI_CR1_SPE)) {
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spin_unlock_irqrestore(&spi->lock, flags);
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return;
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}
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/* Disable interrupts */
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stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
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STM32F4_SPI_CR2_RXNEIE |
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STM32F4_SPI_CR2_ERRIE);
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/* Wait until BSY = 0 */
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if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
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sr, !(sr & STM32F4_SPI_SR_BSY),
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10, 100000) < 0) {
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dev_warn(spi->dev, "disabling condition timeout\n");
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}
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if (spi->cur_usedma && spi->dma_tx)
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dmaengine_terminate_all(spi->dma_tx);
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if (spi->cur_usedma && spi->dma_rx)
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dmaengine_terminate_all(spi->dma_rx);
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stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
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stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
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STM32F4_SPI_CR2_RXDMAEN);
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/* Sequence to clear OVR flag */
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readl_relaxed(spi->base + STM32F4_SPI_DR);
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readl_relaxed(spi->base + STM32F4_SPI_SR);
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spin_unlock_irqrestore(&spi->lock, flags);
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}
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/**
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* stm32h7_spi_disable - Disable SPI controller
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* @spi: pointer to the spi controller data structure
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@ -568,18 +758,128 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
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/**
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* stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
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*
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* If the current transfer size is greater than fifo size, use DMA.
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* If driver has fifo and the current transfer size is greater than fifo size,
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* use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
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*/
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static bool stm32_spi_can_dma(struct spi_master *master,
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struct spi_device *spi_dev,
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struct spi_transfer *transfer)
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{
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unsigned int dma_size;
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struct stm32_spi *spi = spi_master_get_devdata(master);
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dev_dbg(spi->dev, "%s: %s\n", __func__,
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(transfer->len > spi->fifo_size) ? "true" : "false");
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if (spi->cfg->has_fifo)
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dma_size = spi->fifo_size;
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else
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dma_size = SPI_DMA_MIN_BYTES;
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return (transfer->len > spi->fifo_size);
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dev_dbg(spi->dev, "%s: %s\n", __func__,
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(transfer->len > dma_size) ? "true" : "false");
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return (transfer->len > dma_size);
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}
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/**
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* stm32f4_spi_irq_event - Interrupt handler for SPI controller events
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* @irq: interrupt line
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* @dev_id: SPI controller master interface
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*/
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static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct stm32_spi *spi = spi_master_get_devdata(master);
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u32 sr, mask = 0;
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unsigned long flags;
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bool end = false;
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spin_lock_irqsave(&spi->lock, flags);
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sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
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/*
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* BSY flag is not handled in interrupt but it is normal behavior when
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* this flag is set.
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*/
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sr &= ~STM32F4_SPI_SR_BSY;
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if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
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spi->cur_comm == SPI_3WIRE_TX)) {
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/* OVR flag shouldn't be handled for TX only mode */
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sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
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mask |= STM32F4_SPI_SR_TXE;
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}
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if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) {
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/* TXE flag is set and is handled when RXNE flag occurs */
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sr &= ~STM32F4_SPI_SR_TXE;
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mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
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}
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if (!(sr & mask)) {
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dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
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spin_unlock_irqrestore(&spi->lock, flags);
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return IRQ_NONE;
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}
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if (sr & STM32F4_SPI_SR_OVR) {
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dev_warn(spi->dev, "Overrun: received value discarded\n");
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/* Sequence to clear OVR flag */
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readl_relaxed(spi->base + STM32F4_SPI_DR);
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readl_relaxed(spi->base + STM32F4_SPI_SR);
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/*
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* If overrun is detected, it means that something went wrong,
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* so stop the current transfer. Transfer can wait for next
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* RXNE but DR is already read and end never happens.
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*/
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end = true;
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goto end_irq;
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}
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if (sr & STM32F4_SPI_SR_TXE) {
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if (spi->tx_buf)
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stm32f4_spi_write_tx(spi);
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if (spi->tx_len == 0)
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end = true;
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}
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if (sr & STM32F4_SPI_SR_RXNE) {
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stm32f4_spi_read_rx(spi);
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if (spi->rx_len == 0)
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end = true;
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else /* Load data for discontinuous mode */
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stm32f4_spi_write_tx(spi);
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}
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end_irq:
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if (end) {
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/* Immediately disable interrupts to do not generate new one */
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stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
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STM32F4_SPI_CR2_TXEIE |
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STM32F4_SPI_CR2_RXNEIE |
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STM32F4_SPI_CR2_ERRIE);
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spin_unlock_irqrestore(&spi->lock, flags);
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return IRQ_WAKE_THREAD;
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}
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spin_unlock_irqrestore(&spi->lock, flags);
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return IRQ_HANDLED;
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}
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/**
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* stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
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* @irq: interrupt line
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* @dev_id: SPI controller master interface
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*/
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static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct stm32_spi *spi = spi_master_get_devdata(master);
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spi_finalize_current_transfer(master);
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stm32f4_spi_disable(spi);
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return IRQ_HANDLED;
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}
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/**
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@ -748,6 +1048,34 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
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return 0;
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}
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/**
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* stm32f4_spi_dma_tx_cb - dma callback
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*
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* DMA callback is called when the transfer is complete for DMA TX channel.
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*/
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static void stm32f4_spi_dma_tx_cb(void *data)
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{
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struct stm32_spi *spi = data;
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if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
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spi_finalize_current_transfer(spi->master);
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stm32f4_spi_disable(spi);
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}
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}
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/**
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* stm32f4_spi_dma_rx_cb - dma callback
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*
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* DMA callback is called when the transfer is complete for DMA RX channel.
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*/
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static void stm32f4_spi_dma_rx_cb(void *data)
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{
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struct stm32_spi *spi = data;
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spi_finalize_current_transfer(spi->master);
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stm32f4_spi_disable(spi);
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}
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/**
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* stm32h7_spi_dma_cb - dma callback
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*
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@ -790,11 +1118,15 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
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|||
else
|
||||
buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
|
||||
/* Valid for DMA Half or Full Fifo threshold */
|
||||
if (spi->cur_fthlv == 2)
|
||||
if (spi->cfg->has_fifo) {
|
||||
/* Valid for DMA Half or Full Fifo threshold */
|
||||
if (spi->cur_fthlv == 2)
|
||||
maxburst = 1;
|
||||
else
|
||||
maxburst = spi->cur_fthlv;
|
||||
} else {
|
||||
maxburst = 1;
|
||||
else
|
||||
maxburst = spi->cur_fthlv;
|
||||
}
|
||||
|
||||
memset(dma_conf, 0, sizeof(struct dma_slave_config));
|
||||
dma_conf->direction = dir;
|
||||
|
|
@ -815,6 +1147,46 @@ static void stm32_spi_dma_config(struct stm32_spi *spi,
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
|
||||
* interrupts
|
||||
*
|
||||
* It must returns 0 if the transfer is finished or 1 if the transfer is still
|
||||
* in progress.
|
||||
*/
|
||||
static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 cr2 = 0;
|
||||
|
||||
/* Enable the interrupts relative to the current communication mode */
|
||||
if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
|
||||
cr2 |= STM32F4_SPI_CR2_TXEIE;
|
||||
} else if (spi->cur_comm == SPI_FULL_DUPLEX) {
|
||||
/* In transmit-only mode, the OVR flag is set in the SR register
|
||||
* since the received data are never read. Therefore set OVR
|
||||
* interrupt only when rx buffer is available.
|
||||
*/
|
||||
cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&spi->lock, flags);
|
||||
|
||||
stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
|
||||
|
||||
stm32_spi_enable(spi);
|
||||
|
||||
/* starting data transfer when buffer is loaded */
|
||||
if (spi->tx_buf)
|
||||
stm32f4_spi_write_tx(spi);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
|
||||
* interrupts
|
||||
|
|
@ -856,6 +1228,26 @@ static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
|
|||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
|
||||
* transfer using DMA
|
||||
*/
|
||||
static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
|
||||
{
|
||||
/* In DMA mode end of transfer is handled by DMA TX or RX callback. */
|
||||
if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
|
||||
spi->cur_comm == SPI_FULL_DUPLEX) {
|
||||
/*
|
||||
* In transmit-only mode, the OVR flag is set in the SR register
|
||||
* since the received data are never read. Therefore set OVR
|
||||
* interrupt only when rx buffer is available.
|
||||
*/
|
||||
stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
|
||||
}
|
||||
|
||||
stm32_spi_enable(spi);
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
|
||||
* transfer using DMA
|
||||
|
|
@ -976,6 +1368,18 @@ dma_desc_error:
|
|||
return spi->cfg->transfer_one_irq(spi);
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32f4_spi_set_bpw - Configure bits per word
|
||||
* @spi: pointer to the spi controller data structure
|
||||
*/
|
||||
static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
|
||||
{
|
||||
if (spi->cur_bpw == 16)
|
||||
stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
|
||||
else
|
||||
stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_spi_set_bpw - configure bits per word
|
||||
* @spi: pointer to the spi controller data structure
|
||||
|
|
@ -1053,6 +1457,28 @@ static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
|
|||
return type;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32f4_spi_set_mode - configure communication mode
|
||||
* @spi: pointer to the spi controller data structure
|
||||
* @comm_type: type of communication to configure
|
||||
*/
|
||||
static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
|
||||
{
|
||||
if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
|
||||
stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
|
||||
STM32F4_SPI_CR1_BIDIMODE |
|
||||
STM32F4_SPI_CR1_BIDIOE);
|
||||
} else if (comm_type == SPI_FULL_DUPLEX) {
|
||||
stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
|
||||
STM32F4_SPI_CR1_BIDIMODE |
|
||||
STM32F4_SPI_CR1_BIDIOE);
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_spi_set_mode - configure communication mode
|
||||
* @spi: pointer to the spi controller data structure
|
||||
|
|
@ -1267,6 +1693,36 @@ static int stm32_spi_unprepare_msg(struct spi_master *master,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32f4_spi_config - Configure SPI controller as SPI master
|
||||
*/
|
||||
static int stm32f4_spi_config(struct stm32_spi *spi)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&spi->lock, flags);
|
||||
|
||||
/* Ensure I2SMOD bit is kept cleared */
|
||||
stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
|
||||
STM32F4_SPI_I2SCFGR_I2SMOD);
|
||||
|
||||
/*
|
||||
* - SS input value high
|
||||
* - transmitter half duplex direction
|
||||
* - Set the master mode (default Motorola mode)
|
||||
* - Consider 1 master/n slaves configuration and
|
||||
* SS input value is determined by the SSI bit
|
||||
*/
|
||||
stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
|
||||
STM32F4_SPI_CR1_BIDIOE |
|
||||
STM32F4_SPI_CR1_MSTR |
|
||||
STM32F4_SPI_CR1_SSM);
|
||||
|
||||
spin_unlock_irqrestore(&spi->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* stm32h7_spi_config - Configure SPI controller as SPI master
|
||||
*/
|
||||
|
|
@ -1304,6 +1760,24 @@ static int stm32h7_spi_config(struct stm32_spi *spi)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct stm32_spi_cfg stm32f4_spi_cfg = {
|
||||
.regs = &stm32f4_spi_regspec,
|
||||
.get_bpw_mask = stm32f4_spi_get_bpw_mask,
|
||||
.disable = stm32f4_spi_disable,
|
||||
.config = stm32f4_spi_config,
|
||||
.set_bpw = stm32f4_spi_set_bpw,
|
||||
.set_mode = stm32f4_spi_set_mode,
|
||||
.transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
|
||||
.dma_tx_cb = stm32f4_spi_dma_tx_cb,
|
||||
.dma_rx_cb = stm32f4_spi_dma_rx_cb,
|
||||
.transfer_one_irq = stm32f4_spi_transfer_one_irq,
|
||||
.irq_handler_event = stm32f4_spi_irq_event,
|
||||
.irq_handler_thread = stm32f4_spi_irq_thread,
|
||||
.baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
|
||||
.baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
|
||||
.has_fifo = false,
|
||||
};
|
||||
|
||||
static const struct stm32_spi_cfg stm32h7_spi_cfg = {
|
||||
.regs = &stm32h7_spi_regspec,
|
||||
.get_fifo_size = stm32h7_spi_get_fifo_size,
|
||||
|
|
@ -1326,6 +1800,7 @@ static const struct stm32_spi_cfg stm32h7_spi_cfg = {
|
|||
|
||||
static const struct of_device_id stm32_spi_of_match[] = {
|
||||
{ .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
|
||||
{ .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
|
||||
|
|
|
|||
Loading…
Reference in New Issue