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spi/pxa2xx: enable multiblock DMA transfers for LPSS devices 

Intel LPSS SPI controllers need to have bit 0 (disable_ssp_dma_finish) set
in SSP_REG in order to properly perform DMA transfers spanning over
multiple blocks.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
hifive-unleashed-5.1
Mika Westerberg 2013-03-05 12:05:17 +02:00 committed by Mark Brown
parent c134634077
commit 0054e28dc9
1 changed files with 5 additions and 0 deletions
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5
drivers/spi/spi-pxa2xx.c
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@ -68,6 +68,7 @@ MODULE_ALIAS("platform:pxa2xx-spi");
#define LPSS_TX_HITHRESH_DFLT 224
/* Offset from drv_data->lpss_base */
#define SSP_REG 0x0c
#define SPI_CS_CONTROL 0x18
#define SPI_CS_CONTROL_SW_MODE BIT(0)
#define SPI_CS_CONTROL_CS_HIGH BIT(1)
@ -138,6 +139,10 @@ detection_done:
/* Enable software chip select control */
value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
__lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
/* Enable multiblock DMA transfers */
if (drv_data->master_info->enable_dma)
__lpss_ssp_write_priv(drv_data, SSP_REG, 1);
}
static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)