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clk: meson: meson8b: add the fractional divider for vid_pll_dco 

This "vid_pll_dco" (which should be named HDMI_PLL or - as the datasheet
calls it - HPLL) has a 12-bit wide fractional parameter at
HHI_VID_PLL_CNTL2[11:0]. Add this so we correctly calculate the rate of
this PLL when u-boot is configured for a video mode which uses this
fractional parameter.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-3-martin.blumenstingl@googlemail.com
hifive-unleashed-5.1
Martin Blumenstingl 2018-12-02 22:42:19 +01:00 committed by Neil Armstrong
parent 376d8c45bd
commit 007f3da7d3
2 changed files with 6 additions and 0 deletions
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5
drivers/clk/meson/meson8b.c
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@ -137,6 +137,11 @@ static struct clk_regmap meson8b_vid_pll_dco = {
.shift = 10,
.width = 5,
},
.frac = {
.reg_off = HHI_VID_PLL_CNTL2,
.shift = 0,
.width = 12,
},
.l = {
.reg_off = HHI_VID_PLL_CNTL,
.shift = 31,

1
drivers/clk/meson/meson8b.h
View File

@ -33,6 +33,7 @@
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
/*
* MPLL register offeset taken from the S905 datasheet. Vendor kernel source