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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial 

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (43 commits)
  Documentation/trace/events.txt: Remove obsolete sched_signal_send.
  writeback: fix global_dirty_limits comment runtime -> real-time
  ppc: fix comment typo singal -> signal
  drivers: fix comment typo diable -> disable.
  m68k: fix comment typo diable -> disable.
  wireless: comment typo fix diable -> disable.
  media: comment typo fix diable -> disable.
  remove doc for obsolete dynamic-printk kernel-parameter
  remove extraneous 'is' from Documentation/iostats.txt
  Fix spelling milisec -> ms in snd_ps3 module parameter description
  Fix spelling mistakes in comments
  Revert conflicting V4L changes
  i7core_edac: fix typos in comments
  mm/rmap.c: fix comment
  sound, ca0106: Fix assignment to 'channel'.
  hrtimer: fix a typo in comment
  init/Kconfig: fix typo
  anon_inodes: fix wrong function name in comment
  fix comment typos concerning "consistent"
  poll: fix a typo in comment
  ...

Fix up trivial conflicts in:
 - drivers/net/wireless/iwlwifi/iwl-core.c (moved to iwl-legacy.c)
 - fs/ext4/ext4.h

Also fix missed 'diabled' typo in drivers/net/bnx2x/bnx2x.h while at it.
hifive-unleashed-5.1
Linus Torvalds 2011-01-13 10:05:56 -08:00
parent 8f685fbda4 bfc672dcf3
commit 008d23e485
325 changed files with 440 additions and 434 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/DocBook/mtdnand.tmpl
View File

@ -250,7 +250,7 @@ static void board_hwcontrol(struct mtd_info *mtd, int cmd)
<title>Device ready function</title>
<para>
If the hardware interface has the ready busy pin of the NAND chip connected to a
GPIO or other accesible I/O pin, this function is used to read back the state of the
GPIO or other accessible I/O pin, this function is used to read back the state of the
pin. The function has no arguments and should return 0, if the device is busy (R/B pin
is low) and 1, if the device is ready (R/B pin is high).
If the hardware interface does not give access to the ready busy pin, then

2
Documentation/cgroups/cgroup_event_listener.c
View File

@ -91,7 +91,7 @@ int main(int argc, char **argv)
if (ret == -1) {
perror("cgroup.event_control "
"is not accessable any more");
"is not accessible any more");
break;
}

2
Documentation/cgroups/memcg_test.txt
View File

@ -398,7 +398,7 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y.
written to move_charge_at_immigrate.
9.10 Memory thresholds
Memory controler implements memory thresholds using cgroups notification
Memory controller implements memory thresholds using cgroups notification
API. You can use Documentation/cgroups/cgroup_event_listener.c to test
it.

2
Documentation/iostats.txt
View File

@ -81,7 +81,7 @@ Field 9 -- # of I/Os currently in progress
The only field that should go to zero. Incremented as requests are
given to appropriate struct request_queue and decremented as they finish.
Field 10 -- # of milliseconds spent doing I/Os
This field is increases so long as field 9 is nonzero.
This field increases so long as field 9 is nonzero.
Field 11 -- weighted # of milliseconds spent doing I/Os
This field is incremented at each I/O start, I/O completion, I/O
merge, or read of these stats by the number of I/Os in progress

15
Documentation/kdump/kdump.txt
View File

@ -65,18 +65,21 @@ Install kexec-tools
2) Download the kexec-tools user-space package from the following URL:
http://www.kernel.org/pub/linux/kernel/people/horms/kexec-tools/kexec-tools.tar.gz
http://kernel.org/pub/linux/utils/kernel/kexec/kexec-tools.tar.gz
This is a symlink to the latest version.
The latest kexec-tools git tree is available at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/kexec-tools.git
or
http://www.kernel.org/git/?p=linux/kernel/git/horms/kexec-tools.git
git://git.kernel.org/pub/scm/utils/kernel/kexec/kexec-tools.git
and
http://www.kernel.org/pub/scm/utils/kernel/kexec/kexec-tools.git
There is also a gitweb interface available at
http://www.kernel.org/git/?p=utils/kernel/kexec/kexec-tools.git
More information about kexec-tools can be found at
http://www.kernel.org/pub/linux/kernel/people/horms/kexec-tools/README.html
http://www.kernel.org/pub/linux/utils/kernel/kexec/README.html
3) Unpack the tarball with the tar command, as follows:
@ -439,6 +442,6 @@ To Do
Contact
=======
Vivek Goyal (vgoyal@in.ibm.com)
Vivek Goyal (vgoyal@redhat.com)
Maneesh Soni (maneesh@in.ibm.com)

5
Documentation/kernel-parameters.txt
View File

@ -659,11 +659,6 @@ and is between 256 and 4096 characters. It is defined in the file
dscc4.setup= [NET]
dynamic_printk Enables pr_debug()/dev_dbg() calls if
CONFIG_DYNAMIC_PRINTK_DEBUG has been enabled.
These can also be switched on/off via
<debugfs>/dynamic_printk/modules
earlycon= [KNL] Output early console device and options.
uart[8250],io,<addr>[,options]
uart[8250],mmio,<addr>[,options]

4
Documentation/ko_KR/HOWTO
View File

@ -391,8 +391,8 @@ bugme-new 메일링 리스트나(새로운 버그 리포트들만이 이곳에
bugme-janitor 메일링 리스트(bugzilla에 모든 변화들이 여기서 메일로 전해진다)
에 등록하면 된다.
http://lists.osdl.org/mailman/listinfo/bugme-new
http://lists.osdl.org/mailman/listinfo/bugme-janitors
https://lists.linux-foundation.org/mailman/listinfo/bugme-new
https://lists.linux-foundation.org/mailman/listinfo/bugme-janitors

2
Documentation/kprobes.txt
View File

@ -598,7 +598,7 @@ a 5-byte jump instruction. So there are several limitations.
a) The instructions in DCR must be relocatable.
b) The instructions in DCR must not include a call instruction.
c) JTPR must not be targeted by any jump or call instruction.
d) DCR must not straddle the border betweeen functions.
d) DCR must not straddle the border between functions.
Anyway, these limitations are checked by the in-kernel instruction
decoder, so you don't need to worry about that.

2
Documentation/kvm/api.txt
View File

@ -874,7 +874,7 @@ Possible values are:
- KVM_MP_STATE_HALTED: the vcpu has executed a HLT instruction and
is waiting for an interrupt
- KVM_MP_STATE_SIPI_RECEIVED: the vcpu has just received a SIPI (vector
accesible via KVM_GET_VCPU_EVENTS)
accessible via KVM_GET_VCPU_EVENTS)
This ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel
irqchip, the multiprocessing state must be maintained by userspace.

7
Documentation/lguest/lguest.txt
View File

@ -111,8 +111,11 @@ Running Lguest:
Then use --tunnet=bridge:lg0 when launching the guest.
See http://linux-net.osdl.org/index.php/Bridge for general information
on how to get bridging working.
See:
http://www.linuxfoundation.org/collaborate/workgroups/networking/bridge
for general information on how to get bridging to work.
There is a helpful mailing list at http://ozlabs.org/mailman/listinfo/lguest

4
Documentation/networking/bridge.txt
View File

@ -1,8 +1,8 @@
In order to use the Ethernet bridging functionality, you'll need the
userspace tools. These programs and documentation are available
at http://www.linux-foundation.org/en/Net:Bridge. The download page is
at http://www.linuxfoundation.org/en/Net:Bridge. The download page is
http://prdownloads.sourceforge.net/bridge.
If you still have questions, don't hesitate to post to the mailing list
(more info http://lists.osdl.org/mailman/listinfo/bridge).
(more info https://lists.linux-foundation.org/mailman/listinfo/bridge).

2
Documentation/networking/caif/spi_porting.txt
View File

@ -32,7 +32,7 @@ the physical hardware, both with regard to SPI and to GPIOs.
This function is called by the CAIF SPI interface to give
you a chance to set up your hardware to be ready to receive
a stream of data from the master. The xfer structure contains
both physical and logical adresses, as well as the total length
both physical and logical addresses, as well as the total length
of the transfer in both directions.The dev parameter can be used
to map to different CAIF SPI slave devices.

4
Documentation/networking/dccp.txt
View File

@ -38,11 +38,11 @@ The Linux DCCP implementation does not currently support all the features that a
specified in RFCs 4340...42.
The known bugs are at:
http://linux-net.osdl.org/index.php/TODO#DCCP
http://www.linuxfoundation.org/collaborate/workgroups/networking/todo#DCCP
For more up-to-date versions of the DCCP implementation, please consider using
the experimental DCCP test tree; instructions for checking this out are on:
http://linux-net.osdl.org/index.php/DCCP_Testing#Experimental_DCCP_source_tree
http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp_testing#Experimental_DCCP_source_tree
Socket options

2
Documentation/networking/generic_netlink.txt
View File

@ -1,3 +1,3 @@
A wiki document on how to use Generic Netlink can be found here:
* http://linux-net.osdl.org/index.php/Generic_Netlink_HOWTO
* http://www.linuxfoundation.org/collaborate/workgroups/networking/generic_netlink_howto

2
Documentation/powerpc/booting-without-of.txt
View File

@ -1098,7 +1098,7 @@ supported currently at the toplevel.
* an arbitrary array of bytes
*/
childnode@addresss { /* define a child node named "childnode"
childnode@address { /* define a child node named "childnode"
* whose unit name is "childnode at
* address"
*/

2
Documentation/scheduler/00-INDEX
View File

@ -3,7 +3,7 @@
sched-arch.txt
- CPU Scheduler implementation hints for architecture specific code.
sched-design-CFS.txt
- goals, design and implementation of the Complete Fair Scheduler.
- goals, design and implementation of the Completely Fair Scheduler.
sched-domains.txt
- information on scheduling domains.
sched-nice-design.txt

2
Documentation/scsi/ChangeLog.lpfc
View File

@ -573,7 +573,7 @@ Changes from 20041018 to 20041123
* Backround nodev_timeout processing to DPC This enables us to
unblock (stop dev_loss_tmo) when appopriate.
* Fix array discovery with multiple luns. The max_luns was 0 at
the time the host structure was intialized. lpfc_cfg_params
the time the host structure was initialized. lpfc_cfg_params
then set the max_luns to the correct value afterwards.
* Remove unused define LPFC_MAX_LUN and set the default value of
lpfc_max_lun parameter to 512.

2
Documentation/timers/timer_stats.txt
View File

@ -19,7 +19,7 @@ Linux system over a sample period:
- the pid of the task(process) which initialized the timer
- the name of the process which initialized the timer
- the function where the timer was intialized
- the function where the timer was initialized
- the callback function which is associated to the timer
- the number of events (callbacks)

8
Documentation/trace/events.txt
View File

@ -125,7 +125,7 @@ is the size of the data item, in bytes.
For example, here's the information displayed for the 'sched_wakeup'
event:
# cat /debug/tracing/events/sched/sched_wakeup/format
# cat /sys/kernel/debug/tracing/events/sched/sched_wakeup/format
name: sched_wakeup
ID: 60
@ -201,19 +201,19 @@ to the 'filter' file for the given event.
For example:
# cd /debug/tracing/events/sched/sched_wakeup
# cd /sys/kernel/debug/tracing/events/sched/sched_wakeup
# echo "common_preempt_count > 4" > filter
A slightly more involved example:
# cd /debug/tracing/events/sched/sched_signal_send
# cd /sys/kernel/debug/tracing/events/signal/signal_generate
# echo "((sig >= 10 && sig < 15) || sig == 17) && comm != bash" > filter
If there is an error in the expression, you'll get an 'Invalid
argument' error when setting it, and the erroneous string along with
an error message can be seen by looking at the filter e.g.:
# cd /debug/tracing/events/sched/sched_signal_send
# cd /sys/kernel/debug/tracing/events/signal/signal_generate
# echo "((sig >= 10 && sig < 15) || dsig == 17) && comm != bash" > filter
-bash: echo: write error: Invalid argument
# cat filter

4
Documentation/zh_CN/HOWTO
View File

@ -347,8 +347,8 @@ bugzilla.kernel.org是Linux内核开发者们用来跟踪内核Bug的网站。
最新bug的通知，可以订阅bugme-new邮件列表（只有新的bug报告会被寄到这里）
或者订阅bugme-janitor邮件列表（所有bugzilla的变动都会被寄到这里）。
http://lists.osdl.org/mailman/listinfo/bugme-new
http://lists.osdl.org/mailman/listinfo/bugme-janitors
https://lists.linux-foundation.org/mailman/listinfo/bugme-new
https://lists.linux-foundation.org/mailman/listinfo/bugme-janitors
邮件列表

2
Documentation/zh_CN/SubmittingDrivers
View File

@ -61,7 +61,7 @@ Linux 2.4:
Linux 2.6:
除了遵循和 2.4 版内核同样的规则外，你还需要在 linux-kernel 邮件
列表上跟踪最新的 API 变化。向 Linux 2.6 内核提交驱动的顶级联系人
是 Andrew Morton <akpm@osdl.org>。
是 Andrew Morton <akpm@linux-foundation.org>。
决定设备驱动能否被接受的条件
----------------------------

10
MAINTAINERS
View File

@ -2007,7 +2007,7 @@ F: drivers/scsi/dc395x.*
DCCP PROTOCOL
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
L: dccp@vger.kernel.org
W: http://linux-net.osdl.org/index.php/DCCP
W: http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp
S: Maintained
F: include/linux/dccp.h
F: include/linux/tfrc.h
@ -2429,7 +2429,7 @@ ETHERNET BRIDGE
M: Stephen Hemminger <shemminger@linux-foundation.org>
L: bridge@lists.linux-foundation.org
L: netdev@vger.kernel.org
W: http://www.linux-foundation.org/en/Net:Bridge
W: http://www.linuxfoundation.org/en/Net:Bridge
S: Maintained
F: include/linux/netfilter_bridge/
F: net/bridge/
@ -4633,7 +4633,7 @@ M: Jeremy Fitzhardinge <jeremy@xensource.com>
M: Chris Wright <chrisw@sous-sol.org>
M: Alok Kataria <akataria@vmware.com>
M: Rusty Russell <rusty@rustcorp.com.au>
L: virtualization@lists.osdl.org
L: virtualization@lists.linux-foundation.org
S: Supported
F: Documentation/ia64/paravirt_ops.txt
F: arch/*/kernel/paravirt*
@ -6530,7 +6530,7 @@ F: include/linux/virtio_console.h
VIRTIO HOST (VHOST)
M: "Michael S. Tsirkin" <mst@redhat.com>
L: kvm@vger.kernel.org
L: virtualization@lists.osdl.org
L: virtualization@lists.linux-foundation.org
L: netdev@vger.kernel.org
S: Maintained
F: drivers/vhost/
@ -6800,7 +6800,7 @@ XEN HYPERVISOR INTERFACE
M: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
L: virtualization@lists.osdl.org
L: virtualization@lists.linux-foundation.org
S: Supported
F: arch/x86/xen/
F: drivers/*/xen-*front.c

2
arch/arm/common/it8152.c
View File

@ -236,7 +236,7 @@ static struct resource it8152_mem = {
/*
* The following functions are needed for DMA bouncing.
* ITE8152 chip can addrees up to 64MByte, so all the devices
* ITE8152 chip can address up to 64MByte, so all the devices
* connected to ITE8152 (PCI and USB) should have limited DMA window
*/

2
arch/arm/common/vic.c
View File

@ -70,7 +70,7 @@ static inline struct vic_device *to_vic(struct sys_device *sys)
* vic_init2 - common initialisation code
* @base: Base of the VIC.
*
* Common initialisation code for registeration
* Common initialisation code for registration
* and resume.
*/
static void vic_init2(void __iomem *base)

6
arch/arm/mach-at91/board-ecbat91.c
View File

@ -128,17 +128,17 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
.platform_data = &my_flash0_platform,
#endif
},
{ /* User accessable spi - cs1 (250KHz) */
{ /* User accessible spi - cs1 (250KHz) */
.modalias = "spi-cs1",
.chip_select = 1,
.max_speed_hz = 250 * 1000,
},
{ /* User accessable spi - cs2 (1MHz) */
{ /* User accessible spi - cs2 (1MHz) */
.modalias = "spi-cs2",
.chip_select = 2,
.max_speed_hz = 1 * 1000 * 1000,
},
{ /* User accessable spi - cs3 (10MHz) */
{ /* User accessible spi - cs3 (10MHz) */
.modalias = "spi-cs3",
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,

2
arch/arm/mach-at91/pm.c
View File

@ -301,7 +301,7 @@ static void at91_pm_end(void)
}
static struct platform_suspend_ops at91_pm_ops ={
static const struct platform_suspend_ops at91_pm_ops = {
.valid = at91_pm_valid_state,
.begin = at91_pm_begin,
.enter = at91_pm_enter,

2
arch/arm/mach-bcmring/csp/chipc/chipcHw.c
View File

@ -757,7 +757,7 @@ static int chipcHw_divide(int num, int denom)
t = t << 1;
}
/* Intialize the result */
/* Initialize the result */
r = 0;
do {

2
arch/arm/mach-bcmring/csp/dmac/dmacHw.c
View File

@ -893,7 +893,7 @@ int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);

2
arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
View File

@ -316,7 +316,7 @@ static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */
/**
* @brief Check if DMA channel is the flow controller
*
* @return 1 : If DMA is a flow controler
* @return 1 : If DMA is a flow controller
* 0 : Peripheral is the flow controller
*
* @note

2
arch/arm/mach-bcmring/csp/tmr/tmrHw.c
View File

@ -558,7 +558,7 @@ static int tmrHw_divide(int num, int denom)
t = t << 1;
}
/* Intialize the result */
/* Initialize the result */
r = 0;
do {

2
arch/arm/mach-bcmring/dma.c
View File

@ -671,7 +671,7 @@ static int ConfigChannel(DMA_Handle_t handle)
/****************************************************************************/
/**
* Intializes all of the data structures associated with the DMA.
* Initializes all of the data structures associated with the DMA.
* @return
* >= 0 - Initialization was successfull.
*

2
arch/arm/mach-bcmring/include/csp/dmacHw.h
View File

@ -590,7 +590,7 @@ void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
);
#endif /* _DMACHW_H */

4
arch/arm/mach-bcmring/include/csp/tmrHw.h
View File

@ -76,7 +76,7 @@ tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id
* certain time interval
*
* This function initializes a periodic timer to generate timer interrupt
* after every time interval in milisecond
* after every time interval in millisecond
*
* @return On success: Effective interval set in mili-second
* On failure: 0
@ -93,7 +93,7 @@ tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] T
* after certain time interval
*
* This function initializes a periodic timer to generate a single ticks after
* certain time interval in milisecond
* certain time interval in millisecond
*
* @return On success: Effective interval set in mili-second
* On failure: 0

2
arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
View File

@ -28,7 +28,7 @@
/* Data type for DMA Link List Item */
typedef struct {
uint32_t sar; /* Source Adress Register.
uint32_t sar; /* Source Address Register.
Address must be aligned to CTLx.SRC_TR_WIDTH. */
uint32_t dar; /* Destination Address Register.
Address must be aligned to CTLx.DST_TR_WIDTH. */

2
arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
View File

@ -35,7 +35,7 @@ typedef struct {
/* Data type representing DMA channel registers */
typedef struct {
dmacHw_REG64_t ChannelSar; /* Source Adress Register. 64 bits (upper 32 bits are reserved)
dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
Address must be aligned to CTLx.SRC_TR_WIDTH.
*/
dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)

2
arch/arm/mach-davinci/pm.c
View File

@ -110,7 +110,7 @@ static int davinci_pm_enter(suspend_state_t state)
return ret;
}
static struct platform_suspend_ops davinci_pm_ops = {
static const struct platform_suspend_ops davinci_pm_ops = {
.enter = davinci_pm_enter,
.valid = suspend_valid_only_mem,
};

2
arch/arm/mach-gemini/include/mach/hardware.h
View File

@ -33,7 +33,7 @@
#define GEMINI_LPC_HOST_BASE 0x47000000
#define GEMINI_LPC_IO_BASE 0x47800000
#define GEMINI_INTERRUPT_BASE 0x48000000
/* TODO: Different interrupt controlers when SMP
/* TODO: Different interrupt controllers when SMP
* #define GEMINI_INTERRUPT0_BASE 0x48000000
* #define GEMINI_INTERRUPT1_BASE 0x49000000
*/

2
arch/arm/mach-imx/pm-imx27.c
View File

@ -32,7 +32,7 @@ static int mx27_suspend_enter(suspend_state_t state)
return 0;
}
static struct platform_suspend_ops mx27_suspend_ops = {
static const struct platform_suspend_ops mx27_suspend_ops = {
.enter = mx27_suspend_enter,
.valid = suspend_valid_only_mem,
};

2
arch/arm/mach-lpc32xx/pm.c
View File

@ -123,7 +123,7 @@ static int lpc32xx_pm_enter(suspend_state_t state)
return 0;
}
static struct platform_suspend_ops lpc32xx_pm_ops = {
static const struct platform_suspend_ops lpc32xx_pm_ops = {
.valid = suspend_valid_only_mem,
.enter = lpc32xx_pm_enter,
};

2
arch/arm/mach-msm/include/mach/entry-macro-qgic.S
View File

@ -26,7 +26,7 @@
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Migrated the code from ARM MP port to be more consistant
* Migrated the code from ARM MP port to be more consistent
* with interrupt processing , the following still holds true
* however, all interrupts are treated the same regardless of
* if they are local IPI or PPI

2
arch/arm/mach-msm/io.c
View File

@ -154,7 +154,7 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{
if (mtype == MT_DEVICE) {
/* The peripherals in the 88000000 - D0000000 range
* are only accessable by type MT_DEVICE_NONSHARED.
* are only accessible by type MT_DEVICE_NONSHARED.
* Adjust mtype as necessary to make this "just work."
*/
if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))

2
arch/arm/mach-omap1/pm.c
View File

@ -647,7 +647,7 @@ static struct irqaction omap_wakeup_irq = {
static struct platform_suspend_ops omap_pm_ops ={
static const struct platform_suspend_ops omap_pm_ops = {
.prepare = omap_pm_prepare,
.enter = omap_pm_enter,
.finish = omap_pm_finish,

2
arch/arm/mach-omap2/cpuidle34xx.c
View File

@ -252,7 +252,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
* FIXME: we currently manage device-specific idle states
* for PER and CORE in combination with CPU-specific
* idle states. This is wrong, and device-specific
* idle managment needs to be separated out into
* idle management needs to be separated out into
* its own code.
*/

2
arch/arm/mach-omap2/pm24xx.c
View File

@ -350,7 +350,7 @@ static void omap2_pm_end(void)
enable_hlt();
}
static struct platform_suspend_ops omap_pm_ops = {
static const struct platform_suspend_ops omap_pm_ops = {
.begin = omap2_pm_begin,
.enter = omap2_pm_enter,
.end = omap2_pm_end,

2
arch/arm/mach-omap2/pm34xx.c
View File

@ -605,7 +605,7 @@ static void omap3_pm_end(void)
return;
}
static struct platform_suspend_ops omap_pm_ops = {
static const struct platform_suspend_ops omap_pm_ops = {
.begin = omap3_pm_begin,
.end = omap3_pm_end,
.enter = omap3_pm_enter,

2
arch/arm/mach-omap2/pm44xx.c
View File

@ -65,7 +65,7 @@ static void omap4_pm_end(void)
return;
}
static struct platform_suspend_ops omap_pm_ops = {
static const struct platform_suspend_ops omap_pm_ops = {
.begin = omap4_pm_begin,
.end = omap4_pm_end,
.enter = omap4_pm_enter,

2
arch/arm/mach-omap2/serial.c
View File

@ -852,7 +852,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
}
/**
* omap_serial_init() - intialize all supported serial ports
* omap_serial_init() - initialize all supported serial ports
*
* Initializes all available UARTs as serial ports. Platforms
* can call this function when they want to have default behaviour

2
arch/arm/mach-pnx4008/pm.c
View File

@ -119,7 +119,7 @@ static int pnx4008_pm_valid(suspend_state_t state)
(state == PM_SUSPEND_MEM);
}
static struct platform_suspend_ops pnx4008_pm_ops = {
static const struct platform_suspend_ops pnx4008_pm_ops = {
.enter = pnx4008_pm_enter,
.valid = pnx4008_pm_valid,
};

2
arch/arm/mach-pxa/mxm8x10.c
View File

@ -337,7 +337,7 @@ void __init mxm_8x10_mmc_init(void)
}
#endif
/* USB Open Host Controler Interface */
/* USB Open Host Controller Interface */
static struct pxaohci_platform_data mxm_8x10_ohci_platform_data = {
.port_mode = PMM_NPS_MODE,
.flags = ENABLE_PORT_ALL

2
arch/arm/mach-pxa/pm.c
View File

@ -96,7 +96,7 @@ void pxa_pm_finish(void)
pxa_cpu_pm_fns->finish();
}
static struct platform_suspend_ops pxa_pm_ops = {
static const struct platform_suspend_ops pxa_pm_ops = {
.valid = pxa_pm_valid,
.enter = pxa_pm_enter,
.prepare = pxa_pm_prepare,

2
arch/arm/mach-pxa/sharpsl_pm.c
View File

@ -869,7 +869,7 @@ static void sharpsl_apm_get_power_status(struct apm_power_info *info)
}
#ifdef CONFIG_PM
static struct platform_suspend_ops sharpsl_pm_ops = {
static const struct platform_suspend_ops sharpsl_pm_ops = {
.prepare = pxa_pm_prepare,
.finish = pxa_pm_finish,
.enter = corgi_pxa_pm_enter,

2
arch/arm/mach-s3c64xx/dma.c
View File

@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
/* Set all DMA configuration to be DMA, not SDMA */
writel(0xffffff, S3C_SYSREG(0x110));
/* Register standard DMA controlers */
/* Register standard DMA controllers */
s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);

2
arch/arm/mach-sa1100/pm.c
View File

@ -120,7 +120,7 @@ unsigned long sleep_phys_sp(void *sp)
return virt_to_phys(sp);
}
static struct platform_suspend_ops sa11x0_pm_ops = {
static const struct platform_suspend_ops sa11x0_pm_ops = {
.enter = sa11x0_pm_enter,
.valid = suspend_valid_only_mem,
};

4
arch/arm/mach-spear3xx/spear300.c
View File

@ -371,7 +371,7 @@ struct pmx_driver pmx_driver = {
};
/* Add spear300 specific devices here */
/* arm gpio1 device registeration */
/* arm gpio1 device registration */
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
.irq_base = SPEAR_GPIO1_INT_BASE,
@ -451,7 +451,7 @@ void __init spear300_init(void)
/* call spear3xx family common init function */
spear3xx_init();
/* shared irq registeration */
/* shared irq registration */
shirq_ras1.regs.base =
ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE);
if (shirq_ras1.regs.base) {

2
arch/arm/mach-spear3xx/spear310.c
View File

@ -266,7 +266,7 @@ void __init spear310_init(void)
/* call spear3xx family common init function */
spear3xx_init();
/* shared irq registeration */
/* shared irq registration */
base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
if (base) {
/* shirq 1 */

2
arch/arm/mach-spear3xx/spear320.c
View File

@ -519,7 +519,7 @@ void __init spear320_init(void)
/* call spear3xx family common init function */
spear3xx_init();
/* shared irq registeration */
/* shared irq registration */
base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
if (base) {
/* shirq 1 */

6
arch/arm/mach-spear3xx/spear3xx.c
View File

@ -22,7 +22,7 @@
#include <mach/spear.h>
/* Add spear3xx machines common devices here */
/* gpio device registeration */
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data = {
.gpio_base = 0,
.irq_base = SPEAR_GPIO_INT_BASE,
@ -41,7 +41,7 @@ struct amba_device gpio_device = {
.irq = {IRQ_BASIC_GPIO, NO_IRQ},
};
/* uart device registeration */
/* uart device registration */
struct amba_device uart_device = {
.dev = {
.init_name = "uart",
@ -543,6 +543,6 @@ void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size)
pmx_fail:
if (ret)
printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
printk(KERN_ERR "padmux: registration failed. err no: %d\n",
ret);
}

4
arch/arm/mach-spear6xx/spear6xx.c
View File

@ -23,7 +23,7 @@
#include <mach/spear.h>
/* Add spear6xx machines common devices here */
/* uart device registeration */
/* uart device registration */
struct amba_device uart_device[] = {
{
.dev = {
@ -50,7 +50,7 @@ struct amba_device uart_device[] = {
}
};
/* gpio device registeration */
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data[] = {
{
.gpio_base = 0,

2
arch/arm/mach-u300/Kconfig
View File

@ -64,7 +64,7 @@ config MACH_U300_DUAL_RAM
bool "Dual RAM"
help
Select this if you want support for Dual RAM phones.
This is two RAM memorys on different EMIFs.
This is two RAM memories on different EMIFs.
endchoice
config U300_DEBUG

4
arch/arm/mach-u300/include/mach/coh901318.h
View File

@ -24,7 +24,7 @@
* @src_addr: transfer source address
* @dst_addr: transfer destination address
* @link_addr: physical address to next lli
* @virt_link_addr: virtual addres of next lli (only used by pool_free)
* @virt_link_addr: virtual address of next lli (only used by pool_free)
* @phy_this: physical address of current lli (only used by pool_free)
*/
struct coh901318_lli {
@ -90,7 +90,7 @@ struct powersave {
* struct coh901318_platform - platform arch structure
* @chans_slave: specifying dma slave channels
* @chans_memcpy: specifying dma memcpy channels
* @access_memory_state: requesting DMA memeory access (on / off)
* @access_memory_state: requesting DMA memory access (on / off)
* @chan_conf: dma channel configurations
* @max_channels: max number of dma chanenls
*/

1
arch/arm/mm/flush.c
View File

@ -18,7 +18,6 @@
#include <asm/smp_plat.h>
#include <asm/system.h>
#include <asm/tlbflush.h>
#include <asm/smp_plat.h>
#include "mm.h"

2
arch/arm/plat-mxc/include/mach/irqs.h
View File

@ -70,7 +70,7 @@ extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */
#define FIQ_START 0
/* switch betwean IRQ and FIQ */
/* switch between IRQ and FIQ */
extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
#endif /* __ASM_ARCH_MXC_IRQS_H__ */

2
arch/arm/plat-omap/include/plat/omap_hwmod.h
View File

@ -351,7 +351,7 @@ struct omap_hwmod_omap2_prcm {
/**
* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
* @clkctrl_reg: PRCM address of the clock control register
* @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM
* @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
* @submodule_wkdep_bit: bit shift of the WKDEP range
*/
struct omap_hwmod_omap4_prcm {

2
arch/arm/plat-samsung/pm.c
View File

@ -355,7 +355,7 @@ static void s3c_pm_finish(void)
s3c_pm_check_cleanup();
}
static struct platform_suspend_ops s3c_pm_ops = {
static const struct platform_suspend_ops s3c_pm_ops = {
.enter = s3c_pm_enter,
.prepare = s3c_pm_prepare,
.finish = s3c_pm_finish,

2
arch/avr32/mach-at32ap/pm.c
View File

@ -176,7 +176,7 @@ out:
return 0;
}
static struct platform_suspend_ops avr32_pm_ops = {
static const struct platform_suspend_ops avr32_pm_ops = {
.valid = avr32_pm_valid_state,
.enter = avr32_pm_enter,
};

2
arch/blackfin/mach-bf537/include/mach/defBF534.h
View File

@ -1418,7 +1418,7 @@
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
#define GEN 0x0010 /* General Call Address Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */

2
arch/blackfin/mach-common/pm.c
View File

@ -223,7 +223,7 @@ static int bfin_pm_enter(suspend_state_t state)
return 0;
}
struct platform_suspend_ops bfin_pm_ops = {
static const struct platform_suspend_ops bfin_pm_ops = {
.enter = bfin_pm_enter,
.valid = bfin_pm_valid,
};

2
arch/cris/arch-v32/lib/nand_init.S
View File

@ -139,7 +139,7 @@ copy_nand_to_ram:
lsrq 8, $r4
move.b $r4, [$r1] ; Row address
lsrq 8, $r4
move.b $r4, [$r1] ; Row adddress
move.b $r4, [$r1] ; Row address
moveq 20, $r4
2: bne 2b
subq 1, $r4

2
arch/cris/include/asm/etraxgpio.h
View File

@ -1,5 +1,5 @@
/*
* The following devices are accessable using this driver using
* The following devices are accessible using this driver using
* GPIO_MAJOR (120) and a couple of minor numbers.
*
* For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):

2
arch/h8300/Kconfig.debug
View File

@ -48,7 +48,7 @@ config DEFAULT_CMDLINE
builtin kernel commandline enabled.
config KERNEL_COMMAND
string "Buildin commmand string"
string "Buildin command string"
depends on DEFAULT_CMDLINE
help
builtin kernel commandline strings.

2
arch/ia64/kvm/mmio.c
View File

@ -130,7 +130,7 @@ static void mmio_access(struct kvm_vcpu *vcpu, u64 src_pa, u64 *dest,
local_irq_save(psr);
/*Intercept the acces for PIB range*/
/*Intercept the access for PIB range*/
if (iot == GPFN_PIB) {
if (!dir)
lsapic_write(vcpu, src_pa, s, *dest);

2
arch/m68k/ifpsp060/src/fpsp.S
View File

@ -3881,7 +3881,7 @@ _fpsp_fline:
# FP Unimplemented Instruction stack frame and jump to that entry
# point.
#
# but, if the FPU is disabled, then we need to jump to the FPU diabled
# but, if the FPU is disabled, then we need to jump to the FPU disabled
# entry point.
movc %pcr,%d0
btst &0x1,%d0

2
arch/m68k/mac/psc.c
View File

@ -88,7 +88,7 @@ void __init psc_init(void)
/*
* The PSC is always at the same spot, but using psc
* keeps things consisant with the psc_xxxx functions.
* keeps things consistent with the psc_xxxx functions.
*/
psc = (void *) PSC_BASE;

2
arch/mips/alchemy/common/power.c
View File

@ -130,7 +130,7 @@ static void restore_core_regs(void)
au_writel(sleep_usb[1], USBD_ENABLE);
au_sync();
#else
/* enable accces to OTG memory */
/* enable access to OTG memory */
au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
au_sync();

2
arch/mips/alchemy/devboards/pm.c
View File

@ -110,7 +110,7 @@ static void db1x_pm_end(void)
}
static struct platform_suspend_ops db1x_pm_ops = {
static const struct platform_suspend_ops db1x_pm_ops = {
.valid = suspend_valid_only_mem,
.begin = db1x_pm_begin,
.enter = db1x_pm_enter,

2
arch/mips/include/asm/mach-powertv/ioremap.h
View File

@ -88,7 +88,7 @@ static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
}
/* These are not portable and should not be used in drivers. Drivers should
* be using ioremap() and friends to map physical addreses to virtual
* be using ioremap() and friends to map physical addresses to virtual
* addresses and dma_map*() and friends to map virtual addresses into DMA
* addresses and back.
*/

4
arch/mips/jz4740/board-qi_lb60.c
View File

@ -65,7 +65,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
/* Early prototypes of the QI LB60 had only 1GB of NAND.
* In order to support these devices aswell the partition and ecc layout is
* initalized depending on the NAND size */
* initialized depending on the NAND size */
static struct mtd_partition qi_lb60_partitions_1gb[] = {
{
.name = "NAND BOOT partition",
@ -464,7 +464,7 @@ static int __init qi_lb60_board_setup(void)
board_gpio_setup();
if (qi_lb60_init_platform_devices())
panic("Failed to initalize platform devices\n");
panic("Failed to initialize platform devices\n");
return 0;
}

2
arch/mips/jz4740/gpio.c
View File

@ -546,7 +546,7 @@ static int __init jz4740_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
printk(KERN_INFO "JZ4740 GPIO initalized\n");
printk(KERN_INFO "JZ4740 GPIO initialized\n");
return 0;
}

2
arch/mips/jz4740/pm.c
View File

@ -42,7 +42,7 @@ static int jz4740_pm_enter(suspend_state_t state)
return 0;
}
static struct platform_suspend_ops jz4740_pm_ops = {
static const struct platform_suspend_ops jz4740_pm_ops = {
.valid = suspend_valid_only_mem,
.enter = jz4740_pm_enter,
};

2
arch/mips/loongson/common/pm.c
View File

@ -147,7 +147,7 @@ static int loongson_pm_valid_state(suspend_state_t state)
}
}
static struct platform_suspend_ops loongson_pm_ops = {
static const struct platform_suspend_ops loongson_pm_ops = {
.valid = loongson_pm_valid_state,
.enter = loongson_pm_enter,
};

2
arch/mips/mti-malta/malta-memory.c
View File

@ -43,7 +43,7 @@ static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
static char *mtypes[3] = {
"Dont use memory",
"YAMON PROM memory",
"Free memmory",
"Free memory",
};
#endif

2
arch/mips/pci/pcie-octeon.c
View File

@ -900,7 +900,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
mem_access_subid.s.ror = 0;
/* Disable Relaxed Ordering for Writes. */
mem_access_subid.s.row = 0;
/* PCIe Adddress Bits <63:34>. */
/* PCIe Address Bits <63:34>. */
mem_access_subid.s.ba = 0;
/*

2
arch/mips/powertv/memory.c
View File

@ -57,7 +57,7 @@
unsigned long ptv_memsize;
/*
* struct low_mem_reserved - Items in low memmory that are reserved
* struct low_mem_reserved - Items in low memory that are reserved
* @start: Physical address of item
* @size: Size, in bytes, of this item
* @is_aliased: True if this is RAM aliased from another location. If false,

2
arch/mips/txx9/generic/pci.c
View File

@ -107,7 +107,7 @@ int txx9_pci_mem_high __initdata;
/*
* allocate pci_controller and resources.
* mem_base, io_base: physical addresss. 0 for auto assignment.
* mem_base, io_base: physical address. 0 for auto assignment.
* mem_size and io_size means max size on auto assignment.
* pcic must be &txx9_primary_pcic or NULL.
*/

4
arch/powerpc/include/asm/8xx_immap.h
View File

@ -93,7 +93,7 @@ typedef struct mem_ctlr {
} memctl8xx_t;
/*-----------------------------------------------------------------------
* BR - Memory Controler: Base Register 16-9
* BR - Memory Controller: Base Register 16-9
*/
#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
#define BR_AT_MSK 0x00007000 /* Address Type Mask */
@ -110,7 +110,7 @@ typedef struct mem_ctlr {
#define BR_V 0x00000001 /* Bank Valid */
/*-----------------------------------------------------------------------
* OR - Memory Controler: Option Register 16-11
* OR - Memory Controller: Option Register 16-11
*/
#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */

2
arch/powerpc/oprofile/op_model_cell.c
View File

@ -1469,7 +1469,7 @@ static int cell_global_start(struct op_counter_config *ctr)
* The pm_interval register is setup to write the SPU PC value into the
* trace buffer at the maximum rate possible. The trace buffer is configured
* to store the PCs, wrapping when it is full. The performance counter is
* intialized to the max hardware count minus the number of events, N, between
* initialized to the max hardware count minus the number of events, N, between
* samples. Once the N events have occured, a HW counter overflow occurs
* causing the generation of a HW counter interrupt which also stops the
* writing of the SPU PC values to the trace buffer. Hence the last PC

2
arch/powerpc/platforms/52xx/lite5200_pm.c
View File

@ -232,7 +232,7 @@ static void lite5200_pm_end(void)
lite5200_pm_target_state = PM_SUSPEND_ON;
}
static struct platform_suspend_ops lite5200_pm_ops = {
static const struct platform_suspend_ops lite5200_pm_ops = {
.valid = lite5200_pm_valid,
.begin = lite5200_pm_begin,
.prepare = lite5200_pm_prepare,

2
arch/powerpc/platforms/52xx/mpc52xx_pm.c
View File

@ -186,7 +186,7 @@ void mpc52xx_pm_finish(void)
iounmap(mbar);
}
static struct platform_suspend_ops mpc52xx_pm_ops = {
static const struct platform_suspend_ops mpc52xx_pm_ops = {
.valid = mpc52xx_pm_valid,
.prepare = mpc52xx_pm_prepare,
.enter = mpc52xx_pm_enter,

6
arch/powerpc/platforms/83xx/suspend-asm.S
View File

@ -231,7 +231,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
ori r4, r4, 0x002a
mtspr SPRN_DBAT0L, r4
lis r8, TMP_VIRT_IMMR@h
ori r4, r8, 0x001e /* 1 MByte accessable from Kernel Space only */
ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT0U, r4
isync
@ -241,7 +241,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
ori r4, r4, 0x002a
mtspr SPRN_DBAT1L, r4
lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
ori r4, r9, 0x001e /* 1 MByte accessable from Kernel Space only */
ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT1U, r4
isync
@ -253,7 +253,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
li r4, 0x0002
mtspr SPRN_DBAT2L, r4
lis r4, KERNELBASE@h
ori r4, r4, 0x001e /* 1 MByte accessable from Kernel Space only */
ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT2U, r4
isync

2
arch/powerpc/platforms/83xx/suspend.c
View File

@ -311,7 +311,7 @@ static int mpc83xx_is_pci_agent(void)
return ret;
}
static struct platform_suspend_ops mpc83xx_suspend_ops = {
static const struct platform_suspend_ops mpc83xx_suspend_ops = {
.valid = mpc83xx_suspend_valid,
.begin = mpc83xx_suspend_begin,
.enter = mpc83xx_suspend_enter,

2
arch/powerpc/platforms/85xx/mpc85xx_mds.c
View File

@ -309,7 +309,7 @@ static void __init mpc85xx_mds_qe_init(void)
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
* and QE12 for QE MII management singals in PMUXCR
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |

4
arch/powerpc/platforms/ps3/device-init.c
View File

@ -566,10 +566,10 @@ static int ps3_setup_dynamic_device(const struct ps3_repository_device *repo)
case PS3_DEV_TYPE_STOR_DISK:
result = ps3_setup_storage_dev(repo, PS3_MATCH_ID_STOR_DISK);
/* Some devices are not accessable from the Other OS lpar. */
/* Some devices are not accessible from the Other OS lpar. */
if (result == -ENODEV) {
result = 0;
pr_debug("%s:%u: not accessable\n", __func__,
pr_debug("%s:%u: not accessible\n", __func__,
__LINE__);
}

2
arch/powerpc/platforms/ps3/interrupt.c
View File

@ -44,7 +44,7 @@
* @lock:
* @ipi_debug_brk_mask:
*
* The HV mantains per SMT thread mappings of HV outlet to HV plug on
* The HV maintains per SMT thread mappings of HV outlet to HV plug on
* behalf of the guest. These mappings are implemented as 256 bit guest
* supplied bitmaps indexed by plug number. The addresses of the bitmaps
* are registered with the HV through lv1_configure_irq_state_bitmap().

2
arch/powerpc/platforms/pseries/hvCall_inst.c
View File

@ -55,7 +55,7 @@ static void hc_stop(struct seq_file *m, void *p)
static int hc_show(struct seq_file *m, void *p)
{
unsigned long h_num = (unsigned long)p;
struct hcall_stats *hs = (struct hcall_stats *)m->private;
struct hcall_stats *hs = m->private;
if (hs[h_num].num_calls) {
if (cpu_has_feature(CPU_FTR_PURR))

2
arch/powerpc/platforms/pseries/suspend.c
View File

@ -153,7 +153,7 @@ static struct sysdev_class suspend_sysdev_class = {
.name = "power",
};
static struct platform_suspend_ops pseries_suspend_ops = {
static const struct platform_suspend_ops pseries_suspend_ops = {
.valid = suspend_valid_only_mem,
.begin = pseries_suspend_begin,
.prepare_late = pseries_prepare_late,

2
arch/powerpc/sysdev/fsl_pmc.c
View File

@ -53,7 +53,7 @@ static int pmc_suspend_valid(suspend_state_t state)
return 1;
}
static struct platform_suspend_ops pmc_suspend_ops = {
static const struct platform_suspend_ops pmc_suspend_ops = {
.valid = pmc_suspend_valid,
.enter = pmc_suspend_enter,
};

2
arch/sh/boards/mach-hp6xx/pm.c
View File

@ -143,7 +143,7 @@ static int hp6x0_pm_enter(suspend_state_t state)
return 0;
}
static struct platform_suspend_ops hp6x0_pm_ops = {
static const struct platform_suspend_ops hp6x0_pm_ops = {
.enter = hp6x0_pm_enter,
.valid = suspend_valid_only_mem,
};

2
arch/sh/kernel/cpu/shmobile/pm.c
View File

@ -141,7 +141,7 @@ static int sh_pm_enter(suspend_state_t state)
return 0;
}
static struct platform_suspend_ops sh_pm_ops = {
static const struct platform_suspend_ops sh_pm_ops = {
.enter = sh_pm_enter,
.valid = suspend_valid_only_mem,
};

2
arch/sh/mm/cache-sh5.c
View File

@ -568,7 +568,7 @@ static void sh5_flush_dcache_page(void *page)
}
/*
* Flush the range [start,end] of kernel virtual adddress space from
* Flush the range [start,end] of kernel virtual address space from
* the I-cache. The corresponding range must be purged from the
* D-cache also because the SH-5 doesn't have cache snooping between
* the caches. The addresses will be visible through the superpage

2
arch/sparc/kernel/traps_64.c
View File

@ -622,7 +622,7 @@ static const char CHAFSR_PERR_msg[] =
static const char CHAFSR_IERR_msg[] =
"Internal processor error";
static const char CHAFSR_ISAP_msg[] =
"System request parity error on incoming addresss";
"System request parity error on incoming address";
static const char CHAFSR_UCU_msg[] =
"Uncorrectable E-cache ECC error for ifetch/data";
static const char CHAFSR_UCC_msg[] =

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