dt-bindings: net: wiznet: add w5x00 support
Add bindings for Wiznet's w5x00 series of SPI interfaced Ethernet chips. Based on the bindings for microchip,enc28j60. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: David S. Miller <davem@davemloft.net>alistair/sunxi64-5.4-dsi
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* Wiznet w5x00
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This is a standalone 10/100 MBit Ethernet controller with SPI interface.
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For each device connected to a SPI bus, define a child node within
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the SPI master node.
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Required properties:
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- compatible: Should be one of the following strings:
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"wiznet,w5100"
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"wiznet,w5200"
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"wiznet,w5500"
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- reg: Specify the SPI chip select the chip is wired to.
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- interrupts: Specify the interrupt index within the interrupt controller (referred
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to above in interrupt-parent) and interrupt type. w5x00 natively
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generates falling edge interrupts, however, additional board logic
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might invert the signal.
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- pinctrl-names: List of assigned state names, see pinctrl binding documentation.
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- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
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see also generic and your platform specific pinctrl binding
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documentation.
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Optional properties:
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- spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500.
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According to the w5500 datasheet, the chip allows a maximum of 80 MHz, however,
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board designs may need to limit this value.
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- local-mac-address: See ethernet.txt in the same directory.
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Example (for Raspberry Pi with pin control stuff for GPIO irq):
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&spi {
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ethernet@0: w5500@0 {
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compatible = "wiznet,w5500";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <ð1_pins>;
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interrupt-parent = <&gpio>;
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interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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spi-max-frequency = <30000000>;
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};
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};
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&gpio {
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eth1_pins: eth1_pins {
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brcm,pins = <25>;
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brcm,function = <0>; /* in */
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brcm,pull = <0>; /* none */
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};
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};
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