clocksource/drivers/imx-tpm: Add different counter width support
Different TPM modules have different width counters which is 16-bit or 32-bit, the counter width can be read from TPM_PARAM register bit[23:16], this patch adds dynamic check for counter width to support both 16-bit and 32-bit TPM modules. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>hifive-unleashed-5.1
parent
506a7be93f
commit
0136c741ff
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@ -17,9 +17,13 @@
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#include <linux/of_irq.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/sched_clock.h>
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#define TPM_PARAM 0x4
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#define TPM_PARAM_WIDTH_SHIFT 16
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#define TPM_PARAM_WIDTH_MASK (0xff << 16)
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#define TPM_SC 0x10
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#define TPM_SC 0x10
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#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3)
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#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3)
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#define TPM_SC_CMOD_DIV_DEFAULT 0x3
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#define TPM_SC_CMOD_DIV_DEFAULT 0x3
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#define TPM_SC_CMOD_DIV_MAX 0x7
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#define TPM_SC_TOF_MASK (0x1 << 7)
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#define TPM_SC_TOF_MASK (0x1 << 7)
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#define TPM_CNT 0x14
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#define TPM_CNT 0x14
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#define TPM_MOD 0x18
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#define TPM_MOD 0x18
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@ -33,6 +37,8 @@
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#define TPM_C0SC_CHF_MASK (0x1 << 7)
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#define TPM_C0SC_CHF_MASK (0x1 << 7)
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#define TPM_C0V 0x24
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#define TPM_C0V 0x24
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static int counter_width;
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static int rating;
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static void __iomem *timer_base;
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static void __iomem *timer_base;
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static struct clock_event_device clockevent_tpm;
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static struct clock_event_device clockevent_tpm;
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@ -85,10 +91,11 @@ static int __init tpm_clocksource_init(unsigned long rate)
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tpm_delay_timer.freq = rate;
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tpm_delay_timer.freq = rate;
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register_current_timer_delay(&tpm_delay_timer);
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register_current_timer_delay(&tpm_delay_timer);
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sched_clock_register(tpm_read_sched_clock, 32, rate);
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sched_clock_register(tpm_read_sched_clock, counter_width, rate);
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return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
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return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
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rate, 200, 32, clocksource_mmio_readl_up);
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rate, rating, counter_width,
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clocksource_mmio_readl_up);
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}
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}
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static int tpm_set_next_event(unsigned long delta,
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static int tpm_set_next_event(unsigned long delta,
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@ -141,7 +148,6 @@ static struct clock_event_device clockevent_tpm = {
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.set_state_oneshot = tpm_set_state_oneshot,
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.set_state_oneshot = tpm_set_state_oneshot,
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.set_next_event = tpm_set_next_event,
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.set_next_event = tpm_set_next_event,
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.set_state_shutdown = tpm_set_state_shutdown,
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.set_state_shutdown = tpm_set_state_shutdown,
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.rating = 200,
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};
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};
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static int __init tpm_clockevent_init(unsigned long rate, int irq)
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static int __init tpm_clockevent_init(unsigned long rate, int irq)
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@ -151,10 +157,11 @@ static int __init tpm_clockevent_init(unsigned long rate, int irq)
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ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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"i.MX7ULP TPM Timer", &clockevent_tpm);
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"i.MX7ULP TPM Timer", &clockevent_tpm);
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clockevent_tpm.rating = rating;
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clockevent_tpm.cpumask = cpumask_of(0);
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clockevent_tpm.cpumask = cpumask_of(0);
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clockevent_tpm.irq = irq;
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clockevent_tpm.irq = irq;
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clockevents_config_and_register(&clockevent_tpm,
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clockevents_config_and_register(&clockevent_tpm, rate, 300,
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rate, 300, 0xfffffffe);
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GENMASK(counter_width - 1, 1));
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return ret;
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return ret;
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}
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}
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@ -199,6 +206,11 @@ static int __init tpm_timer_init(struct device_node *np)
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goto err_per_clk_enable;
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goto err_per_clk_enable;
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}
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}
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counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK)
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>> TPM_PARAM_WIDTH_SHIFT;
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/* use rating 200 for 32-bit counter and 150 for 16-bit counter */
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rating = counter_width == 0x20 ? 200 : 150;
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/*
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/*
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* Initialize tpm module to a known state
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* Initialize tpm module to a known state
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* 1) Counter disabled
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* 1) Counter disabled
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@ -215,12 +227,17 @@ static int __init tpm_timer_init(struct device_node *np)
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/* CHF is W1C */
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/* CHF is W1C */
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writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
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writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
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/* increase per cnt, div 8 by default */
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/*
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writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
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* increase per cnt,
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* div 8 for 32-bit counter and div 128 for 16-bit counter
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*/
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writel(TPM_SC_CMOD_INC_PER_CNT |
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(counter_width == 0x20 ?
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TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX),
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timer_base + TPM_SC);
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timer_base + TPM_SC);
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/* set MOD register to maximum for free running mode */
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/* set MOD register to maximum for free running mode */
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writel(0xffffffff, timer_base + TPM_MOD);
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writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
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rate = clk_get_rate(per) >> 3;
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rate = clk_get_rate(per) >> 3;
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ret = tpm_clocksource_init(rate);
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ret = tpm_clocksource_init(rate);
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