intel_pstate: Refactor driver to support CPUs with different MSR layouts
Non-core processors have a different MSR layout to commumicate P state information. Refactor the driver to use CPU dependent accessors to P state information. Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>hifive-unleashed-5.1
Dirk Brandewie
Rafael J. Wysocki
parent
9c0ebcf78f
commit
016c815084
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@ -78,7 +78,6 @@ struct cpudata {
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struct timer_list timer;
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struct pstate_adjust_policy *pstate_policy;
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struct pstate_data pstate;
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struct _pid pid;
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@ -100,15 +99,21 @@ struct pstate_adjust_policy {
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int i_gain_pct;
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};
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static struct pstate_adjust_policy default_policy = {
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.sample_rate_ms = 10,
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.deadband = 0,
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.setpoint = 97,
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.p_gain_pct = 20,
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.d_gain_pct = 0,
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.i_gain_pct = 0,
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struct pstate_funcs {
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int (*get_max)(void);
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int (*get_min)(void);
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int (*get_turbo)(void);
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void (*set)(int pstate);
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};
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struct cpu_defaults {
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struct pstate_adjust_policy pid_policy;
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struct pstate_funcs funcs;
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};
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static struct pstate_adjust_policy pid_params;
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static struct pstate_funcs pstate_funcs;
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struct perf_limits {
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int no_turbo;
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int max_perf_pct;
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@ -186,14 +191,14 @@ static signed int pid_calc(struct _pid *pid, int busy)
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static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
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{
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pid_p_gain_set(&cpu->pid, cpu->pstate_policy->p_gain_pct);
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pid_d_gain_set(&cpu->pid, cpu->pstate_policy->d_gain_pct);
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pid_i_gain_set(&cpu->pid, cpu->pstate_policy->i_gain_pct);
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pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
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pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
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pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
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pid_reset(&cpu->pid,
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cpu->pstate_policy->setpoint,
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pid_params.setpoint,
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100,
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cpu->pstate_policy->deadband,
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pid_params.deadband,
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0);
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}
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@ -227,12 +232,12 @@ struct pid_param {
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};
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static struct pid_param pid_files[] = {
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{"sample_rate_ms", &default_policy.sample_rate_ms},
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{"d_gain_pct", &default_policy.d_gain_pct},
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{"i_gain_pct", &default_policy.i_gain_pct},
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{"deadband", &default_policy.deadband},
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{"setpoint", &default_policy.setpoint},
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{"p_gain_pct", &default_policy.p_gain_pct},
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{"sample_rate_ms", &pid_params.sample_rate_ms},
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{"d_gain_pct", &pid_params.d_gain_pct},
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{"i_gain_pct", &pid_params.i_gain_pct},
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{"deadband", &pid_params.deadband},
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{"setpoint", &pid_params.setpoint},
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{"p_gain_pct", &pid_params.p_gain_pct},
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{NULL, NULL}
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};
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@ -337,33 +342,60 @@ static void intel_pstate_sysfs_expose_params(void)
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}
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/************************** sysfs end ************************/
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static int intel_pstate_min_pstate(void)
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static int core_get_min_pstate(void)
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{
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u64 value;
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rdmsrl(MSR_PLATFORM_INFO, value);
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return (value >> 40) & 0xFF;
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}
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static int intel_pstate_max_pstate(void)
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static int core_get_max_pstate(void)
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{
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u64 value;
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rdmsrl(MSR_PLATFORM_INFO, value);
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return (value >> 8) & 0xFF;
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}
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static int intel_pstate_turbo_pstate(void)
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static int core_get_turbo_pstate(void)
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{
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u64 value;
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int nont, ret;
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rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
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nont = intel_pstate_max_pstate();
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nont = core_get_max_pstate();
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ret = ((value) & 255);
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if (ret <= nont)
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ret = nont;
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return ret;
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}
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static void core_set_pstate(int pstate)
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{
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u64 val;
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val = pstate << 8;
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if (limits.no_turbo)
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val |= (u64)1 << 32;
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wrmsrl(MSR_IA32_PERF_CTL, val);
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}
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static struct cpu_defaults core_params = {
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.pid_policy = {
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.sample_rate_ms = 10,
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.deadband = 0,
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.setpoint = 97,
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.p_gain_pct = 20,
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.d_gain_pct = 0,
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.i_gain_pct = 0,
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},
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.funcs = {
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.get_max = core_get_max_pstate,
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.get_min = core_get_min_pstate,
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.get_turbo = core_get_turbo_pstate,
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.set = core_set_pstate,
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},
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};
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static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
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{
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int max_perf = cpu->pstate.turbo_pstate;
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@ -383,7 +415,6 @@ static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
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static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
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{
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int max_perf, min_perf;
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u64 val;
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intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
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@ -395,11 +426,8 @@ static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
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trace_cpu_frequency(pstate * 100000, cpu->cpu);
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cpu->pstate.current_pstate = pstate;
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val = pstate << 8;
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if (limits.no_turbo)
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val |= (u64)1 << 32;
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wrmsrl(MSR_IA32_PERF_CTL, val);
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pstate_funcs.set(pstate);
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}
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static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)
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@ -421,9 +449,9 @@ static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
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{
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sprintf(cpu->name, "Intel 2nd generation core");
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cpu->pstate.min_pstate = intel_pstate_min_pstate();
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cpu->pstate.max_pstate = intel_pstate_max_pstate();
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cpu->pstate.turbo_pstate = intel_pstate_turbo_pstate();
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cpu->pstate.min_pstate = pstate_funcs.get_min();
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cpu->pstate.max_pstate = pstate_funcs.get_max();
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cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
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/*
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* goto max pstate so we don't slow up boot if we are built-in if we are
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@ -464,7 +492,7 @@ static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
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{
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int sample_time, delay;
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sample_time = cpu->pstate_policy->sample_rate_ms;
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sample_time = pid_params.sample_rate_ms;
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delay = msecs_to_jiffies(sample_time);
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mod_timer_pinned(&cpu->timer, jiffies + delay);
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}
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@ -523,14 +551,14 @@ static void intel_pstate_timer_func(unsigned long __data)
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{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&policy }
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static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
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ICPU(0x2a, default_policy),
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ICPU(0x2d, default_policy),
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ICPU(0x3a, default_policy),
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ICPU(0x3c, default_policy),
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ICPU(0x3e, default_policy),
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ICPU(0x3f, default_policy),
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ICPU(0x45, default_policy),
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ICPU(0x46, default_policy),
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ICPU(0x2a, core_params),
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ICPU(0x2d, core_params),
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ICPU(0x3a, core_params),
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ICPU(0x3c, core_params),
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ICPU(0x3e, core_params),
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ICPU(0x3f, core_params),
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ICPU(0x45, core_params),
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ICPU(0x46, core_params),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
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@ -554,8 +582,7 @@ static int intel_pstate_init_cpu(unsigned int cpunum)
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intel_pstate_get_cpu_pstates(cpu);
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cpu->cpu = cpunum;
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cpu->pstate_policy =
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(struct pstate_adjust_policy *)id->driver_data;
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init_timer_deferrable(&cpu->timer);
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cpu->timer.function = intel_pstate_timer_func;
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cpu->timer.data =
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@ -683,9 +710,9 @@ static int intel_pstate_msrs_not_valid(void)
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rdmsrl(MSR_IA32_APERF, aperf);
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rdmsrl(MSR_IA32_MPERF, mperf);
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if (!intel_pstate_min_pstate() ||
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!intel_pstate_max_pstate() ||
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!intel_pstate_turbo_pstate())
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if (!pstate_funcs.get_max() ||
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!pstate_funcs.get_min() ||
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!pstate_funcs.get_turbo())
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return -ENODEV;
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rdmsrl(MSR_IA32_APERF, tmp);
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@ -698,10 +725,30 @@ static int intel_pstate_msrs_not_valid(void)
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return 0;
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}
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void copy_pid_params(struct pstate_adjust_policy *policy)
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{
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pid_params.sample_rate_ms = policy->sample_rate_ms;
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pid_params.p_gain_pct = policy->p_gain_pct;
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pid_params.i_gain_pct = policy->i_gain_pct;
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pid_params.d_gain_pct = policy->d_gain_pct;
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pid_params.deadband = policy->deadband;
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pid_params.setpoint = policy->setpoint;
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}
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void copy_cpu_funcs(struct pstate_funcs *funcs)
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{
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pstate_funcs.get_max = funcs->get_max;
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pstate_funcs.get_min = funcs->get_min;
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pstate_funcs.get_turbo = funcs->get_turbo;
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pstate_funcs.set = funcs->set;
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}
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static int __init intel_pstate_init(void)
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{
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int cpu, rc = 0;
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const struct x86_cpu_id *id;
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struct cpu_defaults *cpu_info;
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if (no_load)
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return -ENODEV;
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@ -710,6 +757,11 @@ static int __init intel_pstate_init(void)
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if (!id)
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return -ENODEV;
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cpu_info = (struct cpu_defaults *)id->driver_data;
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copy_pid_params(&cpu_info->pid_policy);
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copy_cpu_funcs(&cpu_info->funcs);
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if (intel_pstate_msrs_not_valid())
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return -ENODEV;
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