scsi: mpt3sas: SGL to PRP Translation for I/Os to NVMe devices
* Added support for translating the SGLs associated with incoming commands either to IEE SGL or NVMe PRPs for NVMe devices. * The hardware translation of IEEE SGL to NVMe PRPs has limitations and if a command cannot be translated by hardware then it will go to firmware and the firmware needs to translate it. This will have a performance impact. To avoid that, the driver proactively checks whether the translation will be done in hardware or not. If not, then driver translates. [mkp: clarified commit message] Signed-off-by: Chaitra P B <chaitra.basappa@broadcom.com> Signed-off-by: Suganath Prabu S <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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016d5c35e2
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@ -59,6 +59,7 @@
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#include <linux/time.h>
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#include <linux/ktime.h>
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#include <linux/kthread.h>
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#include <asm/page.h> /* To get host page size per arch */
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#include <linux/aer.h>
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@ -1344,7 +1345,218 @@ _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
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}
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}
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/* IEEE format sgls */
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/**
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* base_make_prp_nvme -
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* Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only
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*
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* @ioc: per adapter object
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* @scmd: SCSI command from the mid-layer
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* @mpi_request: mpi request
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* @smid: msg Index
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* @sge_count: scatter gather element count.
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*
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* Returns: true: PRPs are built
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* false: IEEE SGLs needs to be built
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*/
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void
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base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
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struct scsi_cmnd *scmd,
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Mpi25SCSIIORequest_t *mpi_request,
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u16 smid, int sge_count)
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{
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int sge_len, offset, num_prp_in_chain = 0;
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Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
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u64 *curr_buff;
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dma_addr_t msg_phys;
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u64 sge_addr;
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u32 page_mask, page_mask_result;
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struct scatterlist *sg_scmd;
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u32 first_prp_len;
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int data_len = scsi_bufflen(scmd);
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u32 nvme_pg_size;
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nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
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/*
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* Nvme has a very convoluted prp format. One prp is required
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* for each page or partial page. Driver need to split up OS sg_list
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* entries if it is longer than one page or cross a page
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* boundary. Driver also have to insert a PRP list pointer entry as
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* the last entry in each physical page of the PRP list.
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*
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* NOTE: The first PRP "entry" is actually placed in the first
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* SGL entry in the main message as IEEE 64 format. The 2nd
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* entry in the main message is the chain element, and the rest
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* of the PRP entries are built in the contiguous pcie buffer.
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*/
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page_mask = nvme_pg_size - 1;
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/*
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* Native SGL is needed.
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* Put a chain element in main message frame that points to the first
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* chain buffer.
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*
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* NOTE: The ChainOffset field must be 0 when using a chain pointer to
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* a native SGL.
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*/
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/* Set main message chain element pointer */
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main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
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/*
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* For NVMe the chain element needs to be the 2nd SG entry in the main
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* message.
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*/
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main_chain_element = (Mpi25IeeeSgeChain64_t *)
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((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
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/*
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* For the PRP entries, use the specially allocated buffer of
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* contiguous memory. Normal chain buffers can't be used
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* because each chain buffer would need to be the size of an OS
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* page (4k).
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*/
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curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
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msg_phys = (dma_addr_t)mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
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main_chain_element->Address = cpu_to_le64(msg_phys);
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main_chain_element->NextChainOffset = 0;
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main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
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MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
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MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
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/* Build first prp, sge need not to be page aligned*/
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ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
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sg_scmd = scsi_sglist(scmd);
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sge_addr = sg_dma_address(sg_scmd);
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sge_len = sg_dma_len(sg_scmd);
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offset = (u32)(sge_addr & page_mask);
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first_prp_len = nvme_pg_size - offset;
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ptr_first_sgl->Address = cpu_to_le64(sge_addr);
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ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
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data_len -= first_prp_len;
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if (sge_len > first_prp_len) {
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sge_addr += first_prp_len;
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sge_len -= first_prp_len;
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} else if (data_len && (sge_len == first_prp_len)) {
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sg_scmd = sg_next(sg_scmd);
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sge_addr = sg_dma_address(sg_scmd);
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sge_len = sg_dma_len(sg_scmd);
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}
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for (;;) {
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offset = (u32)(sge_addr & page_mask);
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/* Put PRP pointer due to page boundary*/
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page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
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if (unlikely(!page_mask_result)) {
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scmd_printk(KERN_NOTICE,
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scmd, "page boundary curr_buff: 0x%p\n",
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curr_buff);
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msg_phys += 8;
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*curr_buff = cpu_to_le64(msg_phys);
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curr_buff++;
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num_prp_in_chain++;
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}
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*curr_buff = cpu_to_le64(sge_addr);
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curr_buff++;
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msg_phys += 8;
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num_prp_in_chain++;
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sge_addr += nvme_pg_size;
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sge_len -= nvme_pg_size;
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data_len -= nvme_pg_size;
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if (data_len <= 0)
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break;
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if (sge_len > 0)
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continue;
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sg_scmd = sg_next(sg_scmd);
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sge_addr = sg_dma_address(sg_scmd);
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sge_len = sg_dma_len(sg_scmd);
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}
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main_chain_element->Length =
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cpu_to_le32(num_prp_in_chain * sizeof(u64));
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return;
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}
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static bool
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base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
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struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
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{
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u32 data_length = 0;
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struct scatterlist *sg_scmd;
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bool build_prp = true;
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data_length = cpu_to_le32(scsi_bufflen(scmd));
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sg_scmd = scsi_sglist(scmd);
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/* If Datalenth is <= 16K and number of SGE’s entries are <= 2
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* we built IEEE SGL
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*/
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if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
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build_prp = false;
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return build_prp;
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}
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/**
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* _base_check_pcie_native_sgl - This function is called for PCIe end devices to
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* determine if the driver needs to build a native SGL. If so, that native
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* SGL is built in the special contiguous buffers allocated especially for
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* PCIe SGL creation. If the driver will not build a native SGL, return
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* TRUE and a normal IEEE SGL will be built. Currently this routine
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* supports NVMe.
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* @ioc: per adapter object
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* @mpi_request: mf request pointer
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* @smid: system request message index
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* @scmd: scsi command
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* @pcie_device: points to the PCIe device's info
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*
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* Returns 0 if native SGL was built, 1 if no SGL was built
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*/
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static int
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_base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
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Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
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struct _pcie_device *pcie_device)
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{
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struct scatterlist *sg_scmd;
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int sges_left;
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/* Get the SG list pointer and info. */
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sg_scmd = scsi_sglist(scmd);
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sges_left = scsi_dma_map(scmd);
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if (sges_left < 0) {
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sdev_printk(KERN_ERR, scmd->device,
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"scsi_dma_map failed: request for %d bytes!\n",
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scsi_bufflen(scmd));
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return 1;
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}
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/* Check if we need to build a native SG list. */
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if (base_is_prp_possible(ioc, pcie_device,
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scmd, sges_left) == 0) {
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/* We built a native SG list, just return. */
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goto out;
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}
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/*
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* Build native NVMe PRP.
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*/
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base_make_prp_nvme(ioc, scmd, mpi_request,
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smid, sges_left);
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return 0;
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out:
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scsi_dma_unmap(scmd);
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return 1;
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}
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/**
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* _base_add_sg_single_ieee - add sg element for IEEE format
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@ -1391,9 +1603,11 @@ _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
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/**
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* _base_build_sg_scmd - main sg creation routine
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* pcie_device is unused here!
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* @ioc: per adapter object
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* @scmd: scsi command
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* @smid: system request message index
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* @unused: unused pcie_device pointer
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* Context: none.
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*
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* The main routine that builds scatter gather table from a given
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*/
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static int
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_base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
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struct scsi_cmnd *scmd, u16 smid)
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struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
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{
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Mpi2SCSIIORequest_t *mpi_request;
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dma_addr_t chain_dma;
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* @ioc: per adapter object
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* @scmd: scsi command
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* @smid: system request message index
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* @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
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* constructed on need.
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* Context: none.
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*
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* The main routine that builds scatter gather table from a given
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*/
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static int
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_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
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struct scsi_cmnd *scmd, u16 smid)
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struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
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{
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Mpi2SCSIIORequest_t *mpi_request;
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Mpi25SCSIIORequest_t *mpi_request;
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dma_addr_t chain_dma;
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struct scatterlist *sg_scmd;
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void *sg_local, *chain;
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chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
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MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
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/* Check if we need to build a native SG list. */
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if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
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smid, scmd, pcie_device) == 0)) {
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/* We built a native SG list, just return. */
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return 0;
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}
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sg_scmd = scsi_sglist(scmd);
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sges_left = scsi_dma_map(scmd);
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if (sges_left < 0) {
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sg_local = &mpi_request->SGL;
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sges_in_segment = (ioc->request_sz -
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offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
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offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
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if (sges_left <= sges_in_segment)
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goto fill_in_last_segment;
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mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
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(offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
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(offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
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/* fill in main message segment when there is a chain following */
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while (sges_in_segment > 1) {
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@ -2266,6 +2489,33 @@ mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
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SCSI_SENSE_BUFFERSIZE));
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}
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/**
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* mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
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* @ioc: per adapter object
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* @smid: system request message index
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*
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* Returns virt pointer to a PCIe SGL.
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*/
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void *
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mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
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{
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return (void *)(ioc->scsi_lookup[smid - 1].pcie_sg_list.pcie_sgl);
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}
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/**
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* mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
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* @ioc: per adapter object
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* @smid: system request message index
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*
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* Returns phys pointer to the address of the PCIe buffer.
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*/
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void *
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mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
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{
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return (void *)(uintptr_t)
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(ioc->scsi_lookup[smid - 1].pcie_sg_list.pcie_sgl_dma);
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}
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/**
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* mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
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* @ioc: per adapter object
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@ -2945,6 +3195,11 @@ _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
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_base_display_OEMs_branding(ioc);
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if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
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pr_info("%sNVMe", i ? "," : "");
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i++;
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}
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pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
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if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
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@ -3245,6 +3500,17 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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kfree(ioc->reply_post);
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}
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if (ioc->pcie_sgl_dma_pool) {
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for (i = 0; i < ioc->scsiio_depth; i++) {
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if (ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl)
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pci_pool_free(ioc->pcie_sgl_dma_pool,
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ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl,
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ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl_dma);
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}
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if (ioc->pcie_sgl_dma_pool)
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pci_pool_destroy(ioc->pcie_sgl_dma_pool);
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}
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if (ioc->config_page) {
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dexitprintk(ioc, pr_info(MPT3SAS_FMT
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"config_page(0x%p): free\n", ioc->name,
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@ -3286,7 +3552,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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u16 chains_needed_per_io;
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u32 sz, total_sz, reply_post_free_sz;
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u32 retry_sz;
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u16 max_request_credit;
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u16 max_request_credit, nvme_blocks_needed;
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unsigned short sg_tablesize;
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u16 sge_size;
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int i;
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@ -3630,7 +3896,52 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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"internal(0x%p): depth(%d), start smid(%d)\n",
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ioc->name, ioc->internal,
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ioc->internal_depth, ioc->internal_smid));
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/*
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* The number of NVMe page sized blocks needed is:
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* (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
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* ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
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* that is placed in the main message frame. 8 is the size of each PRP
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* entry or PRP list pointer entry. 8 is subtracted from page_size
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* because of the PRP list pointer entry at the end of a page, so this
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* is not counted as a PRP entry. The 1 added page is a round up.
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*
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* To avoid allocation failures due to the amount of memory that could
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* be required for NVMe PRP's, only each set of NVMe blocks will be
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* contiguous, so a new set is allocated for each possible I/O.
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*/
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if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
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nvme_blocks_needed =
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(ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
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nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
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nvme_blocks_needed++;
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sz = nvme_blocks_needed * ioc->page_size;
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ioc->pcie_sgl_dma_pool =
|
||||
pci_pool_create("PCIe SGL pool", ioc->pdev, sz, 16, 0);
|
||||
if (!ioc->pcie_sgl_dma_pool) {
|
||||
pr_info(MPT3SAS_FMT
|
||||
"PCIe SGL pool: pci_pool_create failed\n",
|
||||
ioc->name);
|
||||
goto out;
|
||||
}
|
||||
for (i = 0; i < ioc->scsiio_depth; i++) {
|
||||
ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl =
|
||||
pci_pool_alloc(ioc->pcie_sgl_dma_pool,
|
||||
GFP_KERNEL,
|
||||
&ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl_dma);
|
||||
if (!ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl) {
|
||||
pr_info(MPT3SAS_FMT
|
||||
"PCIe SGL pool: pci_pool_alloc failed\n",
|
||||
ioc->name);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), "
|
||||
"element_size(%d), pool_size(%d kB)\n", ioc->name,
|
||||
ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
|
||||
total_sz += sz * ioc->scsiio_depth;
|
||||
}
|
||||
/* sense buffers, 4 byte align */
|
||||
sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
|
||||
ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
|
||||
|
@ -4475,6 +4786,19 @@ _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
|
|||
le16_to_cpu(mpi_reply.HighPriorityCredit);
|
||||
facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
|
||||
facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
|
||||
facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
|
||||
|
||||
/*
|
||||
* Get the Page Size from IOC Facts. If it's 0, default to 4k.
|
||||
*/
|
||||
ioc->page_size = 1 << facts->CurrentHostPageSize;
|
||||
if (ioc->page_size == 1) {
|
||||
pr_info(MPT3SAS_FMT "CurrentHostPageSize is 0: Setting "
|
||||
"default host page size to 4k\n", ioc->name);
|
||||
ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
|
||||
}
|
||||
dinitprintk(ioc, pr_info(MPT3SAS_FMT "CurrentHostPageSize(%d)\n",
|
||||
ioc->name, facts->CurrentHostPageSize));
|
||||
|
||||
dinitprintk(ioc, pr_info(MPT3SAS_FMT
|
||||
"hba queue depth(%d), max chains per io(%d)\n",
|
||||
|
@ -4514,6 +4838,7 @@ _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
|
|||
mpi_request.VP_ID = 0;
|
||||
mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
|
||||
mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
|
||||
mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
|
||||
|
||||
if (_base_is_controller_msix_enabled(ioc))
|
||||
mpi_request.HostMSIxVectors = ioc->reply_queue_count;
|
||||
|
|
|
@ -54,6 +54,7 @@
|
|||
#include "mpi/mpi2_raid.h"
|
||||
#include "mpi/mpi2_tool.h"
|
||||
#include "mpi/mpi2_sas.h"
|
||||
#include "mpi/mpi2_pci.h"
|
||||
|
||||
#include <scsi/scsi.h>
|
||||
#include <scsi/scsi_cmnd.h>
|
||||
|
@ -115,6 +116,7 @@
|
|||
#define MPT3SAS_KDUMP_SCSI_IO_DEPTH 200
|
||||
|
||||
#define MPT3SAS_RAID_MAX_SECTORS 8192
|
||||
#define MPT3SAS_HOST_PAGE_SIZE_4K 12
|
||||
|
||||
#define MPT_NAME_LENGTH 32 /* generic length of strings */
|
||||
#define MPT_STRING_LENGTH 64
|
||||
|
@ -132,6 +134,15 @@
|
|||
#define MAX_CHAIN_ELEMT_SZ 16
|
||||
#define DEFAULT_NUM_FWCHAIN_ELEMTS 8
|
||||
|
||||
/*
|
||||
* NVMe defines
|
||||
*/
|
||||
#define NVME_PRP_SIZE 8 /* PRP size */
|
||||
#define NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */
|
||||
#define NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */
|
||||
#define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */
|
||||
#define NVME_PRP_PAGE_SIZE 4096 /* Page size */
|
||||
|
||||
/*
|
||||
* reset phases
|
||||
*/
|
||||
|
@ -736,6 +747,16 @@ enum reset_type {
|
|||
SOFT_RESET,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pcie_sg_list - PCIe SGL buffer (contiguous per I/O)
|
||||
* @pcie_sgl: PCIe native SGL for NVMe devices
|
||||
* @pcie_sgl_dma: physical address
|
||||
*/
|
||||
struct pcie_sg_list {
|
||||
void *pcie_sgl;
|
||||
dma_addr_t pcie_sgl_dma;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct chain_tracker - firmware chain tracker
|
||||
* @chain_buffer: chain buffer
|
||||
|
@ -762,6 +783,7 @@ struct scsiio_tracker {
|
|||
struct scsi_cmnd *scmd;
|
||||
u8 cb_idx;
|
||||
u8 direct_io;
|
||||
struct pcie_sg_list pcie_sg_list;
|
||||
struct list_head chain_list;
|
||||
struct list_head tracker_list;
|
||||
u16 msix_io;
|
||||
|
@ -835,13 +857,19 @@ typedef void (*MPT_ADD_SGE)(void *paddr, u32 flags_length, dma_addr_t dma_addr);
|
|||
|
||||
/* SAS3.0 support */
|
||||
typedef int (*MPT_BUILD_SG_SCMD)(struct MPT3SAS_ADAPTER *ioc,
|
||||
struct scsi_cmnd *scmd, u16 smid);
|
||||
struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device);
|
||||
typedef void (*MPT_BUILD_SG)(struct MPT3SAS_ADAPTER *ioc, void *psge,
|
||||
dma_addr_t data_out_dma, size_t data_out_sz,
|
||||
dma_addr_t data_in_dma, size_t data_in_sz);
|
||||
typedef void (*MPT_BUILD_ZERO_LEN_SGE)(struct MPT3SAS_ADAPTER *ioc,
|
||||
void *paddr);
|
||||
|
||||
/* SAS3.5 support */
|
||||
typedef void (*NVME_BUILD_PRP)(struct MPT3SAS_ADAPTER *ioc, u16 smid,
|
||||
Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
|
||||
dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
|
||||
size_t data_in_sz);
|
||||
|
||||
/* To support atomic and non atomic descriptors*/
|
||||
typedef void (*PUT_SMID_IO_FP_HIP) (struct MPT3SAS_ADAPTER *ioc, u16 smid,
|
||||
u16 funcdep);
|
||||
|
@ -884,6 +912,7 @@ struct mpt3sas_facts {
|
|||
u16 MaxDevHandle;
|
||||
u16 MaxPersistentEntries;
|
||||
u16 MinDevHandle;
|
||||
u8 CurrentHostPageSize;
|
||||
};
|
||||
|
||||
struct mpt3sas_port_facts {
|
||||
|
@ -1223,6 +1252,11 @@ struct MPT3SAS_ADAPTER {
|
|||
int pending_io_count;
|
||||
wait_queue_head_t reset_wq;
|
||||
|
||||
/* PCIe SGL */
|
||||
struct dma_pool *pcie_sgl_dma_pool;
|
||||
/* Host Page Size */
|
||||
u32 page_size;
|
||||
|
||||
/* chain */
|
||||
struct chain_tracker *chain_lookup;
|
||||
struct list_head free_chain_list;
|
||||
|
@ -1356,7 +1390,8 @@ void *mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid);
|
|||
void *mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid);
|
||||
__le32 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc,
|
||||
u16 smid);
|
||||
|
||||
void *mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid);
|
||||
void *mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid);
|
||||
void mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc);
|
||||
|
||||
/* hi-priority queue */
|
||||
|
@ -1570,7 +1605,7 @@ void
|
|||
mpt3sas_scsi_direct_io_set(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 direct_io);
|
||||
void
|
||||
mpt3sas_setup_direct_io(struct MPT3SAS_ADAPTER *ioc, struct scsi_cmnd *scmd,
|
||||
struct _raid_device *raid_device, Mpi2SCSIIORequest_t *mpi_request,
|
||||
struct _raid_device *raid_device, Mpi25SCSIIORequest_t *mpi_request,
|
||||
u16 smid);
|
||||
|
||||
/* NCQ Prio Handling Check */
|
||||
|
|
|
@ -299,6 +299,7 @@ mpt3sas_ctl_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
_ctl_display_some_debug(ioc, smid, "ctl_done", mpi_reply);
|
||||
ioc->ctl_cmds.status &= ~MPT3_CMD_PENDING;
|
||||
complete(&ioc->ctl_cmds.done);
|
||||
|
|
|
@ -4255,7 +4255,7 @@ _scsih_flush_running_cmds(struct MPT3SAS_ADAPTER *ioc)
|
|||
*/
|
||||
static void
|
||||
_scsih_setup_eedp(struct MPT3SAS_ADAPTER *ioc, struct scsi_cmnd *scmd,
|
||||
Mpi2SCSIIORequest_t *mpi_request)
|
||||
Mpi25SCSIIORequest_t *mpi_request)
|
||||
{
|
||||
u16 eedp_flags;
|
||||
unsigned char prot_op = scsi_get_prot_op(scmd);
|
||||
|
@ -4358,7 +4358,8 @@ scsih_qcmd(struct Scsi_Host *shost, struct scsi_cmnd *scmd)
|
|||
struct _raid_device *raid_device;
|
||||
struct request *rq = scmd->request;
|
||||
int class;
|
||||
Mpi2SCSIIORequest_t *mpi_request;
|
||||
Mpi25SCSIIORequest_t *mpi_request;
|
||||
struct _pcie_device *pcie_device = NULL;
|
||||
u32 mpi_control;
|
||||
u16 smid;
|
||||
u16 handle;
|
||||
|
@ -4446,7 +4447,7 @@ scsih_qcmd(struct Scsi_Host *shost, struct scsi_cmnd *scmd)
|
|||
goto out;
|
||||
}
|
||||
mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
|
||||
memset(mpi_request, 0, sizeof(Mpi2SCSIIORequest_t));
|
||||
memset(mpi_request, 0, ioc->request_sz);
|
||||
_scsih_setup_eedp(ioc, scmd, mpi_request);
|
||||
|
||||
if (scmd->cmd_len == 32)
|
||||
|
@ -4465,13 +4466,14 @@ scsih_qcmd(struct Scsi_Host *shost, struct scsi_cmnd *scmd)
|
|||
mpi_request->SenseBufferLength = SCSI_SENSE_BUFFERSIZE;
|
||||
mpi_request->SenseBufferLowAddress =
|
||||
mpt3sas_base_get_sense_buffer_dma(ioc, smid);
|
||||
mpi_request->SGLOffset0 = offsetof(Mpi2SCSIIORequest_t, SGL) / 4;
|
||||
mpi_request->SGLOffset0 = offsetof(Mpi25SCSIIORequest_t, SGL) / 4;
|
||||
int_to_scsilun(sas_device_priv_data->lun, (struct scsi_lun *)
|
||||
mpi_request->LUN);
|
||||
memcpy(mpi_request->CDB.CDB32, scmd->cmnd, scmd->cmd_len);
|
||||
|
||||
if (mpi_request->DataLength) {
|
||||
if (ioc->build_sg_scmd(ioc, scmd, smid)) {
|
||||
pcie_device = sas_target_priv_data->pcie_dev;
|
||||
if (ioc->build_sg_scmd(ioc, scmd, smid, pcie_device)) {
|
||||
mpt3sas_base_free_smid(ioc, smid);
|
||||
goto out;
|
||||
}
|
||||
|
@ -4924,7 +4926,7 @@ out_unlock:
|
|||
static u8
|
||||
_scsih_io_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, u32 reply)
|
||||
{
|
||||
Mpi2SCSIIORequest_t *mpi_request;
|
||||
Mpi25SCSIIORequest_t *mpi_request;
|
||||
Mpi2SCSIIOReply_t *mpi_reply;
|
||||
struct scsi_cmnd *scmd;
|
||||
u16 ioc_status;
|
||||
|
|
|
@ -299,7 +299,7 @@ mpt3sas_scsi_direct_io_set(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 direct_io)
|
|||
*/
|
||||
void
|
||||
mpt3sas_setup_direct_io(struct MPT3SAS_ADAPTER *ioc, struct scsi_cmnd *scmd,
|
||||
struct _raid_device *raid_device, Mpi2SCSIIORequest_t *mpi_request,
|
||||
struct _raid_device *raid_device, Mpi25SCSIIORequest_t *mpi_request,
|
||||
u16 smid)
|
||||
{
|
||||
sector_t v_lba, p_lba, stripe_off, column, io_size;
|
||||
|
|
Loading…
Reference in a new issue