spi: rockchip: use irq rather than polling
Register an interrupt handler to fill/empty the tx and rx fifos rather than busy-looping. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
Emil Renner Berthing
Mark Brown
parent
74b7efa82b
commit
01b59ce5da
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@ -172,6 +172,11 @@ struct rockchip_spi {
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dma_addr_t dma_addr_rx;
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dma_addr_t dma_addr_tx;
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const void *tx;
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void *rx;
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unsigned int tx_left;
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unsigned int rx_left;
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atomic_t state;
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/*depth of the FIFO buffer */
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@ -182,11 +187,6 @@ struct rockchip_spi {
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u8 n_bytes;
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u8 rsd;
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const void *tx;
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const void *tx_end;
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void *rx;
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void *rx_end;
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bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
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};
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@ -222,24 +222,6 @@ static u32 get_fifo_len(struct rockchip_spi *rs)
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return (fifo == 31) ? 0 : fifo;
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}
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static inline u32 tx_max(struct rockchip_spi *rs)
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{
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u32 tx_left, tx_room;
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tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
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tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
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return min(tx_left, tx_room);
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}
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static inline u32 rx_max(struct rockchip_spi *rs)
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{
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u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
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u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
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return min(rx_left, rx_room);
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}
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static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
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{
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struct spi_master *master = spi->master;
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@ -277,6 +259,9 @@ static void rockchip_spi_handle_err(struct spi_master *master,
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*/
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spi_enable_chip(rs, false);
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/* make sure all interrupts are masked */
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writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
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if (atomic_read(&rs->state) & TXDMA)
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dmaengine_terminate_async(master->dma_tx);
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@ -286,14 +271,17 @@ static void rockchip_spi_handle_err(struct spi_master *master,
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static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
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{
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u32 max = tx_max(rs);
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u32 txw = 0;
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u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
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u32 words = min(rs->tx_left, tx_free);
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rs->tx_left -= words;
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for (; words; words--) {
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u32 txw;
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while (max--) {
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if (rs->n_bytes == 1)
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txw = *(u8 *)(rs->tx);
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txw = *(u8 *)rs->tx;
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else
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txw = *(u16 *)(rs->tx);
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txw = *(u16 *)rs->tx;
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writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
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rs->tx += rs->n_bytes;
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@ -302,46 +290,72 @@ static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
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static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
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{
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u32 max = rx_max(rs);
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u32 rxw;
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u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
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u32 rx_left = rs->rx_left - words;
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/* the hardware doesn't allow us to change fifo threshold
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* level while spi is enabled, so instead make sure to leave
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* enough words in the rx fifo to get the last interrupt
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* exactly when all words have been received
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*/
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if (rx_left) {
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u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
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if (rx_left < ftl) {
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rx_left = ftl;
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words = rs->rx_left - rx_left;
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}
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}
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rs->rx_left = rx_left;
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for (; words; words--) {
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u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
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if (!rs->rx)
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continue;
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while (max--) {
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rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
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if (rs->n_bytes == 1)
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*(u8 *)(rs->rx) = (u8)rxw;
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*(u8 *)rs->rx = (u8)rxw;
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else
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*(u16 *)(rs->rx) = (u16)rxw;
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*(u16 *)rs->rx = (u16)rxw;
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rs->rx += rs->n_bytes;
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}
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}
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static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
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static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
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{
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int remain = 0;
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struct spi_master *master = dev_id;
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struct rockchip_spi *rs = spi_master_get_devdata(master);
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if (rs->tx_left)
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rockchip_spi_pio_writer(rs);
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rockchip_spi_pio_reader(rs);
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if (!rs->rx_left) {
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spi_enable_chip(rs, false);
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writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
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spi_finalize_current_transfer(master);
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}
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return IRQ_HANDLED;
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}
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static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
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struct spi_transfer *xfer)
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{
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rs->tx = xfer->tx_buf;
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rs->rx = xfer->rx_buf;
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rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
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rs->rx_left = xfer->len / rs->n_bytes;
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writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
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spi_enable_chip(rs, true);
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do {
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if (rs->tx) {
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remain = rs->tx_end - rs->tx;
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rockchip_spi_pio_writer(rs);
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}
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if (rs->tx_left)
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rockchip_spi_pio_writer(rs);
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if (rs->rx) {
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remain = rs->rx_end - rs->rx;
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rockchip_spi_pio_reader(rs);
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}
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cpu_relax();
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} while (remain);
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/* If tx, wait until the FIFO data completely. */
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if (rs->tx)
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wait_for_idle(rs);
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spi_enable_chip(rs, false);
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return 0;
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/* 1 means the transfer is in progress */
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return 1;
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}
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static void rockchip_spi_dma_rxcb(void *data)
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@ -465,7 +479,7 @@ static void rockchip_spi_config(struct rockchip_spi *rs,
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cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
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else if (xfer->rx_buf)
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cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
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else
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else if (use_dma)
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cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
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if (use_dma) {
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@ -484,8 +498,14 @@ static void rockchip_spi_config(struct rockchip_spi *rs,
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else
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writel_relaxed((xfer->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
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writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
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writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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/* unfortunately setting the fifo threshold level to generate an
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* interrupt exactly when the fifo is full doesn't seem to work,
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* so we need the strict inequality here
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*/
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if (xfer->len < rs->fifo_len)
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writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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else
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writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
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writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
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writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
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@ -527,11 +547,6 @@ static int rockchip_spi_transfer_one(
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rs->n_bytes = xfer->bits_per_word >> 3;
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rs->tx = xfer->tx_buf;
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rs->tx_end = rs->tx + xfer->len;
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rs->rx = xfer->rx_buf;
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rs->rx_end = rs->rx + xfer->len;
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use_dma = master->can_dma ? master->can_dma(master, spi, xfer) : false;
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rockchip_spi_config(rs, spi, xfer, use_dma);
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@ -539,7 +554,7 @@ static int rockchip_spi_transfer_one(
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if (use_dma)
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return rockchip_spi_prepare_dma(rs, master, xfer);
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return rockchip_spi_pio_transfer(rs);
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return rockchip_spi_prepare_irq(rs, xfer);
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}
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static bool rockchip_spi_can_dma(struct spi_master *master,
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@ -547,8 +562,13 @@ static bool rockchip_spi_can_dma(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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struct rockchip_spi *rs = spi_master_get_devdata(master);
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unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
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return (xfer->len > rs->fifo_len);
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/* if the numbor of spi words to transfer is less than the fifo
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* length we can just fill the fifo and wait for a single irq,
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* so don't bother setting up dma
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*/
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return xfer->len / bytes_per_word >= rs->fifo_len;
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}
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static int rockchip_spi_probe(struct platform_device *pdev)
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@ -603,6 +623,15 @@ static int rockchip_spi_probe(struct platform_device *pdev)
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spi_enable_chip(rs, false);
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ret = platform_get_irq(pdev, 0);
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if (ret < 0)
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goto err_disable_spiclk;
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ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
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IRQF_ONESHOT, dev_name(&pdev->dev), master);
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if (ret)
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goto err_disable_spiclk;
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rs->dev = &pdev->dev;
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rs->freq = clk_get_rate(rs->spiclk);
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