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arm64: dts: mipi-lvds: fix mipi rx/tx clocks 

By default, the MIPI RX and TX clocks are parented to the BYPASS clock,
but it seems that this doesn't work on QXP. Since these clocks can also
be parented to MIPI_PLL and MIPI_PLL_DIV2, use the MIPI_PLL_DIV2 with a
fixed rate of 432M and parent the RX and TX clocks to it.
This works on both QM and QXP.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Aisheng Dong 2019-12-06 11:42:30 +00:00 committed by Robert Chiras
parent a6a3a9cd11
commit 01b8b7a56f
2 changed files with 38 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi
View File

@ -12,6 +12,13 @@
clock-output-names = "dsi_ipg_clk";
};
mipi_pll_div2_clk: clock-mipi-div2-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <432000000>;
clock-output-names = "mipi_pll_div2_clk";
};
mipi0_subsys: bus@56220000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -148,9 +155,13 @@
"phy_ref",
"tx_esc",
"rx_esc";
assigned-clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
assigned-clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>,
<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>;
assigned-clock-rates = <18000000>, <72000000>;
assigned-clock-parents = <&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>;
assigned-clock-rates = <0>, <18000000>, <72000000>;
interrupts = <16>;
interrupt-parent = <&irqsteer_mipi0>;
power-domains = <&pd IMX_SC_R_MIPI_0>;
@ -314,9 +325,13 @@
"phy_ref",
"tx_esc",
"rx_esc";
assigned-clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
assigned-clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>,
<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>;
assigned-clock-rates = <18000000>, <72000000>;
assigned-clock-parents = <&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>;
assigned-clock-rates = <0>, <18000000>, <72000000>;
interrupts = <16>;
interrupt-parent = <&irqsteer_mipi1>;
power-domains = <&pd IMX_SC_R_MIPI_1>;

23
arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi
View File

@ -18,6 +18,13 @@
clock-output-names = "mipi_ipg_clk";
};
mipi_pll_div2_clk: clock-mipi-div2-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <432000000>;
clock-output-names = "mipi_pll_div2_clk";
};
mipi0_lis_lpcg: clock-controller@56223000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x56223000 0x4>;
@ -223,9 +230,13 @@
"phy_ref",
"tx_esc",
"rx_esc";
assigned-clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
assigned-clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>,
<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
<&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>;
assigned-clock-rates = <18000000>, <72000000>;
assigned-clock-parents = <&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>;
assigned-clock-rates = <0>, <18000000>, <72000000>;
interrupts = <16>;
interrupt-parent = <&irqsteer_mipi_lvds0>;
power-domains = <&pd IMX_SC_R_MIPI_0>;
@ -385,9 +396,13 @@
"phy_ref",
"tx_esc",
"rx_esc";
assigned-clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
assigned-clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>,
<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
<&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>;
assigned-clock-rates = <18000000>, <72000000>;
assigned-clock-parents = <&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>,
<&mipi_pll_div2_clk>;
assigned-clock-rates = <0>, <18000000>, <72000000>;
interrupts = <16>;
interrupt-parent = <&irqsteer_mipi_lvds1>;
power-domains = <&pd IMX_SC_R_MIPI_1>;