dt-bindings: display: dw-hdmi: Clean up DT bindings documentation
Make it clear that the core bridge/dw_hdmi.txt document isn't a device tree binding by itself but is meant to be referenced by platform device tree bindings, and update the Rockchip and Freescale DWC HDMI TX bindings to reference it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-21-laurent.pinchart+renesas@ideasonboard.comhifive-unleashed-5.1
Laurent Pinchart
Archit Taneja
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2668db3788
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01f8c951c2
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DesignWare HDMI bridge bindings
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Synopsys DesignWare HDMI TX Encoder
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===================================
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Required properties:
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- compatible: platform specific such as:
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* "snps,dw-hdmi-tx"
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* "fsl,imx6q-hdmi"
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* "fsl,imx6dl-hdmi"
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* "rockchip,rk3288-dw-hdmi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The HDMI interrupt number
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- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
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as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,
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the clocks are soc specific, the clock-names should be "iahb", "isfr"
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-port@[X]: SoC specific port nodes with endpoint definitions as defined
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in Documentation/devicetree/bindings/media/video-interfaces.txt,
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please refer to the SoC specific binding document:
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* Documentation/devicetree/bindings/display/imx/hdmi.txt
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* Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
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This document defines device tree properties for the Synopsys DesignWare HDMI
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TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
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specification by itself but is meant to be referenced by platform-specific
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device tree bindings.
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Optional properties
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- reg-io-width: the width of the reg:1,4, default set to 1 if not present
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
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if the property is omitted, a functionally reduced I2C bus
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controller on DW HDMI is probed
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- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
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When referenced from platform device tree bindings the properties defined in
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this document are defined as follows. The platform device tree bindings are
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responsible for defining whether each property is required or optional.
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Example:
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hdmi: hdmi@0120000 {
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compatible = "fsl,imx6q-hdmi";
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reg = <0x00120000 0x9000>;
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interrupts = <0 115 0x04>;
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gpr = <&gpr>;
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clocks = <&clks 123>, <&clks 124>;
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clock-names = "iahb", "isfr";
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ddc-i2c-bus = <&i2c2>;
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- reg: Memory mapped base address and length of the DWC HDMI TX registers.
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port@0 {
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reg = <0>;
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- reg-io-width: Width of the registers specified by the reg property. The
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value is expressed in bytes and must be equal to 1 or 4 if specified. The
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register width defaults to 1 if the property is not present.
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hdmi_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_hdmi>;
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};
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};
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- interrupts: Reference to the DWC HDMI TX interrupt.
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port@1 {
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reg = <1>;
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- clocks: References to all the clocks specified in the clock-names property
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as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
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hdmi_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_hdmi>;
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};
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};
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};
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- clock-names: The DWC HDMI TX uses the following clocks.
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- "iahb" is the bus clock for either AHB and APB (mandatory).
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- "isfr" is the internal register configuration clock (mandatory).
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- "cec" is the HDMI CEC controller main clock (optional).
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- ports: The connectivity of the DWC HDMI TX with the rest of the system is
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expressed in using ports as specified in the device graph bindings defined
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in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
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is platform-specific.
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@ -1,29 +1,36 @@
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Device-Tree bindings for HDMI Transmitter
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Freescale i.MX6 DWC HDMI TX Encoder
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===================================
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HDMI Transmitter
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================
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with a companion PHY IP.
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These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
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Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
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following device-specific properties.
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The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with accompanying PHY IP.
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Required properties:
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- #address-cells : should be <1>
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- #size-cells : should be <0>
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- compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
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- gpr : should be <&gpr>.
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The phandle points to the iomuxc-gpr region containing the HDMI
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multiplexer control register.
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- clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
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in Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx6q-clock.txt.
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- port@[0-4]: Up to four port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt,
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corresponding to the four inputs to the HDMI multiplexer.
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Optional properties:
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
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- reg: See dw_hdmi.txt.
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- interrupts: HDMI interrupt number
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- clocks: See dw_hdmi.txt.
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- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
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- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
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numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
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Each port shall have a single endpoint.
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- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
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multiplexer control register.
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example:
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Optional properties
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- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
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or the functionally-reduced I2C master contained in the DWC HDMI. When
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connected to a system I2C master this property contains a phandle to that
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I2C master controller.
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Example:
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gpr: iomuxc-gpr@020e0000 {
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/* ... */
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@ -1,24 +1,39 @@
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Rockchip specific extensions to the Synopsys Designware HDMI
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================================
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Rockchip DWC HDMI TX Encoder
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============================
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with a companion PHY IP.
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These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
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Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
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following device-specific properties.
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Required properties:
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- compatible: "rockchip,rk3288-dw-hdmi";
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- reg: Physical base address and length of the controller's registers.
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- clocks: phandle to hdmi iahb and isfr clocks.
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- clock-names: should be "iahb" "isfr"
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- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
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- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
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- reg: See dw_hdmi.txt.
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- reg-io-width: See dw_hdmi.txt. Shall be 4.
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- interrupts: HDMI interrupt number
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- ports: contain a port node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. For
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vopb,set the reg = <0> and set the reg = <1> for vopl.
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- reg-io-width: the width of the reg:1,4, the value should be 4 on
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rk3288 platform
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- clocks: See dw_hdmi.txt.
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- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
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- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
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corresponding to the video input of the controller. The port shall have two
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endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
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- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
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Optional properties
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
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- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
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or the functionally-reduced I2C master contained in the DWC HDMI. When
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connected to a system I2C master this property contains a phandle to that
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I2C master controller.
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- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
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- clock-names: May contain "cec" as defined in dw_hdmi.txt.
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Example:
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hdmi: hdmi@ff980000 {
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compatible = "rockchip,rk3288-dw-hdmi";
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reg = <0xff980000 0x20000>;
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