iommu/arm-smmu: Wire up generic configuration support
With everything else now in place, fill in an of_xlate callback and the appropriate registration to plumb into the generic configuration machinery, and watch everything just work. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>hifive-unleashed-5.1
Robin Murphy
Will Deacon
parent
d0acbb750a
commit
021bb8420d
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@ -418,6 +418,8 @@ struct arm_smmu_option_prop {
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static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);
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static bool using_legacy_binding, using_generic_binding;
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static struct arm_smmu_option_prop arm_smmu_options[] = {
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{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
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{ 0, NULL},
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@ -817,12 +819,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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if (smmu_domain->smmu)
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goto out_unlock;
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/* We're bypassing these SIDs, so don't allocate an actual context */
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if (domain->type == IOMMU_DOMAIN_DMA) {
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smmu_domain->smmu = smmu;
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goto out_unlock;
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}
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/*
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* Mapping the requested stage onto what we support is surprisingly
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* complicated, mainly because the spec allows S1+S2 SMMUs without
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@ -981,7 +977,7 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
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void __iomem *cb_base;
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int irq;
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if (!smmu || domain->type == IOMMU_DOMAIN_DMA)
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if (!smmu)
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return;
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/*
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@ -1015,8 +1011,8 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
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if (!smmu_domain)
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return NULL;
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if (type == IOMMU_DOMAIN_DMA &&
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iommu_get_dma_cookie(&smmu_domain->domain)) {
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if (type == IOMMU_DOMAIN_DMA && (using_legacy_binding ||
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iommu_get_dma_cookie(&smmu_domain->domain))) {
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kfree(smmu_domain);
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return NULL;
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}
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@ -1133,19 +1129,22 @@ static int arm_smmu_master_alloc_smes(struct device *dev)
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mutex_lock(&smmu->stream_map_mutex);
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/* Figure out a viable stream map entry allocation */
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for_each_cfg_sme(fwspec, i, idx) {
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u16 sid = fwspec->ids[i];
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u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;
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if (idx != INVALID_SMENDX) {
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ret = -EEXIST;
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goto out_err;
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}
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ret = arm_smmu_find_sme(smmu, fwspec->ids[i], 0);
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ret = arm_smmu_find_sme(smmu, sid, mask);
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if (ret < 0)
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goto out_err;
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idx = ret;
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if (smrs && smmu->s2crs[idx].count == 0) {
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smrs[idx].id = fwspec->ids[i];
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smrs[idx].mask = 0; /* We don't currently share SMRs */
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smrs[idx].id = sid;
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smrs[idx].mask = mask;
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smrs[idx].valid = true;
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}
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smmu->s2crs[idx].count++;
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@ -1203,15 +1202,6 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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u8 cbndx = smmu_domain->cfg.cbndx;
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int i, idx;
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/*
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* FIXME: This won't be needed once we have IOMMU-backed DMA ops
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* for all devices behind the SMMU. Note that we need to take
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* care configuring SMRs for devices both a platform_device and
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* and a PCI device (i.e. a PCI host controller)
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*/
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if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA)
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type = S2CR_TYPE_BYPASS;
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for_each_cfg_sme(fwspec, i, idx) {
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if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)
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continue;
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@ -1373,25 +1363,50 @@ static bool arm_smmu_capable(enum iommu_cap cap)
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}
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}
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static int arm_smmu_match_node(struct device *dev, void *data)
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{
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return dev->of_node == data;
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}
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static struct arm_smmu_device *arm_smmu_get_by_node(struct device_node *np)
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{
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struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
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np, arm_smmu_match_node);
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put_device(dev);
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return dev ? dev_get_drvdata(dev) : NULL;
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}
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static int arm_smmu_add_device(struct device *dev)
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{
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struct arm_smmu_device *smmu;
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struct arm_smmu_master_cfg *cfg;
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struct iommu_fwspec *fwspec;
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struct iommu_fwspec *fwspec = dev->iommu_fwspec;
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int i, ret;
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ret = arm_smmu_register_legacy_master(dev, &smmu);
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fwspec = dev->iommu_fwspec;
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if (ret)
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goto out_free;
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if (using_legacy_binding) {
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ret = arm_smmu_register_legacy_master(dev, &smmu);
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fwspec = dev->iommu_fwspec;
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if (ret)
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goto out_free;
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} else if (fwspec) {
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smmu = arm_smmu_get_by_node(to_of_node(fwspec->iommu_fwnode));
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} else {
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return -ENODEV;
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}
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ret = -EINVAL;
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for (i = 0; i < fwspec->num_ids; i++) {
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u16 sid = fwspec->ids[i];
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u16 mask = fwspec->ids[i] >> SMR_MASK_SHIFT;
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if (sid & ~smmu->streamid_mask) {
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dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n",
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sid, cfg->smmu->streamid_mask);
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sid, smmu->streamid_mask);
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goto out_free;
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}
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if (mask & ~smmu->smr_mask_mask) {
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dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n",
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sid, smmu->smr_mask_mask);
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goto out_free;
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}
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}
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@ -1503,6 +1518,19 @@ out_unlock:
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return ret;
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}
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static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
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{
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u32 fwid = 0;
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if (args->args_count > 0)
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fwid |= (u16)args->args[0];
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if (args->args_count > 1)
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fwid |= (u16)args->args[1] << SMR_MASK_SHIFT;
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return iommu_fwspec_add_ids(dev, &fwid, 1);
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}
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static struct iommu_ops arm_smmu_ops = {
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.capable = arm_smmu_capable,
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.domain_alloc = arm_smmu_domain_alloc,
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@ -1517,6 +1545,7 @@ static struct iommu_ops arm_smmu_ops = {
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.device_group = arm_smmu_device_group,
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.domain_get_attr = arm_smmu_domain_get_attr,
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.domain_set_attr = arm_smmu_domain_set_attr,
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.of_xlate = arm_smmu_of_xlate,
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.pgsize_bitmap = -1UL, /* Restricted during device attach */
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};
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@ -1870,6 +1899,19 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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struct arm_smmu_device *smmu;
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struct device *dev = &pdev->dev;
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int num_irqs, i, err;
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bool legacy_binding;
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legacy_binding = of_find_property(dev->of_node, "mmu-masters", NULL);
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if (legacy_binding && !using_generic_binding) {
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if (!using_legacy_binding)
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pr_notice("deprecated \"mmu-masters\" DT property in use; DMA API support unavailable\n");
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using_legacy_binding = true;
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} else if (!legacy_binding && !using_legacy_binding) {
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using_generic_binding = true;
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} else {
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dev_err(dev, "not probing due to mismatched DT properties\n");
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return -ENODEV;
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}
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smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
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if (!smmu) {
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@ -1954,6 +1996,20 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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of_iommu_set_ops(dev->of_node, &arm_smmu_ops);
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platform_set_drvdata(pdev, smmu);
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arm_smmu_device_reset(smmu);
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/* Oh, for a proper bus abstraction */
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if (!iommu_present(&platform_bus_type))
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bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
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#ifdef CONFIG_ARM_AMBA
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if (!iommu_present(&amba_bustype))
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bus_set_iommu(&amba_bustype, &arm_smmu_ops);
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#endif
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#ifdef CONFIG_PCI
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if (!iommu_present(&pci_bus_type)) {
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pci_request_acs();
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bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
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}
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#endif
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return 0;
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}
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@ -1983,41 +2039,14 @@ static struct platform_driver arm_smmu_driver = {
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static int __init arm_smmu_init(void)
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{
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struct device_node *np;
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int ret;
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static bool registered;
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int ret = 0;
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/*
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* Play nice with systems that don't have an ARM SMMU by checking that
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* an ARM SMMU exists in the system before proceeding with the driver
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* and IOMMU bus operation registration.
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*/
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np = of_find_matching_node(NULL, arm_smmu_of_match);
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if (!np)
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return 0;
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of_node_put(np);
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ret = platform_driver_register(&arm_smmu_driver);
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if (ret)
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return ret;
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/* Oh, for a proper bus abstraction */
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if (!iommu_present(&platform_bus_type))
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bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
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#ifdef CONFIG_ARM_AMBA
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if (!iommu_present(&amba_bustype))
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bus_set_iommu(&amba_bustype, &arm_smmu_ops);
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#endif
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#ifdef CONFIG_PCI
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if (!iommu_present(&pci_bus_type)) {
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pci_request_acs();
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bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
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if (!registered) {
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ret = platform_driver_register(&arm_smmu_driver);
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registered = !ret;
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}
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#endif
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return 0;
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return ret;
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}
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static void __exit arm_smmu_exit(void)
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@ -2028,6 +2057,25 @@ static void __exit arm_smmu_exit(void)
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subsys_initcall(arm_smmu_init);
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module_exit(arm_smmu_exit);
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static int __init arm_smmu_of_init(struct device_node *np)
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{
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int ret = arm_smmu_init();
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if (ret)
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return ret;
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if (!of_platform_device_create(np, NULL, platform_bus_type.dev_root))
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return -ENODEV;
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return 0;
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}
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IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1", arm_smmu_of_init);
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IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2", arm_smmu_of_init);
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IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400", arm_smmu_of_init);
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IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", arm_smmu_of_init);
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IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", arm_smmu_of_init);
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IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", arm_smmu_of_init);
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MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
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MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
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MODULE_LICENSE("GPL v2");
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