sfc: Move descriptor cache base addresses to struct efx_nic_type
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -45,11 +45,9 @@
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*/
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*/
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#define TX_DC_ENTRIES 16
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#define TX_DC_ENTRIES 16
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#define TX_DC_ENTRIES_ORDER 1
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#define TX_DC_ENTRIES_ORDER 1
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#define TX_DC_BASE 0x130000
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#define RX_DC_ENTRIES 64
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#define RX_DC_ENTRIES 64
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#define RX_DC_ENTRIES_ORDER 3
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#define RX_DC_ENTRIES_ORDER 3
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#define RX_DC_BASE 0x100000
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static const unsigned int
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static const unsigned int
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/* "Large" EEPROM device: Atmel AT25640 or similar
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/* "Large" EEPROM device: Atmel AT25640 or similar
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@ -3043,9 +3041,11 @@ int falcon_init_nic(struct efx_nic *efx)
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return rc;
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return rc;
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/* Set positions of descriptor caches in SRAM. */
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/* Set positions of descriptor caches in SRAM. */
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
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efx->type->tx_dc_base / 8);
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efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
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efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
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efx->type->rx_dc_base / 8);
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efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
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efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
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/* Set TX descriptor cache size. */
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/* Set TX descriptor cache size. */
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@ -3248,6 +3248,8 @@ struct efx_nic_type falcon_a1_nic_type = {
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.rx_buffer_padding = 0x24,
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.rx_buffer_padding = 0x24,
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.max_interrupt_mode = EFX_INT_MODE_MSI,
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.max_interrupt_mode = EFX_INT_MODE_MSI,
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.phys_addr_channels = 4,
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.phys_addr_channels = 4,
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.tx_dc_base = 0x130000,
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.rx_dc_base = 0x100000,
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};
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};
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struct efx_nic_type falcon_b0_nic_type = {
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struct efx_nic_type falcon_b0_nic_type = {
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@ -3271,5 +3273,7 @@ struct efx_nic_type falcon_b0_nic_type = {
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.phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
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.phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
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* interrupt handler only supports 32
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* interrupt handler only supports 32
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* channels */
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* channels */
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.tx_dc_base = 0x130000,
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.rx_dc_base = 0x100000,
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};
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};
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@ -857,6 +857,8 @@ static inline const char *efx_dev_name(struct efx_nic *efx)
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* from &enum efx_init_mode.
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* from &enum efx_init_mode.
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* @phys_addr_channels: Number of channels with physically addressed
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* @phys_addr_channels: Number of channels with physically addressed
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* descriptors
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* descriptors
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* @tx_dc_base: Base address in SRAM of TX queue descriptor caches
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* @rx_dc_base: Base address in SRAM of RX queue descriptor caches
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*/
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*/
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struct efx_nic_type {
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struct efx_nic_type {
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struct efx_mac_operations *default_mac_ops;
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struct efx_mac_operations *default_mac_ops;
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@ -872,6 +874,8 @@ struct efx_nic_type {
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unsigned int rx_buffer_padding;
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unsigned int rx_buffer_padding;
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unsigned int max_interrupt_mode;
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unsigned int max_interrupt_mode;
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unsigned int phys_addr_channels;
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unsigned int phys_addr_channels;
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unsigned int tx_dc_base;
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unsigned int rx_dc_base;
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};
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};
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/**************************************************************************
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/**************************************************************************
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