GPIO fix for the v4.15 series, this fixes the bit fiddling in the
MMIO GPIO driver. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJaYFB3AAoJEEEQszewGV1z+5EP/in6wDsqTAOnjim6VZs2o72G XcHbVaDpWvBBW3WWVnL6A5HcHBuP5D3YEzfSTnVBM+ClHK82DsgnwT/FlIJ1VdOo 36jQaPtdKZ5CkpQ8zG/84T8BI7wYD15PxvXGNZLQmt0b38tPVDamf+YRqfmmyd2z ilwy/xmj6zKikdc3SJUN+SBquZ2Vsceh574SWOnP36A7PSNQpirCJ4aR+iH0PxPn T6c50LbuvnWwZh1ehdnSh3K7zOBPUTFkVodpiX7jHu1Ahqe55Ld/71ywWBjF76wH rkLWGmYb5PKcGd8rtZslS+YqXstdWMAmYSFU7zRQ4ozlC07l46hd4srhl3oaElG2 fV3w3jyBNAad5Vl0ateKQhwRbbMvkfrXwmDoxU0hpoI8CdZ6COvIP9mFNcPHB1ao lJR6S0+sVhMELfrtnyD46HMt1cx5ija63W8d/yQA8bWF5NZS+jXPdGXKmddr9OPl 1RWOALBd5XmIuzNMg7ojtcKCFJxmIb3rV5s3IOR2okhoOj8+E2YddX0tdiXAX2he 54iQiYOco0TidDpLjHxzOqF/hBt9Z3M7rZsOsKi/qcfY0BmCQoE3i6aNjaVlzLJR 6+wcrBN4g5xtrEsV+jr/U2Tw6GCfM0s0vwsSFMfpbvzjxY4wKbe2si8f8r8UIvrU ln7PLQOYCCh7cvicpXn2 =7onn -----END PGP SIGNATURE----- Merge tag 'gpio-v4.15-5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO fix from Linus Walleij: "This is the (hopefully) last GPIO fix for v4.15, fixing the bit fiddling in the MMIO GPIO driver. Again the especially endowed screwer-upper who has been open coding bit fiddling is yours truly" * tag 'gpio-v4.15-5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: gpio: mmio: Also read bits that are zero
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commit
023080317d
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@ -152,14 +152,13 @@ static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
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{
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unsigned long get_mask = 0;
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unsigned long set_mask = 0;
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int bit = 0;
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while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio) {
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if (gc->bgpio_dir & BIT(bit))
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set_mask |= BIT(bit);
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else
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get_mask |= BIT(bit);
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}
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/* Make sure we first clear any bits that are zero when we read the register */
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*bits &= ~*mask;
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/* Exploit the fact that we know which directions are set */
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set_mask = *mask & gc->bgpio_dir;
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get_mask = *mask & ~gc->bgpio_dir;
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if (set_mask)
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*bits |= gc->read_reg(gc->reg_set) & set_mask;
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@ -176,13 +175,13 @@ static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
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/*
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* This only works if the bits in the GPIO register are in native endianness.
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* It is dirt simple and fast in this case. (Also the most common case.)
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*/
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static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
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unsigned long *bits)
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{
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*bits = gc->read_reg(gc->reg_dat) & *mask;
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/* Make sure we first clear any bits that are zero when we read the register */
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*bits &= ~*mask;
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*bits |= gc->read_reg(gc->reg_dat) & *mask;
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return 0;
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}
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@ -196,9 +195,12 @@ static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
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unsigned long val;
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int bit;
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/* Make sure we first clear any bits that are zero when we read the register */
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*bits &= ~*mask;
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/* Create a mirrored mask */
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bit = 0;
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while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio)
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bit = -1;
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while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio)
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readmask |= bgpio_line2mask(gc, bit);
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/* Read the register */
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@ -208,8 +210,8 @@ static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
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* Mirror the result into the "bits" result, this will give line 0
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* in bit 0 ... line 31 in bit 31 for a 32bit register.
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*/
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bit = 0;
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while ((bit = find_next_bit(&val, gc->ngpio, bit)) != gc->ngpio)
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bit = -1;
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while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio)
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*bits |= bgpio_line2mask(gc, bit);
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return 0;
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