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clk: qcom: Add APQ8084 Global Clock Controller support 

This patch adds support for the global clock controller found on
the APQ8084 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
hifive-unleashed-5.1
Georgi Djakov 2014-06-03 17:24:09 +03:00 committed by Stephen Boyd
parent 56097d8df0
commit 0282465320
5 changed files with 3399 additions and 0 deletions
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8
drivers/clk/qcom/Kconfig
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@ -4,6 +4,14 @@ config COMMON_CLK_QCOM
select REGMAP_MMIO
select RESET_CONTROLLER
config APQ_GCC_8084
tristate "APQ8084 Global Clock Controller"
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on apq8084 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, SATA, PCIe, etc.
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on COMMON_CLK_QCOM

1
drivers/clk/qcom/Makefile
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@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o
clk-qcom-y += clk-branch.o
clk-qcom-y += reset.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o

2944
drivers/clk/qcom/gcc-apq8084.c 100644
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File diff suppressed because it is too large Load Diff

337
include/dt-bindings/clock/qcom,gcc-apq8084.h 100644
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@ -0,0 +1,337 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
#define GPLL0 0
#define GPLL0_VOTE 1
#define GPLL1 2
#define GPLL1_VOTE 3
#define GPLL2 4
#define GPLL2_VOTE 5
#define GPLL3 6
#define GPLL3_VOTE 7
#define GPLL4 8
#define GPLL4_VOTE 9
#define CONFIG_NOC_CLK_SRC 10
#define PERIPH_NOC_CLK_SRC 11
#define SYSTEM_NOC_CLK_SRC 12
#define BLSP_UART_SIM_CLK_SRC 13
#define QDSS_TSCTR_CLK_SRC 14
#define UFS_AXI_CLK_SRC 15
#define RPM_CLK_SRC 16
#define KPSS_AHB_CLK_SRC 17
#define QDSS_AT_CLK_SRC 18
#define BIMC_DDR_CLK_SRC 19
#define USB30_MASTER_CLK_SRC 20
#define USB30_SEC_MASTER_CLK_SRC 21
#define USB_HSIC_AHB_CLK_SRC 22
#define MMSS_BIMC_GFX_CLK_SRC 23
#define QDSS_STM_CLK_SRC 24
#define ACC_CLK_SRC 25
#define SEC_CTRL_CLK_SRC 26
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38
#define BLSP1_UART1_APPS_CLK_SRC 39
#define BLSP1_UART2_APPS_CLK_SRC 40
#define BLSP1_UART3_APPS_CLK_SRC 41
#define BLSP1_UART4_APPS_CLK_SRC 42
#define BLSP1_UART5_APPS_CLK_SRC 43
#define BLSP1_UART6_APPS_CLK_SRC 44
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52
#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53
#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55
#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56
#define BLSP2_UART1_APPS_CLK_SRC 57
#define BLSP2_UART2_APPS_CLK_SRC 58
#define BLSP2_UART3_APPS_CLK_SRC 59
#define BLSP2_UART4_APPS_CLK_SRC 60
#define BLSP2_UART5_APPS_CLK_SRC 61
#define BLSP2_UART6_APPS_CLK_SRC 62
#define CE1_CLK_SRC 63
#define CE2_CLK_SRC 64
#define CE3_CLK_SRC 65
#define GP1_CLK_SRC 66
#define GP2_CLK_SRC 67
#define GP3_CLK_SRC 68
#define PDM2_CLK_SRC 69
#define QDSS_TRACECLKIN_CLK_SRC 70
#define RBCPR_CLK_SRC 71
#define SATA_ASIC0_CLK_SRC 72
#define SATA_PMALIVE_CLK_SRC 73
#define SATA_RX_CLK_SRC 74
#define SATA_RX_OOB_CLK_SRC 75
#define SDCC1_APPS_CLK_SRC 76
#define SDCC2_APPS_CLK_SRC 77
#define SDCC3_APPS_CLK_SRC 78
#define SDCC4_APPS_CLK_SRC 79
#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80
#define SPMI_AHB_CLK_SRC 81
#define SPMI_SER_CLK_SRC 82
#define TSIF_REF_CLK_SRC 83
#define USB30_MOCK_UTMI_CLK_SRC 84
#define USB30_SEC_MOCK_UTMI_CLK_SRC 85
#define USB_HS_SYSTEM_CLK_SRC 86
#define USB_HSIC_CLK_SRC 87
#define USB_HSIC_IO_CAL_CLK_SRC 88
#define USB_HSIC_MOCK_UTMI_CLK_SRC 89
#define USB_HSIC_SYSTEM_CLK_SRC 90
#define GCC_BAM_DMA_AHB_CLK 91
#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92
#define DDR_CLK_SRC 93
#define GCC_BIMC_CFG_AHB_CLK 94
#define GCC_BIMC_CLK 95
#define GCC_BIMC_KPSS_AXI_CLK 96
#define GCC_BIMC_SLEEP_CLK 97
#define GCC_BIMC_SYSNOC_AXI_CLK 98
#define GCC_BIMC_XO_CLK 99
#define GCC_BLSP1_AHB_CLK 100
#define GCC_BLSP1_SLEEP_CLK 101
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113
#define GCC_BLSP1_UART1_APPS_CLK 114
#define GCC_BLSP1_UART1_SIM_CLK 115
#define GCC_BLSP1_UART2_APPS_CLK 116
#define GCC_BLSP1_UART2_SIM_CLK 117
#define GCC_BLSP1_UART3_APPS_CLK 118
#define GCC_BLSP1_UART3_SIM_CLK 119
#define GCC_BLSP1_UART4_APPS_CLK 120
#define GCC_BLSP1_UART4_SIM_CLK 121
#define GCC_BLSP1_UART5_APPS_CLK 122
#define GCC_BLSP1_UART5_SIM_CLK 123
#define GCC_BLSP1_UART6_APPS_CLK 124
#define GCC_BLSP1_UART6_SIM_CLK 125
#define GCC_BLSP2_AHB_CLK 126
#define GCC_BLSP2_SLEEP_CLK 127
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135
#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136
#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137
#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138
#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139
#define GCC_BLSP2_UART1_APPS_CLK 140
#define GCC_BLSP2_UART1_SIM_CLK 141
#define GCC_BLSP2_UART2_APPS_CLK 142
#define GCC_BLSP2_UART2_SIM_CLK 143
#define GCC_BLSP2_UART3_APPS_CLK 144
#define GCC_BLSP2_UART3_SIM_CLK 145
#define GCC_BLSP2_UART4_APPS_CLK 146
#define GCC_BLSP2_UART4_SIM_CLK 147
#define GCC_BLSP2_UART5_APPS_CLK 148
#define GCC_BLSP2_UART5_SIM_CLK 149
#define GCC_BLSP2_UART6_APPS_CLK 150
#define GCC_BLSP2_UART6_SIM_CLK 151
#define GCC_BOOT_ROM_AHB_CLK 152
#define GCC_CE1_AHB_CLK 153
#define GCC_CE1_AXI_CLK 154
#define GCC_CE1_CLK 155
#define GCC_CE2_AHB_CLK 156
#define GCC_CE2_AXI_CLK 157
#define GCC_CE2_CLK 158
#define GCC_CE3_AHB_CLK 159
#define GCC_CE3_AXI_CLK 160
#define GCC_CE3_CLK 161
#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162
#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163
#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164
#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165
#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166
#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167
#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168
#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169
#define GCC_CFG_NOC_AHB_CLK 170
#define GCC_CFG_NOC_DDR_CFG_CLK 171
#define GCC_CFG_NOC_RPM_AHB_CLK 172
#define GCC_COPSS_SMMU_AHB_CLK 173
#define GCC_COPSS_SMMU_AXI_CLK 174
#define GCC_DCD_XO_CLK 175
#define GCC_BIMC_DDR_CH0_CLK 176
#define GCC_BIMC_DDR_CH1_CLK 177
#define GCC_BIMC_DDR_CPLL0_CLK 178
#define GCC_BIMC_DDR_CPLL1_CLK 179
#define GCC_BIMC_GFX_CLK 180
#define GCC_DDR_DIM_CFG_CLK 181
#define GCC_DDR_DIM_SLEEP_CLK 182
#define GCC_DEHR_CLK 183
#define GCC_AHB_CLK 184
#define GCC_IM_SLEEP_CLK 185
#define GCC_XO_CLK 186
#define GCC_XO_DIV4_CLK 187
#define GCC_GP1_CLK 188
#define GCC_GP2_CLK 189
#define GCC_GP3_CLK 190
#define GCC_IMEM_AXI_CLK 191
#define GCC_IMEM_CFG_AHB_CLK 192
#define GCC_KPSS_AHB_CLK 193
#define GCC_KPSS_AXI_CLK 194
#define GCC_LPASS_MPORT_AXI_CLK 195
#define GCC_LPASS_Q6_AXI_CLK 196
#define GCC_LPASS_SWAY_CLK 197
#define GCC_MMSS_BIMC_GFX_CLK 198
#define GCC_MMSS_NOC_AT_CLK 199
#define GCC_MMSS_NOC_CFG_AHB_CLK 200
#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201
#define GCC_OCMEM_NOC_CFG_AHB_CLK 202
#define GCC_OCMEM_SYS_NOC_AXI_CLK 203
#define GCC_MPM_AHB_CLK 204
#define GCC_MSG_RAM_AHB_CLK 205
#define GCC_NOC_CONF_XPU_AHB_CLK 206
#define GCC_PDM2_CLK 207
#define GCC_PDM_AHB_CLK 208
#define GCC_PDM_XO4_CLK 209
#define GCC_PERIPH_NOC_AHB_CLK 210
#define GCC_PERIPH_NOC_AT_CLK 211
#define GCC_PERIPH_NOC_CFG_AHB_CLK 212
#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213
#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214
#define GCC_PERIPH_XPU_AHB_CLK 215
#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216
#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217
#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218
#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219
#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220
#define GCC_PRNG_AHB_CLK 221
#define GCC_QDSS_AT_CLK 222
#define GCC_QDSS_CFG_AHB_CLK 223
#define GCC_QDSS_DAP_AHB_CLK 224
#define GCC_QDSS_DAP_CLK 225
#define GCC_QDSS_ETR_USB_CLK 226
#define GCC_QDSS_STM_CLK 227
#define GCC_QDSS_TRACECLKIN_CLK 228
#define GCC_QDSS_TSCTR_DIV16_CLK 229
#define GCC_QDSS_TSCTR_DIV2_CLK 230
#define GCC_QDSS_TSCTR_DIV3_CLK 231
#define GCC_QDSS_TSCTR_DIV4_CLK 232
#define GCC_QDSS_TSCTR_DIV8_CLK 233
#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234
#define GCC_RBCPR_AHB_CLK 235
#define GCC_RBCPR_CLK 236
#define GCC_RPM_BUS_AHB_CLK 237
#define GCC_RPM_PROC_HCLK 238
#define GCC_RPM_SLEEP_CLK 239
#define GCC_RPM_TIMER_CLK 240
#define GCC_SATA_ASIC0_CLK 241
#define GCC_SATA_AXI_CLK 242
#define GCC_SATA_CFG_AHB_CLK 243
#define GCC_SATA_PMALIVE_CLK 244
#define GCC_SATA_RX_CLK 245
#define GCC_SATA_RX_OOB_CLK 246
#define GCC_SDCC1_AHB_CLK 247
#define GCC_SDCC1_APPS_CLK 248
#define GCC_SDCC1_CDCCAL_FF_CLK 249
#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250
#define GCC_SDCC2_AHB_CLK 251
#define GCC_SDCC2_APPS_CLK 252
#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253
#define GCC_SDCC3_AHB_CLK 254
#define GCC_SDCC3_APPS_CLK 255
#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256
#define GCC_SDCC4_AHB_CLK 257
#define GCC_SDCC4_APPS_CLK 258
#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259
#define GCC_SEC_CTRL_ACC_CLK 260
#define GCC_SEC_CTRL_AHB_CLK 261
#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262
#define GCC_SEC_CTRL_CLK 263
#define GCC_SEC_CTRL_SENSE_CLK 264
#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265
#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266
#define GCC_SPDM_BIMC_CY_CLK 267
#define GCC_SPDM_CFG_AHB_CLK 268
#define GCC_SPDM_DEBUG_CY_CLK 269
#define GCC_SPDM_FF_CLK 270
#define GCC_SPDM_MSTR_AHB_CLK 271
#define GCC_SPDM_PNOC_CY_CLK 272
#define GCC_SPDM_RPM_CY_CLK 273
#define GCC_SPDM_SNOC_CY_CLK 274
#define GCC_SPMI_AHB_CLK 275
#define GCC_SPMI_CNOC_AHB_CLK 276
#define GCC_SPMI_SER_CLK 277
#define GCC_SPSS_AHB_CLK 278
#define GCC_SNOC_CNOC_AHB_CLK 279
#define GCC_SNOC_PNOC_AHB_CLK 280
#define GCC_SYS_NOC_AT_CLK 281
#define GCC_SYS_NOC_AXI_CLK 282
#define GCC_SYS_NOC_KPSS_AHB_CLK 283
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284
#define GCC_SYS_NOC_UFS_AXI_CLK 285
#define GCC_SYS_NOC_USB3_AXI_CLK 286
#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287
#define GCC_TCSR_AHB_CLK 288
#define GCC_TLMM_AHB_CLK 289
#define GCC_TLMM_CLK 290
#define GCC_TSIF_AHB_CLK 291
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292
#define GCC_TSIF_REF_CLK 293
#define GCC_UFS_AHB_CLK 294
#define GCC_UFS_AXI_CLK 295
#define GCC_UFS_RX_CFG_CLK 296
#define GCC_UFS_RX_SYMBOL_0_CLK 297
#define GCC_UFS_RX_SYMBOL_1_CLK 298
#define GCC_UFS_TX_CFG_CLK 299
#define GCC_UFS_TX_SYMBOL_0_CLK 300
#define GCC_UFS_TX_SYMBOL_1_CLK 301
#define GCC_USB2A_PHY_SLEEP_CLK 302
#define GCC_USB2B_PHY_SLEEP_CLK 303
#define GCC_USB30_MASTER_CLK 304
#define GCC_USB30_MOCK_UTMI_CLK 305
#define GCC_USB30_SLEEP_CLK 306
#define GCC_USB30_SEC_MASTER_CLK 307
#define GCC_USB30_SEC_MOCK_UTMI_CLK 308
#define GCC_USB30_SEC_SLEEP_CLK 309
#define GCC_USB_HS_AHB_CLK 310
#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311
#define GCC_USB_HS_SYSTEM_CLK 312
#define GCC_USB_HSIC_AHB_CLK 313
#define GCC_USB_HSIC_CLK 314
#define GCC_USB_HSIC_IO_CAL_CLK 315
#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316
#define GCC_USB_HSIC_MOCK_UTMI_CLK 317
#define GCC_USB_HSIC_SYSTEM_CLK 318
#endif

109
include/dt-bindings/reset/qcom,gcc-apq8084.h 100644
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@ -0,0 +1,109 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
#define _DT_BINDINGS_RESET_APQ_GCC_8084_H
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1
#define GCC_PERIPH_NOC_BCR 2
#define GCC_IMEM_BCR 3
#define GCC_MMSS_BCR 4
#define GCC_QDSS_BCR 5
#define GCC_USB_30_BCR 6
#define GCC_USB3_PHY_BCR 7
#define GCC_USB_HS_HSIC_BCR 8
#define GCC_USB_HS_BCR 9
#define GCC_USB2A_PHY_BCR 10
#define GCC_USB2B_PHY_BCR 11
#define GCC_SDCC1_BCR 12
#define GCC_SDCC2_BCR 13
#define GCC_SDCC3_BCR 14
#define GCC_SDCC4_BCR 15
#define GCC_BLSP1_BCR 16
#define GCC_BLSP1_QUP1_BCR 17
#define GCC_BLSP1_UART1_BCR 18
#define GCC_BLSP1_QUP2_BCR 19
#define GCC_BLSP1_UART2_BCR 20
#define GCC_BLSP1_QUP3_BCR 21
#define GCC_BLSP1_UART3_BCR 22
#define GCC_BLSP1_QUP4_BCR 23
#define GCC_BLSP1_UART4_BCR 24
#define GCC_BLSP1_QUP5_BCR 25
#define GCC_BLSP1_UART5_BCR 26
#define GCC_BLSP1_QUP6_BCR 27
#define GCC_BLSP1_UART6_BCR 28
#define GCC_BLSP2_BCR 29
#define GCC_BLSP2_QUP1_BCR 30
#define GCC_BLSP2_UART1_BCR 31
#define GCC_BLSP2_QUP2_BCR 32
#define GCC_BLSP2_UART2_BCR 33
#define GCC_BLSP2_QUP3_BCR 34
#define GCC_BLSP2_UART3_BCR 35
#define GCC_BLSP2_QUP4_BCR 36
#define GCC_BLSP2_UART4_BCR 37
#define GCC_BLSP2_QUP5_BCR 38
#define GCC_BLSP2_UART5_BCR 39
#define GCC_BLSP2_QUP6_BCR 40
#define GCC_BLSP2_UART6_BCR 41
#define GCC_PDM_BCR 42
#define GCC_PRNG_BCR 43
#define GCC_BAM_DMA_BCR 44
#define GCC_TSIF_BCR 45
#define GCC_TCSR_BCR 46
#define GCC_BOOT_ROM_BCR 47
#define GCC_MSG_RAM_BCR 48
#define GCC_TLMM_BCR 49
#define GCC_MPM_BCR 50
#define GCC_MPM_AHB_RESET 51
#define GCC_MPM_NON_AHB_RESET 52
#define GCC_SEC_CTRL_BCR 53
#define GCC_SPMI_BCR 54
#define GCC_SPDM_BCR 55
#define GCC_CE1_BCR 56
#define GCC_CE2_BCR 57
#define GCC_BIMC_BCR 58
#define GCC_SNOC_BUS_TIMEOUT0_BCR 59
#define GCC_SNOC_BUS_TIMEOUT2_BCR 60
#define GCC_PNOC_BUS_TIMEOUT0_BCR 61
#define GCC_PNOC_BUS_TIMEOUT1_BCR 62
#define GCC_PNOC_BUS_TIMEOUT2_BCR 63
#define GCC_PNOC_BUS_TIMEOUT3_BCR 64
#define GCC_PNOC_BUS_TIMEOUT4_BCR 65
#define GCC_CNOC_BUS_TIMEOUT0_BCR 66
#define GCC_CNOC_BUS_TIMEOUT1_BCR 67
#define GCC_CNOC_BUS_TIMEOUT2_BCR 68
#define GCC_CNOC_BUS_TIMEOUT3_BCR 69
#define GCC_CNOC_BUS_TIMEOUT4_BCR 70
#define GCC_CNOC_BUS_TIMEOUT5_BCR 71
#define GCC_CNOC_BUS_TIMEOUT6_BCR 72
#define GCC_DEHR_BCR 73
#define GCC_RBCPR_BCR 74
#define GCC_MSS_RESTART 75
#define GCC_LPASS_RESTART 76
#define GCC_WCSS_RESTART 77
#define GCC_VENUS_RESTART 78
#define GCC_COPSS_SMMU_BCR 79
#define GCC_SPSS_BCR 80
#define GCC_PCIE_0_BCR 81
#define GCC_PCIE_0_PHY_BCR 82
#define GCC_PCIE_1_BCR 83
#define GCC_PCIE_1_PHY_BCR 84
#define GCC_USB_30_SEC_BCR 85
#define GCC_USB3_SEC_PHY_BCR 86
#define GCC_SATA_BCR 87
#define GCC_CE3_BCR 88
#define GCC_UFS_BCR 89
#define GCC_USB30_PHY_COM_BCR 90
#endif