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drm: rcar-du: lvds: Fix LVDS clock frequency range 

According to the latest versions of both the Gen2 and Gen3 datasheets,
the operating range for the LVDS clock is 31 MHz to 148.5 MHz on all
SoCs. Update the driver accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
hifive-unleashed-5.1
Laurent Pinchart 2018-01-12 16:17:36 +02:00
parent 3e5907a17f
commit 02f0aaaaf0
1 changed files with 2 additions and 8 deletions
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10
drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
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@ -201,17 +201,11 @@ int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
struct drm_display_mode *mode)
{
struct rcar_du_device *rcdu = lvds->dev;
/*
* The internal LVDS encoder has a restricted clock frequency operating
* range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp
* the clock accordingly.
* range (31MHz to 148.5MHz). Clamp the clock accordingly.
*/
if (rcdu->info->gen < 3)
mode->clock = clamp(mode->clock, 30000, 150000);
else
mode->clock = clamp(mode->clock, 25175, 148500);
mode->clock = clamp(mode->clock, 31000, 148500);
}
void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,