drm/amd/pp: Add smu irq handlers for legacy asics
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3998,8 +3998,35 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
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PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
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PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
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}
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}
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static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
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.process = phm_irq_process,
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};
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static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
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static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
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{
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{
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struct amdgpu_irq_src *source =
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kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
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if (!source)
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return -ENOMEM;
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source->funcs = &smu7_irq_funcs;
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amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
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AMDGPU_IH_CLIENTID_LEGACY,
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230,
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source);
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amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
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AMDGPU_IH_CLIENTID_LEGACY,
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231,
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source);
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/* Register CTF(GPIO_19) interrupt */
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amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
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AMDGPU_IH_CLIENTID_LEGACY,
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83,
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source);
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return 0;
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return 0;
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}
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}
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