mmc: dw_mmc: add dw_mmc-k3 for k3 platform
Add dw_mmc-k3.c for k3v2, support sd/emmc Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Zhigang Wang <brooke.wangzhigang@huawei.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chris Ball <chris@printf.net>hifive-unleashed-5.1
Zhangfei Gao
Chris Ball
parent
bf626e5550
commit
036f29d554
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@ -0,0 +1,60 @@
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* Hisilicon specific extensions to the Synopsys Designware Mobile
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Storage Host Controller
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Read synopsys-dw-mshc.txt for more details
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The Synopsys designware mobile storage host controller is used to interface
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a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
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differences between the core Synopsys dw mshc controller properties described
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by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
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extensions to the Synopsys Designware Mobile Storage Host Controller.
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Required Properties:
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* compatible: should be one of the following.
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- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extentions.
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* clock-freq-table: should be the frequency (in Hz) array of the ciu clock
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in each supported mode.
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0. CIU clock rate in Hz for DS mode
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1. CIU clock rate in Hz for MMC HS mode
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2. CIU clock rate in Hz for SD HS mode
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3. CIU clock rate in Hz for SDR12 mode
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4. CIU clock rate in Hz for SDR25 mode
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5. CIU clock rate in Hz for SDR50 mode
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6. CIU clock rate in Hz for SDR104 mode
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7. CIU clock rate in Hz for DDR50 mode
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8. CIU clock rate in Hz for HS200 mode
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Example:
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/* for Hi3620 */
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/* SoC portion */
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dwmmc_0: dwmmc0@fcd03000 {
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compatible = "hisilicon,hi4511-dw-mshc";
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reg = <0xfcd03000 0x1000>;
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interrupts = <0 16 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
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clock-names = "ciu", "biu";
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clock-freq-table =
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<25000000 0 50000000 25000000 50000000 100000000 0 50000000>;
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};
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/* Board portion */
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dwmmc0@fcd03000 {
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num-slots = <1>;
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vmmc-supply = <&ldo12>;
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fifo-depth = <0x100>;
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supports-highspeed;
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pinctrl-names = "default";
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pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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disable-wp;
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cd-gpios = <&gpio10 3 0>;
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};
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};
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@ -576,6 +576,16 @@ config MMC_DW_SOCFPGA
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This selects support for Altera SoCFPGA specific extensions to the
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Synopsys DesignWare Memory Card Interface driver.
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config MMC_DW_K3
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tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
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depends on MMC_DW
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select MMC_DW_PLTFM
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select MMC_DW_IDMAC
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help
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This selects support for Hisilicon K3 SoC specific extensions to the
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on Hisilicon K3 SoC's.
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config MMC_DW_PCI
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tristate "Synopsys Designware MCI support on PCI bus"
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depends on MMC_DW && PCI
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@ -44,6 +44,7 @@ obj-$(CONFIG_MMC_DW) += dw_mmc.o
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obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o
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obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o
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obj-$(CONFIG_MMC_DW_SOCFPGA) += dw_mmc-socfpga.o
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obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
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obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
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obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
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@ -0,0 +1,132 @@
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/*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (c) 2013 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/of_address.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define MAX_NUMS 10
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struct dw_mci_k3_priv_data {
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u32 clk_table[MAX_NUMS];
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};
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static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_k3_priv_data *priv = host->priv;
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u32 rate = priv->clk_table[ios->timing];
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int ret;
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if (!rate) {
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dev_warn(host->dev,
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"no specified rate in timing %u\n", ios->timing);
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return;
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}
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ret = clk_set_rate(host->ciu_clk, rate);
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if (ret)
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dev_warn(host->dev, "failed to set clock rate %uHz\n", rate);
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host->bus_hz = clk_get_rate(host->ciu_clk);
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}
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static int dw_mci_k3_parse_dt(struct dw_mci *host)
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{
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struct dw_mci_k3_priv_data *priv;
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struct device_node *node = host->dev->of_node;
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struct property *prop;
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const __be32 *cur;
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u32 val, num = 0;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(host->dev, "mem alloc failed for private data\n");
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return -ENOMEM;
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}
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host->priv = priv;
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of_property_for_each_u32(node, "clock-freq-table", prop, cur, val) {
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if (num >= MAX_NUMS)
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break;
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priv->clk_table[num++] = val;
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}
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return 0;
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}
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static const struct dw_mci_drv_data k3_drv_data = {
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.set_ios = dw_mci_k3_set_ios,
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.parse_dt = dw_mci_k3_parse_dt,
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};
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static const struct of_device_id dw_mci_k3_match[] = {
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{ .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_k3_match);
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static int dw_mci_k3_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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match = of_match_node(dw_mci_k3_match, pdev->dev.of_node);
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drv_data = match->data;
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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static int dw_mci_k3_suspend(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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int ret;
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ret = dw_mci_suspend(host);
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if (!ret)
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clk_disable_unprepare(host->ciu_clk);
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return ret;
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}
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static int dw_mci_k3_resume(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(host->ciu_clk);
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if (ret) {
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dev_err(host->dev, "failed to enable ciu clock\n");
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return ret;
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}
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return dw_mci_resume(host);
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}
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SIMPLE_DEV_PM_OPS(dw_mci_k3_pmops, dw_mci_k3_suspend, dw_mci_k3_resume);
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static struct platform_driver dw_mci_k3_pltfm_driver = {
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.probe = dw_mci_k3_probe,
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.remove = dw_mci_pltfm_remove,
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.driver = {
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.name = "dwmmc_k3",
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.of_match_table = dw_mci_k3_match,
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.pm = &dw_mci_k3_pmops,
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},
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};
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module_platform_driver(dw_mci_k3_pltfm_driver);
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MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dwmmc-k3");
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