Topic branch for Device Tree changes for Exynos 3250 for v4.7:
Merge necessary new clocks from Sylwester (used by new board) and add support for Exynos3250-based Artik5 board. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXDgugAAoJEME3ZuaGi4PX8JIP/0UmBC5FLJLgzFRgzVcGvwjS nzLRcIqwQ7i/ztT3r3kUndjrHLQAqWRynrNdq0w+W+DYGVEYEToBfVbqdVezJ9i+ XgfeXvUU/k+4aZHpsrcl6ZST7MD6UQn9qSLB1R3Y4zHVw68gldNPMtDNpyrQJutu 440+vd5fKZxmcEx8exAIon4AEnPXsDkom2YQTd4NfeKmVHxsfJsv3Irj3DcRrcYV StCp7n1UhZmEP3pAhOhyGx6XmU/Qrl4iYZtSwpmDC5PwAt8dHQ8b4Z/N+uP8Ghas jCaNTA+z9mKdTyNNdLAefWeIddhCTp1eAdzoV5znBAIDjpGBqZjWKbq77v1m2NqU jSmY+m/UpexNnC5b5eYJbjU+l85VhXECog3qjCUjuJtj+nib95icYM536WhTzhRf ZEZ/NZyU5ReO10bTYr+YTb4O/iz+SMzfghGvs2HXpVk4X89utG7HUqcYg6zCQIWz 4sL8JGAhq1bmzzgnS+8km2ZpRD6gmssB+2tG16nJk0tJFplHzU9Wr46Q/ttMeg9I d2GK/sE9EFooQH+fqoQmi1aNKb3fEJlUIvqpxfTeFbhnRpOCCfaIq+U9bmg9JxdG HuZuEO0ClNFyQN8TBUNmzZL5XzYGPUksbVWyVc4VuZ0PNEXLeMsyzCUmgrLEPQEU EzgObFNrzaouu8QN3rii =mQfO -----END PGP SIGNATURE----- Merge tag 'samsung-dt-exynos3250-artik5-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt Merge "Topic branch for Device Tree changes for Exynos 3250 for v4.7" from Krzysztof Kozlowski: Merge necessary new clocks from Sylwester (used by new board) and add support for Exynos3250-based Artik5 board. * tag 'samsung-dt-exynos3250-artik5-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add MSHC2 DT node for SD card for exynos3250-artik5-eval board ARM: dts: exynos: Add exynos3250-artik5 dtsi file for ARTIK5 module ARM: dts: exynos: Add MSHC2 DT node for Exynos3250 SoC ARM: dts: exynos: Add UART2 DT node for Exynos3250 SoC ARM: dts: exynos: Add initial gpio setting of MMC2 device for exynos3250-monk ARM: dts: exynos: Add initial pin configuration for exynos3250-rinato clk: samsung: exynos3250: Add MMC2 clock clk: samsung: exynos3250: Add UART2 clock dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250hifive-unleashed-5.1
Arnd Bergmann
commit
036f8d0635
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@ -2,6 +2,8 @@
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Required root node properties:
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- compatible = should be one or more of the following.
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- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
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- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
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- "samsung,monk" - for Exynos3250-based Samsung Simband board.
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- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
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- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
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@ -112,6 +112,7 @@ dtb-$(CONFIG_ARCH_DIGICOLOR) += \
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dtb-$(CONFIG_ARCH_EFM32) += \
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efm32gg-dk3750.dtb
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dtb-$(CONFIG_ARCH_EXYNOS3) += \
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exynos3250-artik5-eval.dtb \
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exynos3250-monk.dtb \
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exynos3250-rinato.dtb
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dtb-$(CONFIG_ARCH_EXYNOS4) += \
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@ -0,0 +1,43 @@
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/*
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* Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Device tree source file for Samsung's ARTIK5 evaluation board
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* which is based on Samsung Exynos3250 SoC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "exynos3250-artik5.dtsi"
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/ {
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model = "Samsung ARTIK5 evaluation board";
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compatible = "samsung,artik5-eval", "samsung,artik5",
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"samsung,exynos3250", "samsung,exynos3";
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};
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&mshc_2 {
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num-slots = <1>;
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cap-sd-highspeed;
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disable-wp;
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vqmmc-supply = <&ldo3_reg>;
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card-detect-delay = <200>;
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clock-frequency = <100000000>;
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clock-freq-min-max = <400000 100000000>;
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samsung,dw-mshc-ciu-div = <1>;
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samsung,dw-mshc-sdr-timing = <0 1>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
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bus-width = <4>;
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status = "okay";
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};
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&serial_2 {
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status = "okay";
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};
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@ -0,0 +1,334 @@
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/*
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* Samsung's Exynos3250 based ARTIK5 module device tree source
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Device tree source file for Samsung's ARTIK5 module which is based on
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* Samsung Exynos3250 SoC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos3250.dtsi"
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#include <dt-bindings/clock/samsung,s2mps11.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
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chosen {
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stdout-path = &serial_2;
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};
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memory {
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reg = <0x40000000 0x1ff00000>;
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};
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firmware@0205f000 {
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compatible = "samsung,secure-firmware";
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reg = <0x0205f000 0x1000>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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cooling-maps {
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map0 {
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/* Corresponds to 500MHz */
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cooling-device = <&cpu0 5 5>;
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};
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map1 {
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/* Corresponds to 200MHz */
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cooling-device = <&cpu0 8 8>;
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};
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};
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};
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};
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};
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&adc {
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vdd-supply = <&ldo7_reg>;
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assigned-clocks = <&cmu CLK_SCLK_TSADC>;
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assigned-clock-rates = <6000000>;
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};
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&cpu0 {
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cpu0-supply = <&buck2_reg>;
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};
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&i2c_0 {
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,i2c-sda-delay = <100>;
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samsung,i2c-slave-addr = <0x10>;
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samsung,i2c-max-bus-freq = <100000>;
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status = "okay";
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s2mps14_pmic@66 {
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compatible = "samsung,s2mps14-pmic";
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interrupt-parent = <&gpx3>;
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interrupts = <5 IRQ_TYPE_NONE>;
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reg = <0x66>;
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s2mps14_osc: clocks {
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compatible = "samsung,s2mps14-clk";
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#clock-cells = <1>;
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clock-output-names = "s2mps14_ap", "unused",
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"s2mps14_bt";
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};
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regulators {
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ldo1_reg: LDO1 {
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/* VDD_ALIVE15x */
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regulator-name = "VLDO1_1.0V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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ldo2_reg: LDO2 {
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/* VDDQM176 ~ VDDQM185 */
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regulator-name = "VLDO2_1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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ldo3_reg: LDO3 {
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/*
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* VDD1_E106 ~ VDD1_E111
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* DVDD_RTC_AP, DVDD_MMC2_AP
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*/
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regulator-name = "VLDO3_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo4_reg: LDO4 {
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/* AVDD_PLL1120 ~ AVDD_PLL11201 */
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regulator-name = "VLDO4_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo5_reg: LDO5 {
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/* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */
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regulator-name = "VLDO5_1.0V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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ldo6_reg: LDO6 {
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/* VDD_USB, VDD10_HSIC */
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regulator-name = "VLDO6_1.0V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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ldo7_reg: LDO7 {
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/*
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* VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2,
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* AVDD_ADC, AVDD_ABB_0, M4S_VDD18
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*/
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regulator-name = "VLDO7_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo8_reg: LDO8 {
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/* AVDD33_UOTG */
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regulator-name = "VLDO8_3.0V";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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ldo9_reg: LDO9 {
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/* VDDQ_E86 ~ VDDQ_E105*/
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regulator-name = "VLDO9_1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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ldo10_reg: LDO10 {
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regulator-name = "VLDO10_1.0V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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};
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ldo11_reg: LDO11 {
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/* VDD74 ~ VDD75 */
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regulator-name = "VLDO11_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
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};
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ldo12_reg: LDO12 {
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/* VDD72 ~ VDD73 */
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regulator-name = "VLDO12_2.8V";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
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};
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ldo13_reg: LDO13 {
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regulator-name = "VLDO13_2.8V";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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ldo14_reg: LDO14 {
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regulator-name = "VLDO14_2.7V";
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <2700000>;
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};
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ldo15_reg: LDO15 {
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regulator-name = "VLDO_3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo16_reg: LDO16 {
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regulator-name = "VLDO16_3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo17_reg: LDO17 {
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regulator-name = "VLDO17_3.0V";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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};
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ldo18_reg: LDO18 {
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/* DVDD_MMC2_AP */
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regulator-name = "VLDO18_2.8V";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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ldo19_reg: LDO19 {
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regulator-name = "VLDO19_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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ldo20_reg: LDO20 {
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regulator-name = "VLDO20_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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ldo21_reg: LDO21 {
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regulator-name = "VLDO21_1.25V";
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regulator-min-microvolt = <1250000>;
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regulator-max-microvolt = <1250000>;
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};
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ldo22_reg: LDO22 {
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regulator-name = "VLDO22_1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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ldo23_reg: LDO23 {
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/* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */
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regulator-name = "VLDO23_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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ldo24_reg: LDO24 {
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regulator-name = "VLDO24_3.0V";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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};
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ldo25_reg: LDO25 {
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regulator-name = "VLDO25_3.0V";
|
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
|
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};
|
||||
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buck1_reg: BUCK1 {
|
||||
/* VDD_MIF */
|
||||
regulator-name = "VBUCK1_1.0V";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1000000>;
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regulator-always-on;
|
||||
};
|
||||
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buck2_reg: BUCK2 {
|
||||
/* VDD_CPU */
|
||||
regulator-name = "VBUCK2_1.2V";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1200000>;
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regulator-always-on;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
/* VDD_G3D */
|
||||
regulator-name = "VBUCK3_1.0V";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
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regulator-always-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "VBUCK4_1.95V";
|
||||
regulator-min-microvolt = <1950000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "VBUCK5_1.35V";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mshc_0 {
|
||||
num-slots = <1>;
|
||||
non-removable;
|
||||
cap-mmc-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
vmmc-supply = <&ldo12_reg>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-freq-min-max = <400000 100000000>;
|
||||
samsung,dw-mshc-ciu-div = <1>;
|
||||
samsung,dw-mshc-sdr-timing = <0 1>;
|
||||
samsung,dw-mshc-ddr-timing = <1 2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
|
||||
clock-names = "rtc", "rtc_src";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xusbxti {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
|
@ -558,7 +558,17 @@
|
|||
|
||||
&pinctrl_1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sleep1>;
|
||||
pinctrl-0 = <&initial1 &sleep1>;
|
||||
|
||||
initial1: initial-state {
|
||||
PIN_IN(gpk2-0, DOWN, LV1);
|
||||
PIN_IN(gpk2-1, DOWN, LV1);
|
||||
PIN_IN(gpk2-2, DOWN, LV1);
|
||||
PIN_IN(gpk2-3, DOWN, LV1);
|
||||
PIN_IN(gpk2-4, DOWN, LV1);
|
||||
PIN_IN(gpk2-5, DOWN, LV1);
|
||||
PIN_IN(gpk2-6, DOWN, LV1);
|
||||
};
|
||||
|
||||
sleep1: sleep-state {
|
||||
PIN_SLP(gpe0-0, PREV, NONE);
|
||||
|
|
|
|||
|
|
@ -16,11 +16,49 @@
|
|||
#define PIN_PULL_DOWN 1
|
||||
#define PIN_PULL_UP 3
|
||||
|
||||
#define PIN_DRV_LV1 0
|
||||
#define PIN_DRV_LV2 2
|
||||
#define PIN_DRV_LV3 1
|
||||
#define PIN_DRV_LV4 3
|
||||
|
||||
#define PIN_PDN_OUT0 0
|
||||
#define PIN_PDN_OUT1 1
|
||||
#define PIN_PDN_INPUT 2
|
||||
#define PIN_PDN_PREV 3
|
||||
|
||||
#define PIN_IN(_pin, _pull, _drv) \
|
||||
_pin { \
|
||||
samsung,pins = #_pin; \
|
||||
samsung,pin-function = <0>; \
|
||||
samsung,pin-pud = <PIN_PULL_ ##_pull>; \
|
||||
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
|
||||
}
|
||||
|
||||
#define PIN_OUT(_pin, _drv) \
|
||||
_pin { \
|
||||
samsung,pins = #_pin; \
|
||||
samsung,pin-function = <1>; \
|
||||
samsung,pin-pud = <0>; \
|
||||
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
|
||||
}
|
||||
|
||||
#define PIN_OUT_SET(_pin, _val, _drv) \
|
||||
_pin { \
|
||||
samsung,pins = #_pin; \
|
||||
samsung,pin-function = <1>; \
|
||||
samsung,pin-pud = <0>; \
|
||||
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
|
||||
samsung,pin-val = <_val>; \
|
||||
}
|
||||
|
||||
#define PIN_CFG(_pin, _sel, _pull, _drv) \
|
||||
_pin { \
|
||||
samsung,pins = #_pin; \
|
||||
samsung,pin-function = <_sel>; \
|
||||
samsung,pin-pud = <PIN_PULL_ ##_pull>; \
|
||||
samsung,pin-drv = <PIN_DRV_ ##_drv>; \
|
||||
}
|
||||
|
||||
#define PIN_SLP(_pin, _mode, _pull) \
|
||||
_pin { \
|
||||
samsung,pins = #_pin; \
|
||||
|
|
@ -120,6 +158,13 @@
|
|||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
uart2_data: uart2-data {
|
||||
samsung,pins = "gpa1-0", "gpa1-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
i2c3_bus: i2c3-bus {
|
||||
samsung,pins = "gpa1-2", "gpa1-3";
|
||||
samsung,pin-function = <3>;
|
||||
|
|
@ -445,6 +490,41 @@
|
|||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_clk: sd2-clk {
|
||||
samsung,pins = "gpk2-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_cmd: sd2-cmd {
|
||||
samsung,pins = "gpk2-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_cd: sd2-cd {
|
||||
samsung,pins = "gpk2-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_bus1: sd2-bus-width1 {
|
||||
samsung,pins = "gpk2-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
sd2_bus4: sd2-bus-width4 {
|
||||
samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
};
|
||||
|
||||
cam_port_b_io: cam-port-b-io {
|
||||
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
|
||||
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
|
||||
|
|
|
|||
|
|
@ -681,7 +681,21 @@
|
|||
|
||||
&pinctrl_0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sleep0>;
|
||||
pinctrl-0 = <&initial0 &sleep0>;
|
||||
|
||||
initial0: initial-state {
|
||||
PIN_IN(gpa1-4, DOWN, LV1);
|
||||
PIN_IN(gpa1-5, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpc0-0, DOWN, LV1);
|
||||
PIN_IN(gpc0-1, DOWN, LV1);
|
||||
PIN_IN(gpc0-2, DOWN, LV1);
|
||||
PIN_IN(gpc0-3, DOWN, LV1);
|
||||
PIN_IN(gpc0-4, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpd0-0, DOWN, LV1);
|
||||
PIN_IN(gpd0-1, DOWN, LV1);
|
||||
};
|
||||
|
||||
sleep0: sleep-state {
|
||||
PIN_SLP(gpa0-0, INPUT, DOWN);
|
||||
|
|
@ -735,7 +749,60 @@
|
|||
|
||||
&pinctrl_1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sleep1>;
|
||||
pinctrl-0 = <&initial1 &sleep1>;
|
||||
|
||||
initial1: initial-state {
|
||||
PIN_IN(gpe0-6, DOWN, LV1);
|
||||
PIN_IN(gpe0-7, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpe1-0, DOWN, LV1);
|
||||
PIN_IN(gpe1-3, DOWN, LV1);
|
||||
PIN_IN(gpe1-4, DOWN, LV1);
|
||||
PIN_IN(gpe1-5, DOWN, LV1);
|
||||
PIN_IN(gpe1-6, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpk2-0, DOWN, LV1);
|
||||
PIN_IN(gpk2-1, DOWN, LV1);
|
||||
PIN_IN(gpk2-2, DOWN, LV1);
|
||||
PIN_IN(gpk2-3, DOWN, LV1);
|
||||
PIN_IN(gpk2-4, DOWN, LV1);
|
||||
PIN_IN(gpk2-5, DOWN, LV1);
|
||||
PIN_IN(gpk2-6, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpm0-0, DOWN, LV1);
|
||||
PIN_IN(gpm0-1, DOWN, LV1);
|
||||
PIN_IN(gpm0-2, DOWN, LV1);
|
||||
PIN_IN(gpm0-3, DOWN, LV1);
|
||||
PIN_IN(gpm0-4, DOWN, LV1);
|
||||
PIN_IN(gpm0-5, DOWN, LV1);
|
||||
PIN_IN(gpm0-6, DOWN, LV1);
|
||||
PIN_IN(gpm0-7, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpm1-0, DOWN, LV1);
|
||||
PIN_IN(gpm1-1, DOWN, LV1);
|
||||
PIN_IN(gpm1-2, DOWN, LV1);
|
||||
PIN_IN(gpm1-3, DOWN, LV1);
|
||||
PIN_IN(gpm1-4, DOWN, LV1);
|
||||
PIN_IN(gpm1-5, DOWN, LV1);
|
||||
PIN_IN(gpm1-6, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpm2-0, DOWN, LV1);
|
||||
PIN_IN(gpm2-1, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpm3-0, DOWN, LV1);
|
||||
PIN_IN(gpm3-1, DOWN, LV1);
|
||||
PIN_IN(gpm3-2, DOWN, LV1);
|
||||
PIN_IN(gpm3-3, DOWN, LV1);
|
||||
PIN_IN(gpm3-4, DOWN, LV1);
|
||||
|
||||
PIN_IN(gpm4-1, DOWN, LV1);
|
||||
PIN_IN(gpm4-2, DOWN, LV1);
|
||||
PIN_IN(gpm4-3, DOWN, LV1);
|
||||
PIN_IN(gpm4-4, DOWN, LV1);
|
||||
PIN_IN(gpm4-5, DOWN, LV1);
|
||||
PIN_IN(gpm4-6, DOWN, LV1);
|
||||
PIN_IN(gpm4-7, DOWN, LV1);
|
||||
};
|
||||
|
||||
sleep1: sleep-state {
|
||||
PIN_SLP(gpe0-0, PREV, NONE);
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
pinctrl1 = &pinctrl_1;
|
||||
mshc0 = &mshc_0;
|
||||
mshc1 = &mshc_1;
|
||||
mshc2 = &mshc_2;
|
||||
spi0 = &spi_0;
|
||||
spi1 = &spi_1;
|
||||
i2c0 = &i2c_0;
|
||||
|
|
@ -43,6 +44,7 @@
|
|||
i2c7 = &i2c_7;
|
||||
serial0 = &serial_0;
|
||||
serial1 = &serial_1;
|
||||
serial2 = &serial_2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -357,6 +359,18 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mshc_2: mshc@12530000 {
|
||||
compatible = "samsung,exynos5250-dw-mshc";
|
||||
reg = <0x12530000 0x1000>;
|
||||
interrupts = <0 144 0>;
|
||||
clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
exynos_usbphy: exynos-usbphy@125B0000 {
|
||||
compatible = "samsung,exynos3250-usb2-phy";
|
||||
reg = <0x125B0000 0x100>;
|
||||
|
|
@ -452,6 +466,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial_2: serial@13820000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 111 0>;
|
||||
clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_data>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_0: i2c@13860000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -302,10 +302,12 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
|
|||
|
||||
/* SRC_FSYS */
|
||||
MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
|
||||
MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
|
||||
MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
|
||||
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
|
||||
|
||||
/* SRC_PERIL0 */
|
||||
MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
|
||||
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
|
||||
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
|
||||
|
||||
|
|
@ -389,7 +391,13 @@ static struct samsung_div_clock div_clks[] __initdata = {
|
|||
CLK_SET_RATE_PARENT, 0),
|
||||
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
|
||||
|
||||
/* DIV_FSYS2 */
|
||||
DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
|
||||
|
||||
/* DIV_PERIL0 */
|
||||
DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
|
||||
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
|
||||
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
|
||||
|
||||
|
|
@ -538,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
|
|||
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
|
||||
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
|
||||
GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
|
||||
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
|
||||
|
|
@ -552,6 +562,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
|
|||
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
|
||||
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
|
||||
GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
|
||||
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
|
||||
|
|
@ -630,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
|
|||
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
|
||||
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
|
||||
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
|
||||
GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
|
||||
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
|
||||
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
|
||||
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
|
||||
|
|
@ -649,6 +663,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
|
|||
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
|
||||
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
|
||||
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
|
||||
GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
|
||||
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
|
||||
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -79,6 +79,8 @@
|
|||
#define CLK_MOUT_CORE 58
|
||||
#define CLK_MOUT_APLL 59
|
||||
#define CLK_MOUT_ACLK_266_SUB 60
|
||||
#define CLK_MOUT_UART2 61
|
||||
#define CLK_MOUT_MMC2 62
|
||||
|
||||
/* Dividers */
|
||||
#define CLK_DIV_GPL 64
|
||||
|
|
@ -127,6 +129,9 @@
|
|||
#define CLK_DIV_CORE 107
|
||||
#define CLK_DIV_HPM 108
|
||||
#define CLK_DIV_COPY 109
|
||||
#define CLK_DIV_UART2 110
|
||||
#define CLK_DIV_MMC2_PRE 111
|
||||
#define CLK_DIV_MMC2 112
|
||||
|
||||
/* Gates */
|
||||
#define CLK_ASYNC_G3D 128
|
||||
|
|
@ -223,6 +228,8 @@
|
|||
#define CLK_BLOCK_MFC 219
|
||||
#define CLK_BLOCK_CAM 220
|
||||
#define CLK_SMIES 221
|
||||
#define CLK_UART2 222
|
||||
#define CLK_SDMMC2 223
|
||||
|
||||
/* Special clocks */
|
||||
#define CLK_SCLK_JPEG 224
|
||||
|
|
@ -249,12 +256,14 @@
|
|||
#define CLK_SCLK_SPI0 245
|
||||
#define CLK_SCLK_UART1 246
|
||||
#define CLK_SCLK_UART0 247
|
||||
#define CLK_SCLK_UART2 248
|
||||
#define CLK_SCLK_MMC2 249
|
||||
|
||||
/*
|
||||
* Total number of clocks of main CMU.
|
||||
* NOTE: Must be equal to last clock ID increased by one.
|
||||
*/
|
||||
#define CLK_NR_CLKS 248
|
||||
#define CLK_NR_CLKS 250
|
||||
|
||||
/*
|
||||
* CMU DMC
|
||||
|
|
|
|||
Loading…
Reference in New Issue