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arm: dts: allwinner: H3: Add PMU node 

Add the Performance Monitoring Unit (PMU) device tree node to the H3
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core. The numbers come from the manual and have
been checked in U-Boot and with perf in Linux.

Tested with perf record and taskset on an OrangePi Zero.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
alistair/sensors
Andre Przywara 2019-11-21 01:18:35 +00:00 committed by Maxime Ripard
parent c35a516a46
commit 0388a11074
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 12 additions and 3 deletions
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15
arch/arm/boot/dts/sun8i-h3.dtsi
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@ -80,7 +80,7 @@
#cooling-cells = <2>;
};
cpu@1 {
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
@ -90,7 +90,7 @@
#cooling-cells = <2>;
};
cpu@2 {
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
@ -100,7 +100,7 @@
#cooling-cells = <2>;
};
cpu@3 {
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
@ -111,6 +111,15 @@
};
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,