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MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels. 

The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64
so we change its type to unsigned long.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10644/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Markos Chandras 2015-07-09 10:40:45 +01:00 committed by Ralf Baechle
parent c0b584a269
commit 038b0f536e
1 changed files with 1 additions and 1 deletions
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2
arch/mips/kernel/mips-cm.c
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@ -20,7 +20,7 @@ int mips_cm_is64;
phys_addr_t __mips_cm_phys_base(void)
{
u32 config3 = read_c0_config3();
u32 cmgcr;
unsigned long cmgcr;
/* Check the CMGCRBase register is implemented */
if (!(config3 & MIPS_CONF3_CMGCR))